20 results about "Spurious-free dynamic range" patented technology

The present application relates to a kind of pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, belong to analog integrated circuit technical field.After the residual error signal is obtained in the first stage SAR ADC quantization, pseudo-random sequence is injected in the residual error signal, the superimposed signal is sampled and converted by the later stage ADC, finally cause nonlinear error in digital code output code, then the sequence input and digital output code are correlated to obtain the error information of non-ideal factor in circuit, finally the actual interstage gain value in circuit is approximated by variable step iterative algorithm for digital code reconstruction analog signal, finally reach the effect of calibration.The present application can avoid the influence of step on speed and accuracy in iterative process, be used to calibrate the interstage gain error caused by capacitor mismatch and the limited gain of operational amplifier, and in the iterative process of calibration, better speed and accuracy are realized, the performance of ADC is obviously improved, and signal-to-noise ratio and spurious-free dynamic range are improved.

The invention relates to the field of receivers, and provides a method, a device, equipment and a medium for improving the spurious-free dynamic range of a receiver, and the method comprises the steps: carrying out the sliding FFT operation of data after AD quantization, and obtaining a signal amplitude; counting the maximum value of the amplitude of one frame of signal; comparing the maximum value of the amplitude of one frame of signal with a saturation threshold; obtaining a selection detection threshold according to a comparison result; and comparing the detection threshold with the signal amplitude to obtain a detected signal. According to the method, when the signal amplitude exceeds the saturation threshold, the signals are detected through multi-threshold control, so that signals with larger amplitude can be effectively detected, spurious signals are removed, the spurious-free dynamic range of a receiver is widened, and the system hardware complexity is not increased.

A long-distance frequency-expanded distributed optical fiber sensing system and sensing method, comprising: a narrow-linewidth laser, an optical fiber isolator, a dense wavelength division multiplexer, an optical fiber coupler, a continuous optical amplifier, a narrowband filter, an acousto-optic modulator, an optical fiber circulator, a balanced detector, an acquisition card, and a host computer. By selecting the narrow-linewidth laser and controlling an arbitrary waveform generator, a mode-division multiplexed pulse sequence is obtained. After the pulse sequence enters the optical fiber to be measured, a Rayleigh backscattered light will be returned. After beating with the local light, the original data of the system is obtained. Subsequently, a compensation method is used to demodulate the signal, and the unwanted signals are suppressed successively, solving the problem of limited spurious-free dynamic range caused by phase mismatch of different modes.

This invention discloses a dual passive noise shaping and correction method for high-precision successive approximation ADCs. It combines noise shaping technology with a correction algorithm. Within a short period after chip power-on, using a limited correction DAC capacitor array and noise shaping technology, it achieves higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage. In normal operating mode, this invention again incorporates noise shaping technology, adding the correction codes to the main DAC in analog form, reducing the impact of non-ideal factors. This invention reuses sampling integration capacitors, resulting in a simple structure. With minimal power consumption, it significantly improves correction accuracy and increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby enhancing the overall efficiency of the SAR ADC.

The present application relates to a kind of full differential lissajous frequency modulation MEMS gyroscopes, comprising: gyroscopic sensing unit, differential interface unit;Gyroscopic sensing unit, for generating resonance state in response to control signal, and angular rate signal is obtained in resonance state, first signal and second signal are obtained by differentially processing angular rate signal, and first signal and second signal are sent to differential interface unit;Differential interface unit, for providing control signal to gyroscopic sensing unit, and the first signal and second signal received are subjected to difference frequency harmonic filtering processing and synchronous demodulation processing, filter out the interference signal existing in first signal and second signal, obtain the angular rate signal without interference.The method can eliminate the influence of interference signal on detection accuracy, widen the usable bandwidth and the unspurious dynamic range of lissajous frequency modulation MEMS gyroscope, greatly improve the detection accuracy of lissajous frequency modulation MEMS gyroscope.

The application discloses a digital-to-analog converter and a current calibration device and method thereof, the current calibration method comprising: comparing the output current of a to-be-calibrated current source of the digital-to-analog converter with the output current of a reference current source and outputting an error signal; generating a calibration control code according to the error signal by using a successive approximation algorithm; and controlling a calibration current source to inject corresponding compensation current into the to-be-calibrated current source according to the calibration control code, wherein at least one redundant bit is included in the calibration bits of the calibration control code, and the value of the redundant bit is a positive integer less than N, wherein N is the number of calibration precision bits. The successive approximation algorithm with the redundant bit is adopted, even if a single misjudgment occurs during calibration, the previous error can be corrected in subsequent low-bit calibration, and the calibration stability and calibration precision are significantly improved. Further, the gradient alignment algorithm is adopted, so that the output current of the calibrated current source presents staggered distribution, and the linearity and the spurious-free dynamic range of the signal can be improved.

The invention belongs to the field of ADC digital calibration, particularly relates to a pipeline ADC residual network calibration method based on a genetic algorithm, and aims to solve the problem that the performance of a pipeline ADC is reduced due to coexistence of various errors such as capacitor mismatch and comparator imbalance, and the defects that a traditional calibration method is poor in adaptability and poor in nonlinear error calibration capability. The method comprises the following steps: firstly, constructing a multi-frequency noisy analog signal and inputting the multi-frequency noisy analog signal into a to-be-calibrated pipeline ADC to obtain a data sample; taking a spurious-free dynamic range as an evaluation function, iteratively solving an optimal error compensation value of each data sample through a genetic algorithm, and further constructing a training data set; and training a residual network by using the data set, finally performing error compensation on a to-be-detected sample through a trained model, and outputting a calibrated signal. The method does not need to depend on the details of the internal architecture of the ADC, can process various linear and nonlinear errors at the same time, remarkably improves the key indexes such as the spurious-free dynamic range and the significant digits of the ADC, is high in adaptability and generalization ability, and provides an efficient and flexible technical scheme for the calibration of the high-speed and high-precision pipeline ADC.

The invention discloses a TIADC sampling time mismatch error estimation and calibration method, and belongs to the technical field of high-speed data acquisition and real-time transmission. According to the method, high-precision time error estimation is realized in a mode of combining improved first-order statistics and LMS adaptive filtering, dynamic correction is carried out by adopting a parallel Farrow fractional delay filter based on Lagrange interpolation, and a sub-ADC is used for sampling a difference value between a signal and an ideal signal and derivative information in an error estimation stage. A time mismatch initial estimation value is calculated through improved first-order statistics, the estimation value is iteratively optimized through an LMS algorithm, dynamic error tracking is achieved, optimized error parameters are input into an improved parallel Farrow filter, and K sub-filter banks are generated through a multi-phase decomposition structure. According to the invention, the spurious-free dynamic range and significant digits of the TIADC system are significantly improved, and the TIADC system is suitable for high-frequency signal acquisition scenes such as 5G communication and radar.

The present application relates to the field of microwave photonics, and more particularly to a high linearity microwave photonics down-conversion receiving system based on an optoelectronic oscillator. The system comprises a laser, a first phase modulator, a first optical amplifier, a phase-shifted Bragg grating, a first photodetector, a second phase modulator, an optical filter, a second optical amplifier, and a second photodetector. The frequency of the local oscillator signal generated by the first photodetector can be tuned by changing the frequency of the laser, thereby effectively realizing the tuning of the down-converted signal output by the second photodetector. By adjusting the gain value of the first optical amplifier, the amplitude of the local oscillator spectral harmonic in the output optical signal of the first phase modulator is a specific value, thereby realizing the suppression of the third-order intermodulation distortion in the output signal, and further improving the spurious-free dynamic range of the entire down-conversion receiving system. The system has reconfigurability and high linearity, and can play a technical value in the field of radar and communication applications.

The application discloses a receiver spurious dynamic cancellation system and method, and provides the receiver spurious dynamic cancellation method which can inhibit the in-band spurious signal generated by the internal phase source of the system to a certain extent, and significantly improves the spurious-free dynamic range of the receiver in a complex electromagnetic environment; without extracting the phase of the spurious signal, the phase of the spurious signal is finally determined through iterative cancellation operation by giving different initial phases to the cancellation signals, so that the algorithm is simplified, and logic resources are saved; the method can be realized based on a simple signal processing and a generated digital signal processing algorithm without additional complex system hardware; the method consumes less resources, does not need additional configuration of AD chips and DA chips, and does not generate additional pressure on the FPGA processing time sequence and resources; the dynamic adjustment can be performed at any time when the temperature and time change, so that the method is not affected by the change of the external environment.

An analog-to-digital conversion circuit introducing white noise is characterized in that a combining module is arranged, the first input end of the combining module obtains analog signals, the second input end of the combining module is connected with an amplifying and filtering module, and the input end of the amplifying and filtering module is connected with a noise source module; the output end group of the combining module is connected with a digital filtering module through an analog-to-digital converter (ADC), and the digital filtering module outputs a digital signal; a first input end of the combining module is connected with a positive end of a pre-stage winding of the mutual inductor T1 after acquiring an analog signal, and a second input end of the combining module is connected with the positive end of the pre-stage winding of the mutual inductor T1 through a high-pass filter after acquiring a noise signal from the amplifying and filtering circuit; the positive end of the post-stage winding of the mutual inductor T1 is connected with the first input end of the ADC through a resistor R3, and the negative end of the post-stage winding of the mutual inductor T1 is connected with the second input end of the ADC through a resistor R2. The method has the advantages that the small signal conversion capacity of the integrated ADC chip is improved, and the spurious-free dynamic range index of the system is improved; a high-performance ADC chip does not need to be purchased, so that the cost is saved.

The application relates to the technical field of receiving radio frequency front ends, and discloses a super-high-blocking-sensitivity super-short-wave multi-channel parallel receiving radio frequency front end. After sampling processing of sampling data, a target analog-to-digital converter turns on corresponding channel selection input switches and channel selection output switches according to the type of the sampled radio frequency signals, so as to select a suitable radio frequency signal processing branch to be accessed, to perform low-noise amplification and large-signal attenuation processing on the radio frequency signals, and to ensure that the radio frequency signals entering the target analog-to-digital converter are within the target analog-to-digital converter's spurious-free dynamic range, thus getting rid of the narrow-band signal processing capability in the traditional superheterodyne signal architecture. The advantage lies in that, through the frequency conversion effect of a mixing circuit, interference is mixed to zero frequency or is pulled away from useful signals. For zero-frequency signals, the interference can be suppressed through a blocking capacitor, and the frequency multiplication of the interference signals can be suppressed through a low-pass filter, so that the function of only suppressing interference signals without deteriorating useful signals is realized, and the dynamic range of the receiving front end is improved.

The invention relates to a double-path time domain interleaving return-to-zero system applied to a digital-to-analog converter, which is characterized in that in a time domain interleaving parallel processing stage, a high-speed data stream is decomposed into four paths of low-rate parallel signals to be processed, so that the working frequency and the time sequence design difficulty of a rear-end digital logic circuit are remarkably reduced, and the reliability of the digital-to-analog converter is improved. The limitation of a digital system on the overall conversion rate of the digital-to-analog converter is effectively broken through; in a signal synthesis stage, a zero returning technology is introduced through a multiplexer unit, and four paths of low-rate parallel signals are combined into a double-path time domain interleaving zero returning signal, so that intersymbol interference caused by incomplete establishment of a switch transient process and a current source is inhibited, transient error energy introduced in a switch switching process is pushed to a high-frequency region, and the signal quality is improved. The spurious-free dynamic range of the digital-to-analog converter in the Nyquist range is expanded; according to the invention, the double-time-domain interleaving return-to-zero signal is designed to reserve wide time for the full establishment of the output signal, and the integrity and high linearity of the output signal are ensured while the dynamic error is effectively eliminated.

The application relates to an unsigned error compensation device and method. The device comprises a field programmable logic gate array, the field programmable logic gate array comprising a phase accumulation unit, a dither signal generation unit and an unsigned error shaping module; the phase accumulation unit is used for generating complete phase data according to a clock signal and sending the phase data to the unsigned error shaping module; the unsigned error shaping module is used for splitting the phase data into integer part data and truncated decimal part data, and is also used for performing unsigned error compensation calculation according to a dither signal output by the dither signal generation unit, the decimal part data and historical error data, outputting a compensation signal used for correcting the integer part data, and determining a compensated phase address according to the compensation signal. The device can simplify the hardware structure, effectively suppress output spectrum stray caused by phase truncation and improve the signal non-spur dynamic range.

The invention belongs to the technical field of positioning, and relates to an STM32-based miniaturized low-power-consumption calling beacon machine and a search and rescue system. According to the invention, the hardware combination of the AD9364 chip, the STM32F103 low-power-consumption ARM chip and the FPGA is adopted, and the sleep state control design is matched, so that the electric quantity loss in the standby and invalid communication process of the beacon machine is effectively reduced, and the low-power-consumption operation is realized; the endurance time of the equipment is longer than 48 hours, the 12-hour golden rescue period of maritime search and rescue is fully covered, and the problem that the rescue opportunity is missed due to the fact that a traditional beacon machine is too high in power consumption and not timely in electric quantity supplement is thoroughly solved. By adopting the BPSK modulation mode, a complex modulation-demodulation circuit is not needed, the hardware design difficulty is reduced, and the anti-noise performance, the spectrum utilization rate and the communication stability are remarkably improved; the problem that the signal-to-noise ratio and the spurious-free dynamic range are deteriorated due to the fact that the AD / DA radio frequency front end is affected by clock jitter, power noise and electromagnetic interference is effectively solved.

The application discloses a kind of self-adapting method, device, medium and system of expanding ADC spurious-free dynamic range, belong to the field of expanding ADC spurious-free dynamic range, including steps: under limited processing resources, through multiplication and FFT operation, the spurious-free dynamic range of ADC in digital receiver is expanded.The method of the application only increases multiplication and FFT operation logic, and the processing resource is very little, so that the spurious-free dynamic range of ADC can be expanded, and the expansion capacity can be customized according to the dynamic range requirement of digital receiver, and is suitable for online adaptive real-time processing of signal.

The application relates to a capacitor mismatch foreground calibration method suitable for a SARADC, wherein the capacitor mismatch foreground calibration method comprises the following steps: S1, inputting an analog input signal, a random dithering signal and a dynamic element into a capacitor type digital-to-analog converter; S2, comparing the output of the capacitor type digital-to-analog converter with a reference point through a comparator, and storing the obtained output digital code; S3, calculating the evaluation value of the corresponding output digital code; S4, obtaining the error between the actual output value and the evaluation value of the reference output value; S5, using an LMS algorithm to iteratively adjust the capacitor weight and the random signal according to the error size; and S6, continuously adjusting the capacitor weight and the random signal so that the error is within the allowable range, and more accurate output is obtained. The application does not need to increase an additional analog circuit for capacitor mismatch calibration, and obviously improves the effective bit number and the spur-free dynamic range and other parameters of the ADC.

The application claims a segmented R-2R inverting ladder resistor network with high spurious-free dynamic range, which improves the spurious-free dynamic range (SFDR) of the circuit by segmenting the R-2R inverting ladder resistor network and performing non-overlapping rotation selection processing on the high-bit segment resistor network. The circuit mainly comprises: a thermometer decoder for converting a high-4-bit binary code into a 15-level thermometer code; an accumulator for accumulating the high-4-bit binary code to generate a shift control signal (also called a pointer) required by a logarithmic shifter; a logarithmic shifter for performing a shift operation according to the shift control signal input by the accumulator and the thermometer code input; a level holding circuit for compensating for the level lost during the shift operation of the logarithmic shifter; a latch for time-domain alignment of the signals of the low-12-bit and high-4-bit; and a segmented R-2R inverting ladder resistor network for receiving the digital signal of the latch and then decoding the digital signal.

The application discloses a Sigma Delta ADC digital calibration circuit based on analog domain dithering randomization injection, which comprises a transcoder, an adder, DWA selection logic, a switch matrix, an analog domain dithering injection module and a random number generator; the transcoder is used for converting a temperature code into a binary code; the adder is used for accumulating the input binary code and generating an element pointer; the DWA selection logic module is used for outputting a switch matrix control signal according to the element pointer to control the on-off of the switch matrix; the switch matrix is used for outputting the temperature code with rearranged positions to an external circuit; the random number generator is used for generating a single-bit random control signal; and the analog domain dithering injection module is used for generating a random dithering signal according to the single-bit random control signal. By inputting the random dithering signal at the input end of the multi-bit quantizer, the application can avoid the periodic cycle sequence of the circuit in the extreme case, eliminate the harmonics generated at the input in the extreme case, and realize a higher unmodulated dynamic range.

The application provides a second-order passive noise shaping successive approximation register analog-to-digital converter, a noise shaping method, equipment and a computer readable storage medium. In each conversion period, a timing control circuit controls a capacitive digital-to-analog conversion circuit to perform voltage sampling of the current conversion period according to the conversion result of the previous conversion period, and generates an output voltage that successively approximates the voltage to be measured based on the sampled voltage, until the residual voltage of the current conversion period is generated. During this period, on the one hand, a multi-input comparator performs conversion output according to the output voltage of the capacitive digital-to-analog conversion circuit and the integral voltage of the previous conversion period output by the passive loop filter circuit, to obtain the conversion result of the current conversion period, and on the other hand, the residual sampling unit collects the residual voltage of the current conversion period, and then charges the first integral unit and the second integral unit successively to obtain the integral voltage of the current conversion period, which is used for conversion output in the next conversion period. In this way, the KT / C noise and gain loss during residual sampling can be eliminated, the comparator noise is reduced, the signal-to-noise ratio and the spur-free dynamic range of the analog-to-digital converter are improved, and in addition, the power consumption and design complexity of the entire analog-to-digital converter are low due to the use of passive filtering.