7 results about "Spurious-free dynamic range" patented technology

This invention discloses a dual passive noise shaping and correction method for high-precision successive approximation ADCs. It combines noise shaping technology with a correction algorithm. Within a short period after chip power-on, using a limited correction DAC capacitor array and noise shaping technology, it achieves higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage. In normal operating mode, this invention again incorporates noise shaping technology, adding the correction codes to the main DAC in analog form, reducing the impact of non-ideal factors. This invention reuses sampling integration capacitors, resulting in a simple structure. With minimal power consumption, it significantly improves correction accuracy and increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby enhancing the overall efficiency of the SAR ADC.

The application discloses a digital-to-analog converter and a current calibration device and method thereof, the current calibration method comprising: comparing the output current of a to-be-calibrated current source of the digital-to-analog converter with the output current of a reference current source and outputting an error signal; generating a calibration control code according to the error signal by using a successive approximation algorithm; and controlling a calibration current source to inject corresponding compensation current into the to-be-calibrated current source according to the calibration control code, wherein at least one redundant bit is included in the calibration bits of the calibration control code, and the value of the redundant bit is a positive integer less than N, wherein N is the number of calibration precision bits. The successive approximation algorithm with the redundant bit is adopted, even if a single misjudgment occurs during calibration, the previous error can be corrected in subsequent low-bit calibration, and the calibration stability and calibration precision are significantly improved. Further, the gradient alignment algorithm is adopted, so that the output current of the calibrated current source presents staggered distribution, and the linearity and the spurious-free dynamic range of the signal can be improved.

The invention belongs to the field of ADC digital calibration, particularly relates to a pipeline ADC residual network calibration method based on a genetic algorithm, and aims to solve the problem that the performance of a pipeline ADC is reduced due to coexistence of various errors such as capacitor mismatch and comparator imbalance, and the defects that a traditional calibration method is poor in adaptability and poor in nonlinear error calibration capability. The method comprises the following steps: firstly, constructing a multi-frequency noisy analog signal and inputting the multi-frequency noisy analog signal into a to-be-calibrated pipeline ADC to obtain a data sample; taking a spurious-free dynamic range as an evaluation function, iteratively solving an optimal error compensation value of each data sample through a genetic algorithm, and further constructing a training data set; and training a residual network by using the data set, finally performing error compensation on a to-be-detected sample through a trained model, and outputting a calibrated signal. The method does not need to depend on the details of the internal architecture of the ADC, can process various linear and nonlinear errors at the same time, remarkably improves the key indexes such as the spurious-free dynamic range and the significant digits of the ADC, is high in adaptability and generalization ability, and provides an efficient and flexible technical scheme for the calibration of the high-speed and high-precision pipeline ADC.

The present application relates to the field of microwave photonics, and more particularly to a high linearity microwave photonics down-conversion receiving system based on an optoelectronic oscillator. The system comprises a laser, a first phase modulator, a first optical amplifier, a phase-shifted Bragg grating, a first photodetector, a second phase modulator, an optical filter, a second optical amplifier, and a second photodetector. The frequency of the local oscillator signal generated by the first photodetector can be tuned by changing the frequency of the laser, thereby effectively realizing the tuning of the down-converted signal output by the second photodetector. By adjusting the gain value of the first optical amplifier, the amplitude of the local oscillator spectral harmonic in the output optical signal of the first phase modulator is a specific value, thereby realizing the suppression of the third-order intermodulation distortion in the output signal, and further improving the spurious-free dynamic range of the entire down-conversion receiving system. The system has reconfigurability and high linearity, and can play a technical value in the field of radar and communication applications.

The invention relates to a double-path time domain interleaving return-to-zero system applied to a digital-to-analog converter, which is characterized in that in a time domain interleaving parallel processing stage, a high-speed data stream is decomposed into four paths of low-rate parallel signals to be processed, so that the working frequency and the time sequence design difficulty of a rear-end digital logic circuit are remarkably reduced, and the reliability of the digital-to-analog converter is improved. The limitation of a digital system on the overall conversion rate of the digital-to-analog converter is effectively broken through; in a signal synthesis stage, a zero returning technology is introduced through a multiplexer unit, and four paths of low-rate parallel signals are combined into a double-path time domain interleaving zero returning signal, so that intersymbol interference caused by incomplete establishment of a switch transient process and a current source is inhibited, transient error energy introduced in a switch switching process is pushed to a high-frequency region, and the signal quality is improved. The spurious-free dynamic range of the digital-to-analog converter in the Nyquist range is expanded; according to the invention, the double-time-domain interleaving return-to-zero signal is designed to reserve wide time for the full establishment of the output signal, and the integrity and high linearity of the output signal are ensured while the dynamic error is effectively eliminated.

The invention belongs to the technical field of positioning, and relates to an STM32-based miniaturized low-power-consumption calling beacon machine and a search and rescue system. According to the invention, the hardware combination of the AD9364 chip, the STM32F103 low-power-consumption ARM chip and the FPGA is adopted, and the sleep state control design is matched, so that the electric quantity loss in the standby and invalid communication process of the beacon machine is effectively reduced, and the low-power-consumption operation is realized; the endurance time of the equipment is longer than 48 hours, the 12-hour golden rescue period of maritime search and rescue is fully covered, and the problem that the rescue opportunity is missed due to the fact that a traditional beacon machine is too high in power consumption and not timely in electric quantity supplement is thoroughly solved. By adopting the BPSK modulation mode, a complex modulation-demodulation circuit is not needed, the hardware design difficulty is reduced, and the anti-noise performance, the spectrum utilization rate and the communication stability are remarkably improved; the problem that the signal-to-noise ratio and the spurious-free dynamic range are deteriorated due to the fact that the AD / DA radio frequency front end is affected by clock jitter, power noise and electromagnetic interference is effectively solved.

The application claims a segmented R-2R inverting ladder resistor network with high spurious-free dynamic range, which improves the spurious-free dynamic range (SFDR) of the circuit by segmenting the R-2R inverting ladder resistor network and performing non-overlapping rotation selection processing on the high-bit segment resistor network. The circuit mainly comprises: a thermometer decoder for converting a high-4-bit binary code into a 15-level thermometer code; an accumulator for accumulating the high-4-bit binary code to generate a shift control signal (also called a pointer) required by a logarithmic shifter; a logarithmic shifter for performing a shift operation according to the shift control signal input by the accumulator and the thermometer code input; a level holding circuit for compensating for the level lost during the shift operation of the logarithmic shifter; a latch for time-domain alignment of the signals of the low-12-bit and high-4-bit; and a segmented R-2R inverting ladder resistor network for receiving the digital signal of the latch and then decoding the digital signal.