Two-way time domain interleaving return-to-zero system applied to digital-to-analog converter

By designing a dual-channel time-domain interleaved return-to-zero system, high-speed data streams are processed and time-domain interleaved return-to-zero signals are generated. This solves the problems of inter-symbol interference and dynamic error in high-speed digital-to-analog converters, achieving a synchronous improvement in conversion rate and dynamic performance, and ensuring the integrity and high linearity of the output signal.

CN121966562APending Publication Date: 2026-05-01SOUTHEAST UNIV
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Patent Information

Application Number
CN202511762478.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-11-27
Publication Date
2026-05-01

AI Technical Summary

Technical Problem

High-speed digital-to-analog converters are affected by switching transients and incomplete current source establishment at high conversion rates, leading to inter-symbol interference and dynamic errors, which limit performance improvement.

Method used

Design a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters. The system processes high-speed data streams through a 4:2 multiplexer and decoding circuit to generate two time-domain interleaved return-to-zero signals. The system then controls the output of the digital-to-analog converter to output analog differential current through a drive circuit, thereby suppressing inter-symbol interference and transient errors.

Benefits of technology

It significantly improves the spurious-free dynamic range of the digital-to-analog converter within the Nyquist range, reduces the difficulty of operating the digital logic circuit at the required frequency, and ensures the integrity and high linearity of the output signal.

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Abstract

The invention relates to a double-path time domain interleaving return-to-zero system applied to a digital-to-analog converter, which is characterized in that in a time domain interleaving parallel processing stage, a high-speed data stream is decomposed into four paths of low-rate parallel signals to be processed, so that the working frequency and the time sequence design difficulty of a rear-end digital logic circuit are remarkably reduced, and the reliability of the digital-to-analog converter is improved. The limitation of a digital system on the overall conversion rate of the digital-to-analog converter is effectively broken through; in a signal synthesis stage, a zero returning technology is introduced through a multiplexer unit, and four paths of low-rate parallel signals are combined into a double-path time domain interleaving zero returning signal, so that intersymbol interference caused by incomplete establishment of a switch transient process and a current source is inhibited, transient error energy introduced in a switch switching process is pushed to a high-frequency region, and the signal quality is improved. The spurious-free dynamic range of the digital-to-analog converter in the Nyquist range is expanded; according to the invention, the double-time-domain interleaving return-to-zero signal is designed to reserve wide time for the full establishment of the output signal, and the integrity and high linearity of the output signal are ensured while the dynamic error is effectively eliminated.
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