TIADC sampling time mismatch error estimation and calibration method

Abstract

The invention discloses a TIADC sampling time mismatch error estimation and calibration method, and belongs to the technical field of high-speed data acquisition and real-time transmission. According to the method, high-precision time error estimation is realized in a mode of combining improved first-order statistics and LMS adaptive filtering, dynamic correction is carried out by adopting a parallel Farrow fractional delay filter based on Lagrange interpolation, and a sub-ADC is used for sampling a difference value between a signal and an ideal signal and derivative information in an error estimation stage. A time mismatch initial estimation value is calculated through improved first-order statistics, the estimation value is iteratively optimized through an LMS algorithm, dynamic error tracking is achieved, optimized error parameters are input into an improved parallel Farrow filter, and K sub-filter banks are generated through a multi-phase decomposition structure. According to the invention, the spurious-free dynamic range and significant digits of the TIADC system are significantly improved, and the TIADC system is suitable for high-frequency signal acquisition scenes such as 5G communication and radar.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-speed data acquisition and real-time transmission, and particularly relates to a TIADC sampling time mismatch error estimation and calibration method. BACKGROUND

[0002] With the continuous progress of integrated circuit technology and the rapid development of high-end application fields such as autonomous driving and 5G communication, the data processing system puts forward higher requirements on the number of channels and conversion precision of external signal acquisition. As the core bridge connecting the analog world and the digital world, the analog-to-digital converter (ADC) undertakes the key data conversion task. In the scene of high-speed sampling and signal processing, the traditional single ADC has gradually been unable to meet the growing demand for data throughput and precision. Limited by the current process level, the sampling rate of ADC has approached the physical limit. In the design of ADC, sampling speed and conversion precision are two key performance indicators, but there is an inherent trade-off between them, and a single ADC cannot balance high speed and high precision.

[0003] The problem of mismatch error often occurs in the application of TIADC (Time-Interleaved Analog-to-Digital Converter). Mismatch error refers to the phenomenon that the system output signal deviates from the ideal characteristics due to the inconsistency between multiple parallel sub-ADC channels. This inconsistency will introduce additional noise and distortion, which seriously affects the dynamic performance and precision of the system. For example, gain mismatch will cause different amplification of input signals in different channels; clock mismatch will cause sampling time offset, resulting in signal phase distortion; offset mismatch will cause different DC bias voltages of sub-ADCs, resulting in the superposition of fixed DC components and reducing the signal-to-noise ratio. The mismatch problem will introduce additional harmonic distortion and noise components, leading to the reduction of signal-to-noise ratio and the reduction of spurious-free dynamic range, and thus limiting its application potential in data acquisition scenarios requiring high sampling rate and high quantization precision.

[0004] For the channel mismatch error calibration problem in TIADC system, the existing methods mainly include the following categories: the foreground calibration algorithm has faster processing speed and higher calibration accuracy, but it depends on static characteristic parameters, and it is difficult to cope with dynamic errors caused by environmental changes (such as temperature drift, device aging, etc.), so the application scene is limited; the calibration method based on adaptive blind equalization can compensate for errors without prior knowledge, but it is mainly suitable for low-frequency signals, and its support capability for high-frequency applications is limited, and its hardware implementation complexity is high; the reference channel method estimates and compensates errors by introducing an additional sampling channel, although the implementation is relatively intuitive, but its performance is highly dependent on the matching accuracy of the reference channel and the target channel, and the convergence speed is limited by the ADC resolution, which is difficult to meet the needs of high-precision scenes; the calibration strategy based on injected reference signal can realize online calibration, but the stability and high-fidelity requirements of the reference signal are high, and the system design is complex. SUMMARY

[0005] The present application aims to provide a TIADC sampling time mismatch error estimation and calibration method, which solves the existing problems through the following technical means, including:

[0006] (1) PXIe Gen3 x4 channel is adopted to realize 1GB / s theoretical bandwidth, which meets the demand of high-speed data transmission;

[0007] (2) The improved first-order statistics + LMS iterative time error estimation algorithm is adopted to estimate the time error, and this algorithm can realize system time mismatch error estimation with smaller time and calculation overhead;

[0008] (3) The improved Farrow structure fractional delay filter based on Lagrange interpolation is used to correct the time error;

[0009] (4) The DMA engine and the hardware flow control mechanism are optimized to reduce the CPU load.

[0010] The present application discloses a TIADC sampling time mismatch error estimation and calibration method, which is used for background correction of TIADC system with sampling time mismatch. The TIADC system includes M ADCs, and the M ADCs correspond to M channels. For an input signal x(t), the sampling output of the mth sub-channel can be represented as:

[0011] x m [n]=x(nMT s +mT s +Δt m )

[0012] Where T s is the sampling interval.

[0013] Under the small error assumption (Δtm Very small), and m Perform a first-order Taylor expansion on [n]:

[0014] x m [n]≈x(nMT s +mT s )+Δt m ·x′(nMT s +mT s )

[0015] where x(nMT s +mT s ) is the ideal sample value without mismatch, is the derivative of the signal (which can be computed by a digital difference approximation).

[0016] e m [n]=x m [n]-x ideal [n]

[0017] Combining the Taylor expansion, we have:

[0018] e m [n]≈Δt m ·x′(nMT s +mT s )

[0019] The traditional first-order statistics (e.g., mean) cannot directly estimate the timing error, but we can exploit the derivative correlation to extract Δt m , and compute the correlation between e m [n] and the derivative x'(nMT s +mT s ):

[0020] E[e m (n)·x'(nMT s +mT s )]≈e[Δt m ·(x'(nMT s +mT s )) 2 ]

[0021] Since Δt m is a constant, we can extract:

[0022]

[0023] The numerator measures the linear correlation between the error signal and the derivative signal, and the denominator is the power of the derivative signal, used for normalization.

[0024] The improved first-order statistics provide an initial estimate, but may be affected by noise. The LMS algorithm further optimizes Δt by gradient descent. m The purpose of defining the cost function is to make the compensated output y[n] as close to the ideal signal as possible:

[0025]

[0026] The mean square error (MSE) is:

[0027] J=E[(y[n]-x(nMT s +mT s )) 2 ]

[0028] About J Find the gradient:

[0029]

[0030] e[n]=y[n]-x(nMT s +mT s )

[0031] Take the instantaneous gradient approximation and substitute it into the gradient expression:

[0032]

[0033] Among them, μ is the step size (learning rate), which controls the convergence speed, e[n] is the error at the current moment, and x'(nMT s +mT s ) is the derivative signal (gradient direction), from which the time error can be estimated.

[0034] For a TIADC system with M channels of time mismatch error, e is the time error When its discrete Fourier transform is multiplied by the ideal frequency response, The error caused by time mismatch can be eliminated by using an all-pass filter. Since the coefficients of an all-pass filter are infinite, it is almost impossible to implement it using an FPGA. Instead, a digital delay chain method is used, that is, an FIR (finite impulse response) filter is used to approximate the infinite impulse response of the all-pass filter. The filter coefficients are then combined according to similar terms using Lagrange interpolation, dividing the entire filter into multiple sub-filters. The coefficients of the sub-filters are first calculated, and then the outputs of the sub-filters are multiplied by the degree of the similar terms. The accumulated results complete the function of the variable coefficient filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0036] Figure 1 A brief flow chart of a TIADC sampling time mismatch error estimation and calibration method in an embodiment of the application;

[0037] Figure 2 A principle block diagram of calibration by Lagrange interpolation in an embodiment of the application;

[0038] Figure 3 A flow chart of a TIADC sampling time mismatch error estimation and calibration method in an embodiment of the application. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solutions in the specification, the technical solutions in the specification will be described in detail and completely below with reference to the drawings in the embodiments. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative efforts should fall within the protection scope of the application.

[0040] One embodiment of the specification provides a TIADC sampling time mismatch error estimation and calibration method, Figure 1 A brief flow chart of a TIADC sampling time mismatch error extraction and calibration method proposed for embodiment 1, which is used for background correction of a TIADC system with sampling time mismatch.

[0041] It should be noted that the method is performed under the condition that the offset mismatch and gain mismatch have been calibrated. If the offset mismatch and gain mismatch exist, the offset mismatch and gain mismatch should be calibrated first, and then the time mismatch is calibrated by using the method.

[0042] The method can be summarized as follows: first, input signal sampling is performed, then ideal sampling point calculation is performed, error signal calculation is performed, digital difference calculation signal reciprocal is performed, improved first-order statistical quantity estimation initial time error is performed, and finally LMS adaptive iteration optimization is performed to output the final time error estimation.

[0043] Then, the FIR structure based all-pass filter approximation method is used to discretize the infinite impulse response (IIR) system through Lagrange interpolation polynomial. The specific implementation scheme uses polyphase decomposition technology to expand the prototype filter into a plurality of order-related sub-filter groups according to the transfer function. On the operation architecture, the coefficients of each sub-filter are calculated independently, and then based on the polynomial order sorting, the linear combination of the sub-filter outputs is realized through weighted accumulation, and finally a time-varying digital filter system with programmable coefficient characteristics is constructed.

[0044] Each coefficient of the FIR filter is approximated by a p-order polynomial, and then brought into the transfer function of the Farrow fractional delay filter to obtain:

[0045]

[0046] Wherein, C p (z) is the coefficient of the Farrow structure filter, and in actual application, p=3-5 can meet the accuracy requirement.

[0047] The biggest advantage of this structure is that when the estimation error value changes, since the structure and coefficients of the filter are irrelevant to the phase error size of the sampling signal, it is not necessary to recalculate, but only to change the size of a. The coefficients of the Farrow filter are calculated by using the Lagrange interpolation algorithm. The output after the interpolation filtering of the N-order Farrow structure filter is:

[0048]

[0049] According to a, the like terms are combined, and the coefficients of the filter can be obtained through simplification.

[0050] Since the TIADC is time-sharing sampling, the error estimation is also extracted in sequence, so the Farrow filter can be multiplexed multiple times to reduce resource waste.

[0051] The filter structure is simple, the whole filter structure is k+1 direct type FIR filter multiplied by delay a and added, and the resource occupation is small.

[0052] The above describes the specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different than the order in which the embodiments are described, and still achieve the intended results. In addition, the processes shown in the figures do not necessarily require the particular order or sequential order shown or to achieve the intended results. In some embodiments, multitasking and parallel processing are possible or advantageous.

[0053] The above merely provides one or more examples of the present specification, and is not intended to limit the present specification. One of ordinary skill in the art can make various modifications and changes to one or more examples of the present specification. Any modification, equivalent replacement or improvement made within the spirit and principle of the present specification shall be included in the scope of claims of the present specification.

Claims

1. A TIADC sampling time mismatch error estimation and calibration method, characterized in that: The method comprises: improving time error adaptive estimation of first-order statistics, LMS iterative time error estimation, and parallel Farrow fractional delay filter; The improved first-order statistic time error adaptive estimation is combined with the LMS iterative time error estimation, which only requires first-order statistics (mean) and LMS iteration, without matrix operations or complex spectrum analysis. The LMS algorithm supports online calibration, is applicable to dynamically changing signal environments, and has low dependence on the input signal type. The LMS iterative time error estimation uses an LMS adaptive filtering algorithm to iteratively optimize the initial estimate and dynamically update the accurate estimate of the time mismatch error; The optimized time mismatch error parameters are input into the improved parallel Farrow fractional delay filter to generate the delay compensation signal of each sub-channel. The compensated sub-channel signals are synchronously synthesized through weighted accumulation to output the corrected high-precision sampling signal.

2. The method according to claim 1, characterized in that The specific implementation of the time error adaptive estimation algorithm of the improved first-order statistics includes: Output signal x to each sub-ADC m [n] The difference e between the ideal sampled signal x_ideal m [n] Perform first-order moment statistics and use the sliding window method to update the statistics to achieve real-time error extraction.

3. A TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: The parallel Farrow fractional delay filter; The parallel Farrow fractional delay filter, in which the Farrow structure achieves sub-sample fractional delay through polynomial approximation, has significantly higher accuracy than traditional interpolation methods. The improved parallel Farrow filter supports independent correction of multiple channels, reduces hardware resource usage, and updates the filter coefficients in real time to adapt to the time-varying error estimation of the LMS output.

4. The method according to claim 1, wherein The LMS iteration time error estimate: The LMS iterative time error estimation can track time-varying time mismatches caused by temperature drift, circuit aging, etc. in real time by iteratively updating the time error estimate value without interrupting the sampling process. LMS uses instantaneous gradient approximation and only requires multiplication and addition operations, avoiding matrix inversion or complex statistical calculations. It is suitable for FPGA hardware implementation. Farrow filters require sub-sampling period level (such as ps level) delay adjustment, and the continuous fine-tuning capability of LMS is a perfect match for this.

5. The method according to claim 1 or 3, characterized in that The variable coefficient filter structure: The FIR filter approximates the infinite impulse response of the all-pass filter, and then uses the Lagrange interpolation method to merge the filter coefficients according to similar terms, dividing the entire filter into multiple sub-filters. The coefficients of the sub-filters are first calculated, and then the outputs of the sub-filters are multiplied in order according to the degree of the similar terms, and then accumulated to complete the function of the variable coefficient filter; The biggest advantage of this structure is that when the estimated error value changes, since the structure and coefficients of the filter are independent of the phase error of the sampling signal, there is no need to recalculate, only the size of a needs to be changed.

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