36results about How to "Improve spurious-free dynamic range" patented technology

The invention provides a pipelined successive approximation analog-to-digital converter and a conversion method. The pipelined successive approximation analog-to-digital converter comprises a first-stage successive approximation analog-to-digital conversion module, a second-stage successive approximation analog-to-digital conversion module and a digital code error correction logic module, whereinthe first-stage successive approximation analog-to-digital conversion module comprises a first capacitor array unit, an amplification unit, a latch comparison unit, a first register logic control unitand a control switch, and the amplification unit is multiplexed as a residual amplifier and a pre-amplifier of a comparator in the first-stage successive approximation analog-to-digital converter. Bymultiplexing the residual amplifier pre-amplifier, input offset voltage mismatch existing between the residual amplifier pre-amplifier and the residual amplifier pre-amplifier is completely eliminated, the input swing of the residual amplifier is stabilized, the linearity of the residual amplifier is improved, and the area of a chip is saved; and the gain error is obtained by multiplexing the second-stage successive approximation type analog-to-digital conversion module, so that the gain error of the residual amplifier is reduced, and the conversion accuracy of the whole pipelined successiveapproximation type analog-to-digital converter is improved.

The invention discloses a sampling clock generation circuit and an analog-digital converter and belongs to the digital signal processing field. The sampling clock generation circuit comprises a variable-resistance circuit, a NOT gate type circuit and a capacitor, the input end of the NOT gate type circuit receives pulse signals of which the period is T, the output end of the NOT gate type circuit is connected with one end of the capacitor, the other end of the capacitor is connected with the ground, the power supply end of the NOT gate type circuit is connected with a power supply, the ground end of the NOT gate type circuit is connected with one end of the variable-resistance circuit, and the other end of the variable-resistance circuit is connected with the ground; the NOT gate type circuit is used for outputting low level when the pulse signal has high level and outputting high level when the pulse signal has low level; the variable-resistance circuit is used for regularly changing the resistance according to a time length T, the resistance change period is n*T, the resistance is different after each change in each period, and n is an integer larger than or equal to 2. The sampling clock generation circuit and the analog-digital converter enable the conversion accuracy of the ADC to be improved.

The invention relates to a method for suppressing third-order and fifth-order intermodulation distortion of a microwave photon down-conversion link, and the method comprises the following steps that:a laser emits a light beam, and the light beam is modulated by a local oscillation signal received by a third phase modulator and then is output, wherein the modulation of the third phase modulator iscontrolled by controlling the power of the local oscillation signal, so as to suppress the third-order and fifth-order intermodulation distortion; a signal modulated by the third phase modulator passes through a 3dB coupler, and the optical signal is divided into a first light beam and a second light beam, wherein the first light beam is modulated by a first phase modulator, then passes through afirst optical filter and is output to a first input end of the balance detector, so a first branch is formed; the second light beam is output to the second phase modulator after passing through the optical attenuator, is output to the second optical filter after being modulated by the second phase modulator, and is output to the second input end of the balance detector after passing through the second optical filter, so a second branch is formed.

The invention provides a high SFDR (spurious free dynamic range) folding interpolation analog-to-digital converter structure adopting cascade folding interpolator inter-stage switch 'pseudo random disorder sequence'. The folding interpolation analog-to-digital converter comprises a folding unit analog preprocessing module or an interpolation analog preprocessing module; the cascade folding interpolator inter-stage switch 'pseudo random disorder sequence' is a logic sequence for pseudo-randomly selecting a folding interpolation signal path for analog signals in a preprocessing process, and a folding interpolation circuit of each stage comprises two groups of switch logics, namely a positive disorder sequence switch logic and a corresponding negative disorder sequence removal switch logic. Moreover, the switch disorder sequence logics are divided into intra-stage disorder sequence logic and inter-stage disorder sequence combined logic. The intra-stage and inter-stage switch disorder sequence logics of the cascade folding interpolation circuit average the input equivalent imbalance between a folder and an interpolator in the processed adjacent quantification ranges to average the harmonic components introduced by mismatch into the noise floor so as to improve the spurious free dynamic range (SFDR) of the whole analog-to-digital converter.

The invention discloses a segmented current-steering digital-to-analog converter circuit and a calibration method. The current-steering digital-to-analog converter circuit comprises a current source array, a current source switch array, an encoding circuit, a serial-to-parallel conversion circuit, a latch circuit and a calibration circuit. The circuit is integrated into the circuit; on-chip calibration realized, meanwhile, the defect that a binary current source in the sectional type current steering digital-to-analog converter cannot be calibrated by a traditional calibration circuit is overcome; the current source of each bit in the segmented current steering digital-to-analog converter is calibrated in sequence, so that the matching degree between the current sources is improved, and the static linearity, the spurious-free dynamic range and other performances of the digital-to-analog converter are improved.

The invention discloses a four-channel single-bit digital receiver and a design method thereof. The method comprises the steps: carrying out the single-bit sampling of a signal, obtaining a single-bit digital signal, analyzing the harmonic characteristics of the single-bit digital signal in a Nyquist sampling frequency band, and obtaining four frequency bands which do not contain a target harmonic component; designing a four-channel single-bit digital receiver model according to the four frequency bands without the target harmonic component; and performing a simulation test according to the four-channel single-bit digital receiver model and preset test parameters to obtain a test result. Through the design of the special frequency band, higher harmonics can be effectively avoided, the spurious-free dynamic range of single-bit digital signals in each channel can be effectively improved, the instantaneous dynamic range of the receiver can be improved, the real-time processing capacity of the receiver can be enhanced, and the designed four-channel single-bit digital receiver has the advantages of simple structure and low cost. The device has the advantages of simple structure, strong anti-noise capability, high instantaneous dynamic range and the like.

The invention provides a method for enlarging an SFDR (spurious free dynamic range) of a signal after data truncation. A uniformly distributed random integer signal sequence in a certain amplitude range is generated through design, the bit width of the random integer signal sequence is identical with the truncated bit width, the random integer signal sequence is stacked on a signal before truncation, then bit width truncation is performed, and a random signal after truncation is obtained, so that the harmonic amplitude of the truncation error is decayed rapidly, harmonic distortion caused by direct truncation is eliminated, and the dynamic range of the random signal after truncation is enlarged.

Disclosed are a digital control oscillator and a magnetic resonance imaging system. The digital control oscillator comprises a phase accumulation unit, a quantitative shaping unit and a conversion unit. The phase accumulation unit is used for accumulating frequency control words to generate first phase signals; the quantitative shaping unit is used for quantizing the first phase signals to generate second phase signals, performing low-frequency attenuation and high-frequency amplification on quantizing noises generated from quantization and performing low-pass filtering on the quantizing noises subjected to low-frequency attenuation and high-frequency amplification; the conversion unit is used for outputting waveform data corresponding to the second phase signals. Since the quantizing noises are shaped by the digital control oscillator, the signal to noise ratio and the stray-free dynamic range of outputted periodic signals are increased.

The invention relates to a spurious-free dynamic range improvement method based on single sideband modulation. The spurious-free dynamic range improvement method comprises the following steps that: step 1, a laser device emits an optical carrier S1; step 2, a radio frequency input signal S2 modulates an optical signal S1 output by a laser through using a phase modulator so as to obtain and outputa phase modulation signal S3; step 3, the phase modulation signal S3 passes through a third-order intermodulation distortion suppressor, and then a single-sideband phase modulation signal S4 with a certain carrier-to-sideband ratio is output; and step 4, a photoelectric detector demodulates the signal S4 to suppress third-order intermodulation distortion in a output radio frequency signal S5, andan output signal of the photoelectric detector is input into a frequency spectrograph to be analyzed. The third-order intermodulation distortion suppressor obtains the single-sideband signal with a certain ratio of an optical carrier to +2-order sideband amplitude after carrying out amplitude-frequency processing on the signal, and the signal is extracted by the photoelectric detector in the step4, so that a spurious-free dynamic range of a spurious-free dynamic range link is improved.

The invention relates to an N-bit digital-to-analog conversion apparatus, which is used for receiving a digital signal and a clock signal. The clock signal is switched between a first state and a second state. Besides, the N-bit digital-to-analog conversion apparatus comprises a decoder, a random number generator and a conversion module. More specifically, the decoder is used for converting a digital signal into a multi-bit thermometer code. The random number generator is used for outputting a reset signal in a random number state; the rest signal has a plurality of bits that are arranged alternatively and randomly, wherein the arrangement mode is changed at different time; and in the reset signal, the number of the bits that are in a logic high level is equal to the number of the bits that are in a logic low level. When the clock signal is in the first state, the conversion module converts the thermometer code into an analog voltage relating to the digital signal; and when the clock signal is in the second state, the conversion module enables the analog voltage to be reduced to zero according to the reset signal. According to the invention, a spurious free dynamic range can be enlarged.