Sampling clock generation circuit and analog-digital converter

Abstract

The invention discloses a sampling clock generation circuit and an analog-digital converter and belongs to the digital signal processing field. The sampling clock generation circuit comprises a variable-resistance circuit, a NOT gate type circuit and a capacitor, the input end of the NOT gate type circuit receives pulse signals of which the period is T, the output end of the NOT gate type circuit is connected with one end of the capacitor, the other end of the capacitor is connected with the ground, the power supply end of the NOT gate type circuit is connected with a power supply, the ground end of the NOT gate type circuit is connected with one end of the variable-resistance circuit, and the other end of the variable-resistance circuit is connected with the ground; the NOT gate type circuit is used for outputting low level when the pulse signal has high level and outputting high level when the pulse signal has low level; the variable-resistance circuit is used for regularly changing the resistance according to a time length T, the resistance change period is n*T, the resistance is different after each change in each period, and n is an integer larger than or equal to 2. The sampling clock generation circuit and the analog-digital converter enable the conversion accuracy of the ADC to be improved.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a sampling clock generation circuit and an analog-to-digital converter. Background technique [0002] Due to the limitations of technology and device development, the sampling frequency of a single-chip Analog to Digital Converter (ADC) chip cannot be made very high. To achieve a higher sampling frequency, multiple ADC chips can be used in the Interleaved sampling is realized under the driving of sampling clocks with different phases. [0003] Among them, the sampling clocks of different phases are usually realized by the following scheme: the logic circuit divides the clock source signal into n channels, and obtains n channels whose frequency is equal to the frequency of the clock source signal / n and whose phases are different, n≥2 and n is an integer; Different numbers of inverters are connected in series in the transmission channels of n signals for delay, and n sampl...

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problem that the existing technology cannot effectively adjust the sampling point timing deviation and reduce the conversion accuracy of the ADC, the embodiment of the present invention provides a sampling clock generation circuit and an analog-to-digital converter

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