152results about "Power saving provisions" patented technology

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

The invention discloses a successive approximation type analog-to-digital converter and a conversion method. The analog-to-digital converter comprises a digital-to-analog converter, a comparator and a shift register, the digital-to-analog converter comprises a normal-phase capacitor array connected with the normal-phase end of the comparator and an inverted-phase capacitor array connected with the inverted-phase end of the comparator. The other end of each first capacitor in the high array is connected with one of a sampling signal, a reference voltage, a common-mode voltage and a reference ground through a switch; the other end of each second capacitor in the low array is connected with one of reference voltage, common-mode voltage and reference ground through the switch; capacitors in the high array and the low array are binary weighted capacitors from a low bit to a high bit; and the shift register is used for receiving a comparison result output by the comparator after the switch in the normal-phase capacitor array or the reverse-phase capacitor array is switched. The invention is beneficial to saving area, increasing input range and reducing power consumption, and can be widely applied to the technical field of electronics.

The invention discloses an analog signal pulse encoding device based on event driving and an analog signal processing method, and the device comprises a signal conditioning module which comprises at least one conditioning unit, and the conditioning unit is used for receiving an analog signal, carrying out the front-end analog conditioning of the signal, and outputting an analog conditioning signal; the threshold comparison module is connected with the signal conditioning module and is used for carrying out threshold detection on the analog conditioning signal according to a set threshold and then outputting a threshold comparison signal; the event triggering module is connected with the threshold comparison module and is used for triggering a pulse event signal corresponding to the analog conditioning signal according to the threshold comparison signal; and the pulse coding module is connected with the event triggering module and is used for converting the pulse event signal into a pulse coding signal by adopting a pulse coding mode. According to the invention, by introducing the threshold comparison module and the event trigger module at the front end of the device, invalid sampling can be effectively avoided, a large amount of redundant data can be reduced, and power consumption, communication and storage pressure and burden can be reduced.

The invention relates to the technical field of integrated circuits, and provides a digital-to-analog conversion circuit and a control chip. The circuit comprises a digital decoder, a nonlinear digital-to-analog converter and a linear digital-to-analog converter, the digital decoder is used for decoding the first M bits of the N-bit digital code and outputting a decoding result; the nonlinear digital-to-analog converter is connected with the linear digital-to-analog converter, and the nonlinear digital-to-analog converter is used for processing a voltage range formed by the received first input voltage and second input voltage according to a decoding result and outputting corresponding voltages respectively; the linear digital-to-analog converter receives the last N-M digital codes of the N digital codes, quantizes a voltage range formed by voltages received by the two input ends of the linear digital-to-analog converter according to the last N-M digital codes of the N digital codes, and outputs a reference voltage. According to the digital-to-analog conversion circuit provided by the embodiment of the invention, the consumption of parts and the layout area of the digital-to-analog conversion circuit can be reduced.

A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

This invention provides an analog-to-digital converter (ADC) comprising: a switched-capacitor array for operating in a first ADC mode or a second ADC mode based on a received timing signal; a first logic unit for outputting a first timing signal to control the switched-capacitor array to operate in the first ADC mode; a second logic unit for outputting a second timing signal to control the switched-capacitor array to operate in the second ADC mode; a control unit for outputting a control signal to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal; and a comparator, the output of which is electrically connected to the first and second logic units to feed back the output voltage of the switched-capacitor array to the control unit through the first and second logic units. This satisfies the requirements for high-precision and fast sampling of signals at different time periods, and reduces the area of ​​the ADC by reusing the switched-capacitor array and the comparator.

To reduce power consumption. A photodetection element includes a plurality of pixels, in which each of the plurality of pixels includes: a physical signal acquisition unit that acquires a physical signal; a comparison unit that compares a physical signal acquired by the physical signal acquisition unit with a reference signal; a signal accumulation floating unit that is electrically connected to one end of the comparison unit; a signal detection unit that is electrically connected to the signal accumulation floating unit and detects a comparison result of the comparison unit; a signal amplification unit that amplifies a detection result of the signal detection unit; a signal storage unit that stores a time code; a signal input / output unit that inputs and outputs a time code; and a signal control unit that performs control to store a time code output from the signal input / output unit in the signal storage unit on the basis of the comparison result, and outputs, to the signal input / output unit, a time code of the time when the comparison result is inverted, the time code being stored in the signal storage unit, and at least two or more of the pixels operate in parallel.

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.

The application discloses a successive approximation type analog-digital conversion device based on a composite dielectric grid and a working method, and belongs to the technical field of semiconductor devices, analog-digital conversion and storage-computation integration. The device is divided into coupling units with different areas according to binary values, and then the control of each weight coupling unit is realized through binary weights. The device does not need large MIM capacitors and complex metal switch trees, thereby reducing area consumption. The on-off characteristics of a semiconductor are utilized, and whether the readout transistor is turned on or not is taken as a comparison result to realize the step-by-step comparison between a two-part interval and an input quantity, thereby avoiding the comparison circuit logic of a circuit stage, so that the power consumption of a quantization unit is significantly reduced. In addition, the device provided by the application has a simple structure, can be extended in a row or column direction in parallel according to actual conditions, and mismatch can be eliminated through code table compensation. The device can be used as an on-chip ADC front end and can also be embedded in a pixel / storage-computation unit as a local quantizer, and has strong versatility.

A top-plate sampling circuitry (10) for sampling a voltage input signal (11), the circuitry comprising: a sampling transistor (110) and a sampling capacitor (120); the sampling transistor being operable as a switch by a gate node (14) according to a tracking phase and a holding phase; a bootstrapper sub-circuitry (140) configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage (155), and to, during the tracking phase, provide the bootstrapped voltage to the gate node; and a gate switch (190) between the gate node and a fixed reference voltage (160), wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time; wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling (180) between the bootstrapped voltage and the gate node.

The invention relates to a multi-stage amplifier, an analog-to-digital converter and electronic equipment, and the multi-stage amplifier comprises a first-stage amplifier which comprises a first step-down charge pump and is used for carrying out the first-stage amplification of a to-be-amplified signal and outputting a first amplified signal; the second-stage amplifier comprises a second step-down charge pump and a second amplifier and is used for carrying out second-stage amplification on the first amplification signal and outputting a second amplification signal; and the third-stage amplifier comprises a boost charge pump and a third amplifier and is used for carrying out third-stage amplification on the second amplification signal and outputting a third amplification signal. According to the multi-stage amplifier, low-power-consumption, high-gain and large-swing output can be achieved in the multi-stage amplifier, voltage rising and falling adjustment is achieved among different amplification stages through a multi-stage dynamic power supply framework, and therefore balance among gain, speed and power consumption is achieved.

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

The present disclosure relates to systems and methods for signed conversion. Described herein relate to systems and methods for a converter including a first input, a second input, and a plurality of digital-to-analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a zeroing operation. The DAC cell is configured to provide a data magnitude in a polarity on at least one of the first leg or the second leg during at least a portion of a clock cycle. The data magnitude and the polarity are provided according to a first signal at the first input and a second signal at the second input.

A voltage-to-time converter (VTC) circuit includes an input capacitor being charged according to an input voltage during a precharge operation; an output capacitor being charged during the precharge operation; a first transistor configured to discharge the output capacitor according to a voltage charged in the input capacitor during a first operation following the precharge operation; and a second transistor configured to charge the output capacitor according to the voltage charged in the input capacitor during a second operation following the first operation.

According to an example embodiment, a client device is configured to: obtain a signal sequence configuration defining a plurality of signal sequences, wherein each signal sequence in the plurality of signal sequences corresponds to an uplink transmission power level in a plurality of uplink transmission power levels; transmit the plurality of signal sequences according to the signal sequence configuration to a network node device; receive, from the network node device, an indication about an uplink transmission power level out of the plurality of uplink transmission power levels to be used for uplink transmission; and perform an uplink transmission using the indicated uplink transmission power level to the network node device.

The invention relates to the technical field of integrated circuits, and discloses a successive approximation type analog-to-digital converter with a data prediction function. The converter comprises a differential capacitor array, a comparator, a control logic module, a prediction control unit and a capacitor switch module. The differential capacitor array is responsible for charge redistribution in the sampling and quantification process; the comparator is used for comparing the array output voltage; the control logic module generates bit-by-bit comparison clock signals; the prediction control unit receives an external prediction signal; the capacitor switch module comprises a plurality of either-or data selectors, first input ends of the either-or data selectors are connected with output of the comparator, second input ends of the either-or data selectors are connected with prediction signals, output ends of the either-or data selectors are connected with the capacitor lower polar plate, and enable ends receive mode selection signals. In a prediction mode, the converter directly uses an external prediction signal to set a high-order capacitance state, and an earlier successive comparison process is skipped, so that the quantization power consumption is remarkably reduced, and the conversion speed is improved.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit / cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit / cycle conversion.

To provide an analog-to-digital converter capable of reducing power consumption by utilizing auto-zero period optimization, and to provide an operation method thereof, and an image sensor including the analog-to-digital converter.SOLUTION: A circuit includes: a first amplifier that adjusts and equalizes voltage levels of an input node and an output node in response to a first auto-zero signal in a first auto-zero period, compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, and generates a second output signal on the basis of the first output signal in the first operation period and the second operation period. An operation of the second amplifier is stopped from a time point at which the second auto-zero period ends to a time point at which the first operation period starts.SELECTED DRAWING: Figure 4

There is provided a method for an apparatus for converting a digital signal into an analog signal, comprising: a weight adjustment unit, configured to adjust a weight of a digital signal having an arbitrary bit order; a conversion unit, configured to output a variable resistance value based on a result of adjusting the weight; and an output unit, configured to output a current signal having a magnitude corresponding to the result based on the resistance value.

The invention discloses a logic control circuit of a successive approximation type analog-to-digital conversion chip. The logic control circuit comprises a shift register, a data register and a logic gate array, the shift register is used for generating a shift signal, and the shift signal is used for controlling the logic gate array to output a switching signal corresponding to each bit in the digital-to-analog converter, and is also used for controlling the data register to store a comparison result output by the comparator; the logic gate array is used for gradually controlling each bit switch of the digital-to-analog converter to be turned on according to a shift signal output by a D trigger in the shift register so as to output a corresponding reference signal; and the data register is used for responding to the shift signals output by the D triggers in the shift register and gradually storing the comparison results output by the comparator into the D triggers at the corresponding positions. The problem that a traditional SAR logic control module is large in resource consumption can be solved.

An analog-to-digital converter includes a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal; a double binary counter having a first input coupled to a first output of the VCO, a second input coupled to a second output of the VCO; a first set of registers coupled to the first output of the double binary counter; a second set of registers coupled to the second output of the double binary counter; sense amplifiers coupled to the outputs of the VCO; and a correction component coupled to the first set of registers, the second set of registers, and the sense amplifiers, wherein the correction component generates a coarse count, a fine count, and combines the coarse count and the fine count to provide a digital output signal representative of the analog input signal.

The invention relates to the technical field of power electronics, in particular to an analog-to-digital conversion ADC circuit. The circuit comprises N assembly line modules which are in cascade connection, and N is a positive integer; wherein the effective precision of the first assembly line module is two bits, and the first assembly line module is set to be 2.5 bit quantization. By adopting the scheme, factors such as power consumption, precision, design difficulty and the like of the pipelined ADC can be considered when the first-stage pipelined module is designed.

A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

The application relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-digital converter and a quantization method thereof.The resistance-capacitance hybrid analog-digital converter comprises a CDAC capacitor array connected to the positive input end and the negative input end of a comparator, and the output end of the comparator is connected to a SAR control logic circuit; a reference voltage sampling capacitor unit is selected to be connected between the output end of an RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or to be connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and the reference voltage sampling capacitor unit samples the output voltage of the RDAC; in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and the switching of the RDAC and the CDAC is controlled through the SAR control logic circuit according to the comparison result, so that the successive approximation analog-digital conversion process is completed.

A method for performing an analog-to-digital conversion using an analog-to-digital converter (ADC) with a successive approximation register (SAR), the method comprising: performing bit tests using a digital-to-analog converter (DAC) circuit of the SAR-ADC to convert a first sample of an analog input signal into an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and Controlling a value of M using at least one result of a previous bit attempt.

The application relates to the technical field of integrated circuits, and discloses a successive approximation analog-to-digital converter with a data prediction function. The converter comprises a differential capacitor array, a comparator, a control logic module, a prediction control unit and a capacitor switch module. The differential capacitor array is responsible for charge redistribution in the sampling and quantization process; the comparator is used for comparing array output voltages; the control logic module generates a bit-by-bit comparison clock signal; the prediction control unit receives an external prediction signal; the capacitor switch module comprises a plurality of two-way data selectors, the first input end of the two-way data selectors is connected with the comparator output, the second input end is connected with the prediction signal, the output end is connected with a capacitor lower plate, and the enable end receives a mode selection signal. In the prediction mode, the converter directly uses the external prediction signal to set the high-bit capacitor state, skips the previous successive comparison process, thereby significantly reducing the quantization power consumption and improving the conversion speed.