225results about "Power saving provisions" patented technology

The invention provides an analog front-end circuit, electronic equipment, a successive approximation type analog-to-digital converter and a method, and the analog front-end circuit comprises a digital-to-analog conversion capacitor array which comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, in the conversion process, the capacitor lower polar plate is switched between the reference voltage and the reference ground to realize charge redistribution; the second digital-to-analog conversion unit samples the reference voltage, and the capacitor lower polar plate is switched between the reference voltage and the reference ground in the conversion process to realize charge redistribution; the comparison module is used for comparing output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit; the clock generation module generates a clock signal based on the comparison result; the successive approximation logic module outputs a digital signal based on a clock signal and generates a switching control signal. According to the invention, the requirement on the power supply voltage is reduced, the power consumption and the area are reduced, and the chip cost is saved.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

The invention discloses a successive approximation type analog-to-digital converter and a conversion method. The analog-to-digital converter comprises a digital-to-analog converter, a comparator and a shift register, the digital-to-analog converter comprises a normal-phase capacitor array connected with the normal-phase end of the comparator and an inverted-phase capacitor array connected with the inverted-phase end of the comparator. The other end of each first capacitor in the high array is connected with one of a sampling signal, a reference voltage, a common-mode voltage and a reference ground through a switch; the other end of each second capacitor in the low array is connected with one of reference voltage, common-mode voltage and reference ground through the switch; capacitors in the high array and the low array are binary weighted capacitors from a low bit to a high bit; and the shift register is used for receiving a comparison result output by the comparator after the switch in the normal-phase capacitor array or the reverse-phase capacitor array is switched. The invention is beneficial to saving area, increasing input range and reducing power consumption, and can be widely applied to the technical field of electronics.

The present application discloses an analog-to-digital conversion circuit, a chip, and a recording device. The analog-to-digital conversion circuit comprises a main path module, a dynamic range enhancement module, and a dynamic digital-to-analog conversion module. The main path module is used for converting an analog signal and an analog feedback signal into a digital signal to be processed for outputting to the dynamic range enhancement module, and obtaining a digital signal on the basis of the digital signal to be processed and a digital gain signal and outputting the digital signal. The dynamic range enhancement module is used for performing dynamic quantization processing on the digital signal to be processed to obtain a control signal, and generating the digital gain signal. The dynamic digital-to-analog conversion module is used for, on the basis of the control signal, dynamically controlling the activation and deactivation of each DAC element in a digital-to-analog conversion array, and generating an analog feedback signal. According to the analog-to-digital conversion circuit of the present application, the need for a front-end fixed-gain OPA is eliminated, reducing power consumption and reducing costs; moreover, dynamically controlling the activation and deactivation of each DAC element in the digital-to-analog conversion array further reduces the power consumption.

The invention discloses an analog signal pulse encoding device based on event driving and an analog signal processing method, and the device comprises a signal conditioning module which comprises at least one conditioning unit, and the conditioning unit is used for receiving an analog signal, carrying out the front-end analog conditioning of the signal, and outputting an analog conditioning signal; the threshold comparison module is connected with the signal conditioning module and is used for carrying out threshold detection on the analog conditioning signal according to a set threshold and then outputting a threshold comparison signal; the event triggering module is connected with the threshold comparison module and is used for triggering a pulse event signal corresponding to the analog conditioning signal according to the threshold comparison signal; and the pulse coding module is connected with the event triggering module and is used for converting the pulse event signal into a pulse coding signal by adopting a pulse coding mode. According to the invention, by introducing the threshold comparison module and the event trigger module at the front end of the device, invalid sampling can be effectively avoided, a large amount of redundant data can be reduced, and power consumption, communication and storage pressure and burden can be reduced.

The present disclosure relates to the technical field of integrated circuits, and in particular to an analog signal processing circuit and method for a high-precision ADC, a chip and a device. The circuit comprises: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module and a first switch; the auxiliary ADC module is configured to convert a conditioned analog signal to be converted and output a converted first digital code by means of a digital output end; and the main ADC module is configured to establish the input voltage of the main ADC module to a target precision on the basis of said conditioned analog signal and the first digital code so as to sample the analog signal. According to the circuit, when the input voltage of the main ADC module changes greatly, the power consumption and the area overhead of the analog signal processing circuit are saved due to the power consumption and the area overhead of an auxiliary ADC and an auxiliary amplifier being very small while the main amplifier module is protected against rapid charging interference.

The invention relates to the technical field of integrated circuits, and provides a digital-to-analog conversion circuit and a control chip. The circuit comprises a digital decoder, a nonlinear digital-to-analog converter and a linear digital-to-analog converter, the digital decoder is used for decoding the first M bits of the N-bit digital code and outputting a decoding result; the nonlinear digital-to-analog converter is connected with the linear digital-to-analog converter, and the nonlinear digital-to-analog converter is used for processing a voltage range formed by the received first input voltage and second input voltage according to a decoding result and outputting corresponding voltages respectively; the linear digital-to-analog converter receives the last N-M digital codes of the N digital codes, quantizes a voltage range formed by voltages received by the two input ends of the linear digital-to-analog converter according to the last N-M digital codes of the N digital codes, and outputs a reference voltage. According to the digital-to-analog conversion circuit provided by the embodiment of the invention, the consumption of parts and the layout area of the digital-to-analog conversion circuit can be reduced.

The invention discloses a low-power-consumption reading circuit based on pixel signal prediction and a CMOS image sensor, the low-power-consumption reading circuit comprises a ramp generator, a comparator, a logic circuit and a counter, the positive phase input end of the comparator receives a ramp signal of the ramp generator, the negative phase input end of the comparator receives a pixel signal, and the logic circuit is connected with the counter. The comparator predicts and compares the input pixel signal according to the ramp signal, and outputs a prediction signal and a comparison signal; the logic circuit separates the prediction signal output by the comparator from the comparison signal, feeds the prediction signal back to the comparator, and outputs a generated prediction window to the counter; the counter quantizes the pixel signal based on the prediction window generated by the logic circuit and outputs the quantized pixel signal. According to the invention, the pixel signals are predicted and compared through only one comparator, and the prediction window is generated, so that the low n-bit counter only needs to work in the prediction window, the turnover frequency of the counter is greatly reduced, and the dynamic power consumption of the reading circuit is reduced.

A partial common mode level-based switching method for SAR-ADC relates to the technical field of integrated circuits, in a sampling stage, an input signal is sampled to a top plate of a capacitor array, and bottom plates of a highest weight bit capacitor and a second highest weight bit capacitor are connected to a common mode level Vcm; in the conversion phase, the MSB decision is directly made by comparing the differences between the differential inputs. Since the operation of the highest weight bit capacitor and the operation of the second highest weight bit capacitor are differential, the common mode remains unchanged. For the cycle of the remaining bits, the bits in the corresponding capacitor array will be discharged to Gnd. For an n-bit ADC, this operation is repeated n-3 times until the last bit is determined. Compared with a back-switching method, the common mode change can be improved while good energy efficiency of the switch and the logic controller is maintained.

A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

The invention relates to an MDAC circuit of a pipelined analog-to-digital converter. The technical problems that in the prior art, an assembly line ADC is large in stage number and large in delay are solved, and jitter signal injection is facilitated. According to the technical scheme, the circuit comprises a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array and an operational amplifier. According to the further technical scheme, the circuit further comprises a first bridge capacitor, a first correction capacitor array, a second bridge capacitor and a second correction capacitor array. According to the technical scheme, the operational amplifiers of the adjacent sub-conversion stages are shared, so that one operational amplifier is saved, and the overall power consumption of the ADC is effectively reduced. The single conversion stage can adopt high-resolution conversion processing, the serial stage number of the whole assembly line analog-to-digital converter is reduced, and the assembly line delay is reduced. The capacitors of two adjacent sub-conversion stages are shared, so that the number of the capacitors is reduced, and the layout area of an integrated circuit is reduced.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

A first analog signal may be sampled during a first time period in accordance with a first sampling range and a sampling resolution step size, where a first digital sequence may be outputted during the first time period based on sampling the first analog signal. Based on a metric of interference, the first sampling range may be adapted to a second sampling range while the sampling resolution step size may be maintained at a same level or a level that is below a sampling resolution step size threshold. During a second time period, a second analog signal may be sampled in accordance with the second sampling range, where a second digital sequence may be output based sampling the second analog signal.

This invention provides an analog-to-digital converter (ADC) comprising: a switched-capacitor array for operating in a first ADC mode or a second ADC mode based on a received timing signal; a first logic unit for outputting a first timing signal to control the switched-capacitor array to operate in the first ADC mode; a second logic unit for outputting a second timing signal to control the switched-capacitor array to operate in the second ADC mode; a control unit for outputting a control signal to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal; and a comparator, the output of which is electrically connected to the first and second logic units to feed back the output voltage of the switched-capacitor array to the control unit through the first and second logic units. This satisfies the requirements for high-precision and fast sampling of signals at different time periods, and reduces the area of ​​the ADC by reusing the switched-capacitor array and the comparator.

The invention discloses a comparator relative gain-based successive approximation analog-to-digital converter, which relates to the field of integrated circuit design, and comprises a high-order DAC (Digital-to-Analog Converter), a low-order DAC, a four-input comparator and SAR (Synthetic Aperture Radar) logic. Through the relative gain of a four-input comparator, a traditional large-overhead DAC is divided into two small-overhead DACs, namely a high-bit DAC and a low-bit DAC, the high-bit DAC is used for providing reference voltage needed for quantizing M-bit high-bit digital codes, the low-bit DAC is used for providing reference voltage needed for quantizing N-M-bit low-bit digital codes, and therefore N-bit digital codes are achieved. The total number of unit capacitors is reduced to 2M + 1 + 2N-M, the size of the DAC is greatly reduced, and compared with a traditional SAR ADC, the SAR ADC has lower power consumption and area.

A digital-to-analog converter (DAC) circuit, an electronic device including the digital-to-analog converter circuit, and a control method of the digital-to-analog converter circuit are provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switching circuit connected to the first multiplexer; a second switching circuit connected to the second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switching circuit and the second switching circuit, respectively.

To reduce power consumption. A photodetection element includes a plurality of pixels, in which each of the plurality of pixels includes: a physical signal acquisition unit that acquires a physical signal; a comparison unit that compares a physical signal acquired by the physical signal acquisition unit with a reference signal; a signal accumulation floating unit that is electrically connected to one end of the comparison unit; a signal detection unit that is electrically connected to the signal accumulation floating unit and detects a comparison result of the comparison unit; a signal amplification unit that amplifies a detection result of the signal detection unit; a signal storage unit that stores a time code; a signal input / output unit that inputs and outputs a time code; and a signal control unit that performs control to store a time code output from the signal input / output unit in the signal storage unit on the basis of the comparison result, and outputs, to the signal input / output unit, a time code of the time when the comparison result is inverted, the time code being stored in the signal storage unit, and at least two or more of the pixels operate in parallel.

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.

An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.

The invention discloses a low-power-consumption high-precision current frequency conversion circuit and an implementation method, and particularly relates to the technical field of analog-to-digital conversion, and the low-power-consumption high-precision current frequency conversion circuit comprises an automatic gain control transimpedance amplification circuit, an integrator charge balance conversion circuit and an arm single-chip microcomputer compensation circuit. The automatic gain control transimpedance amplification circuit is connected with input current, the automatic gain control transimpedance amplification circuit is respectively connected with the integrator charge balance conversion circuit and the arm single chip microcomputer compensation circuit, the arm single chip microcomputer compensation circuit is connected with the constant current source and the FPGA logic control circuit, the constant current source is connected with the integrator charge balance conversion circuit, and the FPGA logic control circuit is connected with the FPGA logic control circuit. And the integrator charge balance conversion circuit is connected with the FPGA logic control circuit. The automatic gain control transimpedance amplification circuit is utilized to enable the actual current input into the integrator charge balance conversion circuit and the original input current to be subjected to gain adjustment control, the current actually input into the integrator circuit is reduced during large current conversion, the output current requirement for a constant current source is reduced, and the power consumption requirement of the circuit is reduced.

The application discloses a successive approximation type analog-digital conversion device based on a composite dielectric grid and a working method, and belongs to the technical field of semiconductor devices, analog-digital conversion and storage-computation integration. The device is divided into coupling units with different areas according to binary values, and then the control of each weight coupling unit is realized through binary weights. The device does not need large MIM capacitors and complex metal switch trees, thereby reducing area consumption. The on-off characteristics of a semiconductor are utilized, and whether the readout transistor is turned on or not is taken as a comparison result to realize the step-by-step comparison between a two-part interval and an input quantity, thereby avoiding the comparison circuit logic of a circuit stage, so that the power consumption of a quantization unit is significantly reduced. In addition, the device provided by the application has a simple structure, can be extended in a row or column direction in parallel according to actual conditions, and mismatch can be eliminated through code table compensation. The device can be used as an on-chip ADC front end and can also be embedded in a pixel / storage-computation unit as a local quantizer, and has strong versatility.

A top-plate sampling circuitry (10) for sampling a voltage input signal (11), the circuitry comprising: a sampling transistor (110) and a sampling capacitor (120); the sampling transistor being operable as a switch by a gate node (14) according to a tracking phase and a holding phase; a bootstrapper sub-circuitry (140) configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage (155), and to, during the tracking phase, provide the bootstrapped voltage to the gate node; and a gate switch (190) between the gate node and a fixed reference voltage (160), wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time; wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling (180) between the bootstrapped voltage and the gate node.

The invention relates to a multi-stage amplifier, an analog-to-digital converter and electronic equipment, and the multi-stage amplifier comprises a first-stage amplifier which comprises a first step-down charge pump and is used for carrying out the first-stage amplification of a to-be-amplified signal and outputting a first amplified signal; the second-stage amplifier comprises a second step-down charge pump and a second amplifier and is used for carrying out second-stage amplification on the first amplification signal and outputting a second amplification signal; and the third-stage amplifier comprises a boost charge pump and a third amplifier and is used for carrying out third-stage amplification on the second amplification signal and outputting a third amplification signal. According to the multi-stage amplifier, low-power-consumption, high-gain and large-swing output can be achieved in the multi-stage amplifier, voltage rising and falling adjustment is achieved among different amplification stages through a multi-stage dynamic power supply framework, and therefore balance among gain, speed and power consumption is achieved.

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

The present disclosure relates to systems and methods for signed conversion. Described herein relate to systems and methods for a converter including a first input, a second input, and a plurality of digital-to-analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a zeroing operation. The DAC cell is configured to provide a data magnitude in a polarity on at least one of the first leg or the second leg during at least a portion of a clock cycle. The data magnitude and the polarity are provided according to a first signal at the first input and a second signal at the second input.

The invention relates to the field of integrated circuit design, in particular to an incremental ADC (Analog to Digital Converter) for weak current detection, which comprises a resettable Sigma-Delta modulator, a resettable accumulator and a control clock, wherein the resettable Sigma-Delta modulator comprises an extremely low frequency low distortion filter, a quantizer and a current feedback DAC (Digital-to-Analog Converter); the extremely-low-frequency low-distortion filter is composed of a first-stage low-pass filter, a second-stage integrator, a first reset switch and a second reset switch. The resettable accumulator has a reset function and is used for accumulating output results of the quantizer; the control clock comprises a reset signal rst and a clock signal CLK; according to the invention, an extremely-low-frequency low-distortion filter structure is used in the resettable Sigma-Delta modulator, so that the problem of performance bottleneck caused by introduction of a pseudo resistor in sub-picoampere-level weak current detection of a traditional second-order incremental ADC is solved, and the dynamic range, the anti-noise capability and the linearity of a system are improved.

A voltage-to-time converter (VTC) circuit includes an input capacitor being charged according to an input voltage during a precharge operation; an output capacitor being charged during the precharge operation; a first transistor configured to discharge the output capacitor according to a voltage charged in the input capacitor during a first operation following the precharge operation; and a second transistor configured to charge the output capacitor according to the voltage charged in the input capacitor during a second operation following the first operation.

According to an example embodiment, a client device is configured to: obtain a signal sequence configuration defining a plurality of signal sequences, wherein each signal sequence in the plurality of signal sequences corresponds to an uplink transmission power level in a plurality of uplink transmission power levels; transmit the plurality of signal sequences according to the signal sequence configuration to a network node device; receive, from the network node device, an indication about an uplink transmission power level out of the plurality of uplink transmission power levels to be used for uplink transmission; and perform an uplink transmission using the indicated uplink transmission power level to the network node device.