299results about "Power saving provisions" patented technology

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

The invention provides an analog front-end circuit, electronic equipment, a successive approximation type analog-to-digital converter and a method, and the analog front-end circuit comprises a digital-to-analog conversion capacitor array which comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, in the conversion process, the capacitor lower polar plate is switched between the reference voltage and the reference ground to realize charge redistribution; the second digital-to-analog conversion unit samples the reference voltage, and the capacitor lower polar plate is switched between the reference voltage and the reference ground in the conversion process to realize charge redistribution; the comparison module is used for comparing output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit; the clock generation module generates a clock signal based on the comparison result; the successive approximation logic module outputs a digital signal based on a clock signal and generates a switching control signal. According to the invention, the requirement on the power supply voltage is reduced, the power consumption and the area are reduced, and the chip cost is saved.

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

A single-end input configurable Successive Approximation Register Analog-to-Digital Converter (SARADC) allows for the input configuration as single-ended or differential inputs without adding extra circuitry. In both configurations, the ADC maintains the same LSB voltage and output code range. Furthermore, when configured as a single-ended input, power consumption is further reduced.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-to-digital converter and a quantization method thereof. According to the resistance-capacitance hybrid analog-to-digital converter, a CDAC capacitor array is connected with the positive input end and the negative input end of a comparator, and the output end of the comparator is connected with an SAR control logic circuit; the reference voltage sampling capacitor unit is selectively connected between the output end of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or is connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and meanwhile, the reference voltage sampling capacitor unit samples the output voltage of the RDAC; and in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and controls the switching of the RDAC and the CDAC through the SAR control logic circuit according to the comparison result, thereby completing the successive approximation analog-to-digital conversion process.

The invention discloses a successive approximation type analog-to-digital converter and a conversion method. The analog-to-digital converter comprises a digital-to-analog converter, a comparator and a shift register, the digital-to-analog converter comprises a normal-phase capacitor array connected with the normal-phase end of the comparator and an inverted-phase capacitor array connected with the inverted-phase end of the comparator. The other end of each first capacitor in the high array is connected with one of a sampling signal, a reference voltage, a common-mode voltage and a reference ground through a switch; the other end of each second capacitor in the low array is connected with one of reference voltage, common-mode voltage and reference ground through the switch; capacitors in the high array and the low array are binary weighted capacitors from a low bit to a high bit; and the shift register is used for receiving a comparison result output by the comparator after the switch in the normal-phase capacitor array or the reverse-phase capacitor array is switched. The invention is beneficial to saving area, increasing input range and reducing power consumption, and can be widely applied to the technical field of electronics.

The present application discloses an analog-to-digital conversion circuit, a chip, and a recording device. The analog-to-digital conversion circuit comprises a main path module, a dynamic range enhancement module, and a dynamic digital-to-analog conversion module. The main path module is used for converting an analog signal and an analog feedback signal into a digital signal to be processed for outputting to the dynamic range enhancement module, and obtaining a digital signal on the basis of the digital signal to be processed and a digital gain signal and outputting the digital signal. The dynamic range enhancement module is used for performing dynamic quantization processing on the digital signal to be processed to obtain a control signal, and generating the digital gain signal. The dynamic digital-to-analog conversion module is used for, on the basis of the control signal, dynamically controlling the activation and deactivation of each DAC element in a digital-to-analog conversion array, and generating an analog feedback signal. According to the analog-to-digital conversion circuit of the present application, the need for a front-end fixed-gain OPA is eliminated, reducing power consumption and reducing costs; moreover, dynamically controlling the activation and deactivation of each DAC element in the digital-to-analog conversion array further reduces the power consumption.

The invention discloses an analog signal pulse encoding device based on event driving and an analog signal processing method, and the device comprises a signal conditioning module which comprises at least one conditioning unit, and the conditioning unit is used for receiving an analog signal, carrying out the front-end analog conditioning of the signal, and outputting an analog conditioning signal; the threshold comparison module is connected with the signal conditioning module and is used for carrying out threshold detection on the analog conditioning signal according to a set threshold and then outputting a threshold comparison signal; the event triggering module is connected with the threshold comparison module and is used for triggering a pulse event signal corresponding to the analog conditioning signal according to the threshold comparison signal; and the pulse coding module is connected with the event triggering module and is used for converting the pulse event signal into a pulse coding signal by adopting a pulse coding mode. According to the invention, by introducing the threshold comparison module and the event trigger module at the front end of the device, invalid sampling can be effectively avoided, a large amount of redundant data can be reduced, and power consumption, communication and storage pressure and burden can be reduced.

The present disclosure relates to the technical field of integrated circuits, and in particular to an analog signal processing circuit and method for a high-precision ADC, a chip and a device. The circuit comprises: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module and a first switch; the auxiliary ADC module is configured to convert a conditioned analog signal to be converted and output a converted first digital code by means of a digital output end; and the main ADC module is configured to establish the input voltage of the main ADC module to a target precision on the basis of said conditioned analog signal and the first digital code so as to sample the analog signal. According to the circuit, when the input voltage of the main ADC module changes greatly, the power consumption and the area overhead of the analog signal processing circuit are saved due to the power consumption and the area overhead of an auxiliary ADC and an auxiliary amplifier being very small while the main amplifier module is protected against rapid charging interference.

The invention relates to the technical field of integrated circuits, and provides a digital-to-analog conversion circuit and a control chip. The circuit comprises a digital decoder, a nonlinear digital-to-analog converter and a linear digital-to-analog converter, the digital decoder is used for decoding the first M bits of the N-bit digital code and outputting a decoding result; the nonlinear digital-to-analog converter is connected with the linear digital-to-analog converter, and the nonlinear digital-to-analog converter is used for processing a voltage range formed by the received first input voltage and second input voltage according to a decoding result and outputting corresponding voltages respectively; the linear digital-to-analog converter receives the last N-M digital codes of the N digital codes, quantizes a voltage range formed by voltages received by the two input ends of the linear digital-to-analog converter according to the last N-M digital codes of the N digital codes, and outputs a reference voltage. According to the digital-to-analog conversion circuit provided by the embodiment of the invention, the consumption of parts and the layout area of the digital-to-analog conversion circuit can be reduced.

The partition dormancy type resolution-adjustable capacitor array analog-to-digital converter comprises a normal-phase conversion capacitor array which comprises a normal-phase high-capacitor array and a normal-phase low-capacitor array; the anti-phase conversion capacitor array comprises an anti-phase high capacitor array and an anti-phase low capacitor array; the sampling module is used for carrying out initial sampling on the input signals from the top plates of all the capacitor units; the comparator is used for comparing an input signal or the states of the normal-phase conversion capacitor array and the reverse-phase conversion capacitor array and outputting bit data; the shift register is used for storing bit data; and the state switching module is used for being matched with the bridge switch to control circuit connection states of all the capacitor units, and the circuit connection states comprise a connection state and a voltage state. According to the invention, the energy consumption required by the capacitor unit is reduced through a partition dormancy mode, and the number of unit capacitors is reduced, so that the overall power consumption of the analog-to-digital converter is reduced.

The invention discloses a low-power-consumption reading circuit based on pixel signal prediction and a CMOS image sensor, the low-power-consumption reading circuit comprises a ramp generator, a comparator, a logic circuit and a counter, the positive phase input end of the comparator receives a ramp signal of the ramp generator, the negative phase input end of the comparator receives a pixel signal, and the logic circuit is connected with the counter. The comparator predicts and compares the input pixel signal according to the ramp signal, and outputs a prediction signal and a comparison signal; the logic circuit separates the prediction signal output by the comparator from the comparison signal, feeds the prediction signal back to the comparator, and outputs a generated prediction window to the counter; the counter quantizes the pixel signal based on the prediction window generated by the logic circuit and outputs the quantized pixel signal. According to the invention, the pixel signals are predicted and compared through only one comparator, and the prediction window is generated, so that the low n-bit counter only needs to work in the prediction window, the turnover frequency of the counter is greatly reduced, and the dynamic power consumption of the reading circuit is reduced.

A partial common mode level-based switching method for SAR-ADC relates to the technical field of integrated circuits, in a sampling stage, an input signal is sampled to a top plate of a capacitor array, and bottom plates of a highest weight bit capacitor and a second highest weight bit capacitor are connected to a common mode level Vcm; in the conversion phase, the MSB decision is directly made by comparing the differences between the differential inputs. Since the operation of the highest weight bit capacitor and the operation of the second highest weight bit capacitor are differential, the common mode remains unchanged. For the cycle of the remaining bits, the bits in the corresponding capacitor array will be discharged to Gnd. For an n-bit ADC, this operation is repeated n-3 times until the last bit is determined. Compared with a back-switching method, the common mode change can be improved while good energy efficiency of the switch and the logic controller is maintained.

A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

The embodiment of the invention provides a state switching method and device and electronic equipment, and the method comprises the steps: generating and maintaining a state switching signal under the condition that a preset state switching condition is satisfied; performing state switching on the target object by adopting the state switching signal; counting the time interval between the current moment and the ending moment of the synchronous alignment signal; the synchronous alignment signal is a signal which is applied to the target object and is earlier than the state switching signal; under the condition that the time interval meets the preset condition, the state switching signal is ended, and state switching of the target object is completed; the preset condition comprises that the time interval is even times of the first clock period. According to the scheme of the embodiment, the output signal after state switching of the target object is synchronized with the synchronous alignment signal, the problem of time sequence chaos is solved, and the circuit performance is improved.

The present invention relates to the technical field of analog circuits. Disclosed are a low-voltage floating inverter amplifier and a switched-capacitor analog-to-digital converter. The low-voltage floating inverter amplifier comprises a first self-biased inverter, a second self-biased inverter, and an energy storage capacitor connected in parallel. Both the first self-biased inverter and the second self-biased inverter are clock-controlled inverters that self-generate bias voltages. One end of the parallel connection is connected to a power supply voltage by means of a reset switch, and the other end of the parallel connection is connected to a ground voltage by means of a reset switch. Each of an input end of the first self-biased inverter and an input end of the second self-biased inverter is connected to an input signal, and is connected to a ground voltage by means of a reset switch. Each of an output end of the first self-biased inverter and an output end of the second self-biased inverter is provided with an amplification switch. The reset switches and the amplification switches are closed in an alternating manner by means of clock control. The low-voltage floating inverter amplifier is compatible with power supplies below 1 V under low-cost conditions, reducing power consumption and enhancing energy efficiency.

The invention discloses a high-speed low-power-consumption comparator of an SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits. The comparator comprises a pre-amplification stage and a latch stage, an enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, a positive input end of the pre-amplification stage is connected with a differential input positive end signal vp, a negative input end of the pre-amplification stage is connected with a differential input negative end signal vn, a positive output end vop is connected with a positive input end of the latch stage through a switch K1, and a negative output end von is connected with a positive input end of the latch stage through a switch K2. The switch K1 and the switch K2 are both controlled by an enable signal Ki; a differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, a differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switch K3 and the switch K4 are both controlled by an inversion signal Kim of an enable signal Ki. According to the scheme, the gain and the bandwidth of the pre-amplification stage are improved, so that the speed and the precision of the pre-amplification stage are improved at the same time.

The invention relates to an MDAC circuit of a pipelined analog-to-digital converter. The technical problems that in the prior art, an assembly line ADC is large in stage number and large in delay are solved, and jitter signal injection is facilitated. According to the technical scheme, the circuit comprises a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array and an operational amplifier. According to the further technical scheme, the circuit further comprises a first bridge capacitor, a first correction capacitor array, a second bridge capacitor and a second correction capacitor array. According to the technical scheme, the operational amplifiers of the adjacent sub-conversion stages are shared, so that one operational amplifier is saved, and the overall power consumption of the ADC is effectively reduced. The single conversion stage can adopt high-resolution conversion processing, the serial stage number of the whole assembly line analog-to-digital converter is reduced, and the assembly line delay is reduced. The capacitors of two adjacent sub-conversion stages are shared, so that the number of the capacitors is reduced, and the layout area of an integrated circuit is reduced.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and / or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

A unit capacitor for a switched-capacitor digital-to-analog converter is provided. An apparatus includes a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

A first analog signal may be sampled during a first time period in accordance with a first sampling range and a sampling resolution step size, where a first digital sequence may be outputted during the first time period based on sampling the first analog signal. Based on a metric of interference, the first sampling range may be adapted to a second sampling range while the sampling resolution step size may be maintained at a same level or a level that is below a sampling resolution step size threshold. During a second time period, a second analog signal may be sampled in accordance with the second sampling range, where a second digital sequence may be output based sampling the second analog signal.

This invention provides an analog-to-digital converter (ADC) comprising: a switched-capacitor array for operating in a first ADC mode or a second ADC mode based on a received timing signal; a first logic unit for outputting a first timing signal to control the switched-capacitor array to operate in the first ADC mode; a second logic unit for outputting a second timing signal to control the switched-capacitor array to operate in the second ADC mode; a control unit for outputting a control signal to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal; and a comparator, the output of which is electrically connected to the first and second logic units to feed back the output voltage of the switched-capacitor array to the control unit through the first and second logic units. This satisfies the requirements for high-precision and fast sampling of signals at different time periods, and reduces the area of ​​the ADC by reusing the switched-capacitor array and the comparator.

The invention discloses a comparator relative gain-based successive approximation analog-to-digital converter, which relates to the field of integrated circuit design, and comprises a high-order DAC (Digital-to-Analog Converter), a low-order DAC, a four-input comparator and SAR (Synthetic Aperture Radar) logic. Through the relative gain of a four-input comparator, a traditional large-overhead DAC is divided into two small-overhead DACs, namely a high-bit DAC and a low-bit DAC, the high-bit DAC is used for providing reference voltage needed for quantizing M-bit high-bit digital codes, the low-bit DAC is used for providing reference voltage needed for quantizing N-M-bit low-bit digital codes, and therefore N-bit digital codes are achieved. The total number of unit capacitors is reduced to 2M + 1 + 2N-M, the size of the DAC is greatly reduced, and compared with a traditional SAR ADC, the SAR ADC has lower power consumption and area.

The invention relates to the technical field of analog-digital conversion circuit design, in particular to a Flash-ADC circuit and module with three-stage comparison stages. The invention provides a newly designed Flash-ADC (Analog to Digital Converter) circuit. The 15 reference voltages VREF1-VREF15 are divided into three stages for comparison; wherein the comparison result of the first stage controls the selection of the reference voltage of the second stage, and the comparison results of the first stage and the second stage also control the selection of the reference voltage of the third stage, so that the direct comparison of 15 reference voltages with the input voltage is avoided; according to the Flash-ADC circuit, the number of comparators in the circuit and the number of devices of the output coding circuit are reduced, the number of times of comparison is also reduced, and then the power consumption and the area of the Flash-ADC circuit are greatly reduced. According to the invention, the problem that the area and power consumption of the existing Flash ADC are large due to the number of comparators is solved.

A digital-to-analog converter (DAC) circuit, an electronic device including the digital-to-analog converter circuit, and a control method of the digital-to-analog converter circuit are provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switching circuit connected to the first multiplexer; a second switching circuit connected to the second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switching circuit and the second switching circuit, respectively.

To reduce power consumption. A photodetection element includes a plurality of pixels, in which each of the plurality of pixels includes: a physical signal acquisition unit that acquires a physical signal; a comparison unit that compares a physical signal acquired by the physical signal acquisition unit with a reference signal; a signal accumulation floating unit that is electrically connected to one end of the comparison unit; a signal detection unit that is electrically connected to the signal accumulation floating unit and detects a comparison result of the comparison unit; a signal amplification unit that amplifies a detection result of the signal detection unit; a signal storage unit that stores a time code; a signal input / output unit that inputs and outputs a time code; and a signal control unit that performs control to store a time code output from the signal input / output unit in the signal storage unit on the basis of the comparison result, and outputs, to the signal input / output unit, a time code of the time when the comparison result is inverted, the time code being stored in the signal storage unit, and at least two or more of the pixels operate in parallel.