86results about "Power saving provisions" patented technology

The invention discloses an analog signal pulse encoding device based on event driving and an analog signal processing method, and the device comprises a signal conditioning module which comprises at least one conditioning unit, and the conditioning unit is used for receiving an analog signal, carrying out the front-end analog conditioning of the signal, and outputting an analog conditioning signal; the threshold comparison module is connected with the signal conditioning module and is used for carrying out threshold detection on the analog conditioning signal according to a set threshold and then outputting a threshold comparison signal; the event triggering module is connected with the threshold comparison module and is used for triggering a pulse event signal corresponding to the analog conditioning signal according to the threshold comparison signal; and the pulse coding module is connected with the event triggering module and is used for converting the pulse event signal into a pulse coding signal by adopting a pulse coding mode. According to the invention, by introducing the threshold comparison module and the event trigger module at the front end of the device, invalid sampling can be effectively avoided, a large amount of redundant data can be reduced, and power consumption, communication and storage pressure and burden can be reduced.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.

The application discloses a successive approximation type analog-digital conversion device based on a composite dielectric grid and a working method, and belongs to the technical field of semiconductor devices, analog-digital conversion and storage-computation integration. The device is divided into coupling units with different areas according to binary values, and then the control of each weight coupling unit is realized through binary weights. The device does not need large MIM capacitors and complex metal switch trees, thereby reducing area consumption. The on-off characteristics of a semiconductor are utilized, and whether the readout transistor is turned on or not is taken as a comparison result to realize the step-by-step comparison between a two-part interval and an input quantity, thereby avoiding the comparison circuit logic of a circuit stage, so that the power consumption of a quantization unit is significantly reduced. In addition, the device provided by the application has a simple structure, can be extended in a row or column direction in parallel according to actual conditions, and mismatch can be eliminated through code table compensation. The device can be used as an on-chip ADC front end and can also be embedded in a pixel / storage-computation unit as a local quantizer, and has strong versatility.

A top-plate sampling circuitry (10) for sampling a voltage input signal (11), the circuitry comprising: a sampling transistor (110) and a sampling capacitor (120); the sampling transistor being operable as a switch by a gate node (14) according to a tracking phase and a holding phase; a bootstrapper sub-circuitry (140) configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage (155), and to, during the tracking phase, provide the bootstrapped voltage to the gate node; and a gate switch (190) between the gate node and a fixed reference voltage (160), wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time; wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling (180) between the bootstrapped voltage and the gate node.

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

The present disclosure relates to systems and methods for signed conversion. Described herein relate to systems and methods for a converter including a first input, a second input, and a plurality of digital-to-analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a zeroing operation. The DAC cell is configured to provide a data magnitude in a polarity on at least one of the first leg or the second leg during at least a portion of a clock cycle. The data magnitude and the polarity are provided according to a first signal at the first input and a second signal at the second input.

A voltage-to-time converter (VTC) circuit includes an input capacitor being charged according to an input voltage during a precharge operation; an output capacitor being charged during the precharge operation; a first transistor configured to discharge the output capacitor according to a voltage charged in the input capacitor during a first operation following the precharge operation; and a second transistor configured to charge the output capacitor according to the voltage charged in the input capacitor during a second operation following the first operation.

According to an example embodiment, a client device is configured to: obtain a signal sequence configuration defining a plurality of signal sequences, wherein each signal sequence in the plurality of signal sequences corresponds to an uplink transmission power level in a plurality of uplink transmission power levels; transmit the plurality of signal sequences according to the signal sequence configuration to a network node device; receive, from the network node device, an indication about an uplink transmission power level out of the plurality of uplink transmission power levels to be used for uplink transmission; and perform an uplink transmission using the indicated uplink transmission power level to the network node device.

There is provided a method for an apparatus for converting a digital signal into an analog signal, comprising: a weight adjustment unit, configured to adjust a weight of a digital signal having an arbitrary bit order; a conversion unit, configured to output a variable resistance value based on a result of adjusting the weight; and an output unit, configured to output a current signal having a magnitude corresponding to the result based on the resistance value.

The invention discloses a logic control circuit of a successive approximation type analog-to-digital conversion chip. The logic control circuit comprises a shift register, a data register and a logic gate array, the shift register is used for generating a shift signal, and the shift signal is used for controlling the logic gate array to output a switching signal corresponding to each bit in the digital-to-analog converter, and is also used for controlling the data register to store a comparison result output by the comparator; the logic gate array is used for gradually controlling each bit switch of the digital-to-analog converter to be turned on according to a shift signal output by a D trigger in the shift register so as to output a corresponding reference signal; and the data register is used for responding to the shift signals output by the D triggers in the shift register and gradually storing the comparison results output by the comparator into the D triggers at the corresponding positions. The problem that a traditional SAR logic control module is large in resource consumption can be solved.

An analog-to-digital converter includes a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal; a double binary counter having a first input coupled to a first output of the VCO, a second input coupled to a second output of the VCO; a first set of registers coupled to the first output of the double binary counter; a second set of registers coupled to the second output of the double binary counter; sense amplifiers coupled to the outputs of the VCO; and a correction component coupled to the first set of registers, the second set of registers, and the sense amplifiers, wherein the correction component generates a coarse count, a fine count, and combines the coarse count and the fine count to provide a digital output signal representative of the analog input signal.

The application relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-digital converter and a quantization method thereof.The resistance-capacitance hybrid analog-digital converter comprises a CDAC capacitor array connected to the positive input end and the negative input end of a comparator, and the output end of the comparator is connected to a SAR control logic circuit; a reference voltage sampling capacitor unit is selected to be connected between the output end of an RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or to be connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and the reference voltage sampling capacitor unit samples the output voltage of the RDAC; in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and the switching of the RDAC and the CDAC is controlled through the SAR control logic circuit according to the comparison result, so that the successive approximation analog-digital conversion process is completed.

The application relates to the technical field of integrated circuits, and discloses a successive approximation analog-to-digital converter with a data prediction function. The converter comprises a differential capacitor array, a comparator, a control logic module, a prediction control unit and a capacitor switch module. The differential capacitor array is responsible for charge redistribution in the sampling and quantization process; the comparator is used for comparing array output voltages; the control logic module generates a bit-by-bit comparison clock signal; the prediction control unit receives an external prediction signal; the capacitor switch module comprises a plurality of two-way data selectors, the first input end of the two-way data selectors is connected with the comparator output, the second input end is connected with the prediction signal, the output end is connected with a capacitor lower plate, and the enable end receives a mode selection signal. In the prediction mode, the converter directly uses the external prediction signal to set the high-bit capacitor state, skips the previous successive comparison process, thereby significantly reducing the quantization power consumption and improving the conversion speed.

The invention discloses a high-speed successive approximation analog-to-digital converter based on shared biphase dynamic pre-amplification. The analog-to-digital converter comprises a sampling switch, a capacitive digital-to-analog converter, a shared biphase dynamic pre-amplifier, a latch comparator array and a DAC switch control logic. According to the invention, the pre-amplification function is executed by sharing the dual-phase dynamic pre-amplifier; different amplified sampling signals can be effectively compared and latched by combining a latch comparator array; compared with a traditional SAR ADC with the same single quantization time, the overall quantization time is halved; in addition, the mode of sharing the pre-amplification stage is adopted, so that the chip area is saved, and the influence caused by mismatch between latch comparator arrays can be reduced; meanwhile, the latch comparator array can directly store each quantization result, so that the design difficulty and power consumption of the SAR logic circuit are reduced; according to the invention, the speed and power consumption bottlenecks of the SAR ADC are broken through, and the application scene of the high-speed and low-power consumption SAR ADC is widened.

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

A receiver for wired communication includes a DC (direct current) level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is configured to receive a first signal and generate a second signal, in which the DC level shift circuit comprises a capacitor, and the DC level shift circuit is further configured to transmit a first common-mode voltage in a first voltage domain to a first terminal of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second terminal of the capacitor before the first signal is received, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is configured to generate a digital signal according to the second signal.

The invention discloses a high-precision low-delay analog-to-digital converter based on a capacitor multiplexing type redundancy bit, which adopts a successive approximation type architecture, is provided with at least one redundancy bit realized based on capacitor multiplexing, and comprises a DAC (Digital-to-Analog Converter) capacitor array, a comparator, an SAR (Synthetic Aperture Radar) logic circuit, a sampling hold circuit and a latch, a positive-phase capacitor array and a negative-phase capacitor array of the DAC capacitor array each comprise M capacitor units, the capacitor unit in front of each redundant bit comprises a non-reusable capacitor and at least one reusable capacitor, and the weight of the at least one reusable capacitor is sequentially and correspondingly equal to the weight of the redundant bit and the weight of the redundant bit behind the redundant bit; the weight of each redundancy bit is smaller than or equal to the weight of the capacitor unit of the previous bit of the redundancy bit. According to the analog-to-digital converter, the reusable capacitor serves the non-redundant bits and the redundant bits in different comparison periods respectively, so that redundancy correction is achieved, and the analog-to-digital converter has the advantages that the quantization range is not reduced, the redundant bits are flexibly configured, and the power consumption of the analog-to-digital converter is reduced.

An interpolation type time-to-digital converter based on pre-judgment partial activation comprises a reference voltage generating circuit, a parallel converter array, a parallel pre-judgment circuit array, an interpolation TDC, a one-hot code encoder and a binary encoder which are connected in sequence, and a pre-judgment auxiliary converter which is connected with the parallel converter array and the parallel pre-judgment circuit array respectively, dynamic partial activation is achieved through a pre-judgment mechanism, and the method is suitable for any VTC structure and has wider applicability and lower dynamic power consumption. Meanwhile, the decoding logic structure is simple, extra delay is not introduced, and the method is suitable for a high-speed low-power-consumption time domain ADC system.

A flux pump DAC (digital-to-analog converter) includes a ring in the Josephson transmission line (JTL) stage. The ring includes multiple injector Josephson junctions (JJs). Each injector JJ can be individually operated to inject flux into the ring in a given AC clock cycle, or can be controllably stopped to not inject flux during a given AC clock cycle. The flux pump DAC further includes a load inductor coupled to the ring JJs of the ring. The load inductor is configured to store the flux injected into the ring. Because the flux pump DAC includes multiple injector JJs arranged along the JTL ring, it can ramp up the current stored in the load inductor at a faster rate than a single-injector flux pump DAC, and the ramp speed can be precisely and variably controlled, thus improving thermal insulation.

An adaptive current generation circuit includes an inverter drive chain, a frequency divider, a frequency detector, a low-pass filter, a static comparator group, and a controllable current mirror. An input analog signal of the input buffer is converted into a frequency discrimination voltage in a direct current form sequentially through conversion of the inverter drive chain, frequency division of the frequency divider, frequency detection of the frequency detector, and conversion of the low-pass filter. Then the static comparator group performs a plurality of times of comparison to obtain N bits of digital codes. Finally, the controllable current mirror is controlled by using the N bits of digital codes. The controllable current mirror provides a magnitude-adjustable input current for the input buffer under control of the N bits of digital codes. A magnitude of the input current is positively correlated with a frequency of the input analog signal.

An analog to digital converter configured to acquire a first sample comprising a first plurality of bits representative of a digital signal, determine one or more bit positions within the first plurality of bits that are variable, determine one or more bit positions within the first plurality of bits that are static, and acquire a second sample after having acquired the first sample, the second sample comprising a second plurality of bits representative of the digital signal, at least a portion of the one or more bit positions that are variable have their bit values generated by sampling the analog signal, and each of the one or more bit positions that are static have their bit values set to the same bit value as the bit value of the corresponding bit position in the first sample.

The application discloses a signal sampling method, system and device of a digital-to-analog converter and a storage medium, and the method comprises the following steps: obtaining a first sampling result and a second sampling result of the low-power consumption prediction ADC; the first sampling result is used for representing a quantization result of an input ADC signal in a previous sampling period after analog-to-digital conversion; the second sampling result is used for representing a quantization result of an input ADC signal in a current sampling period after analog-to-digital conversion; determining that the first sampling result is not equal to the second sampling result, and switching the connection between a group of differential capacitor digital-to-analog converters of the main ADC and a reference voltage. The method can reduce the power consumption of signal sampling of the digital-to-analog converter. The application can be widely applied in the technical field of signal sampling.

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

The invention provides an analog-to-digital conversion device and method. The analog-to-digital conversion device includes: an analog-to-digital converter, wherein the analog-to-digital converter includes N successive approximation register (SAR) analog-to-digital converters and M slope analog-to-digital converters, N is a positive integer greater than or equal to 1, and M is a positive integer greater than 1; output ends of the N SAR analog-to-digital converters are connected to input ends of the M slope analog-to-digital converters.

A unit capacitor for a switched-capacitor digital-to-analog converter is provided. An apparatus includes a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

A semiconductor device of a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit to which an output signal of the amplifier is input and which holds a voltage corresponding to the output signal, an analog-digital conversion circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of controlling switching during a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is held in the sample-and-hold circuit, and a second control period in which a digital signal obtained by outputting the voltage held in the sample-and-hold circuit to the analog-digital conversion circuit is output to the interface circuit. The analog-digital conversion circuit is switched to stop the output of the digital signal during the first control period. The first control period is longer than the second control period.

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate first digital data of N bits and second digital data of N bits of analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSB) having the same value, the SAR ADC may be used in partial mode to generate third digital data of N bits of the analog data. In the partial mode, the SAR ADC is configured to skip determining a second MSB sequence of the third digital data and determine only remaining bits of the third digital data. When the second digital data and the first digital data do not include the first MSB sequence having the same value, the SAR ADC operates in a full mode to determine each bit of the N-bit third digital data.

The invention discloses an analog to digital converter integrated with reference voltage generation and a calibration method. The analog to digital converter integrated with reference voltage generation comprises a sample-hold circuit, a capacitive digital to analog converter and a quantizer. The sample-and-hold circuit is configured for sampling and holding an analog input signal to obtain a first signal; the capacitive digital to analog converter is configured for generating a reference signal and generating a second signal in equal proportion to the reference signal according to a feedback digital output signal, and differencing the first signal and the second signal to obtain an error signal; and the quantizer is configured for digitizing the error signal to obtain a digital output signal. The analog to digital converter is internally provided with a high-precision reference source, which directly generates the reference signal in the capacitive digital to analog converter of the analog to digital converter without needing an additional reference signal generating circuit and an additional reference signal driver, thus solving defects of large power consumption, area and error and the like of a conventional architecture, and realizing output calibration only by one-step calibration, reducing system calibration cost and achieving high precision.

An example semiconductor device includes a plurality of analog-to-digital converters (ADCs) configured to receive an analog signal from at least one amplifier connected to a pad, and a logic circuit configured to control the plurality of ADCs. The logic circuit is configured to activate first active ADCs, among the plurality of ADCs, in a first operating mode, and to activate second active ADCs, among the plurality of ADCs, in a second operating mode different from the first operating mode. A first latency required for the first active ADCs to receive the analog signal and to output a first digital signal is longer than a second latency required for the second active ADCs to receive the analog signal and to output a second digital signal.