Dynamic gain switching digital to analog converter

Abstract

A digital to analog converter that may include a digital gain block; an analog gain block; a digital to analog conversion (DAC) block and a controller that is configured to: determine a digital gain factor, selected out of multiple digital gain factors, of the digital gain block and an analog gain factor, selected out of multiple analog gain factors of the analog gain block; wherein the DAC block is preceded by the digital gain block and is followed by the analog gain block; wherein the digital gain block is configured to multiply a digital input signal by the digital gain factor to provide an intermediate digital signal; wherein the DAC block is configured to convert the intermediate digital signal to a converted analog signal; and wherein the analog gain block is configured to multiply the converted analog signal by the analog gain factor to provide an output signal; wherein an increment of the analog gain factor results in a decrement of the digital gain factor.

Description

RELATED APPLICATIONS[0001]This application claims priority from U.S. provisional patent Ser. No. 61 / 946,808, filing date Mar. 2, 2014 which is incorporated herein by reference.FIELD OF THE INVENTION[0002]This invention relates to the field of low noise digital to analog converters.BACKGROUND OF THE INVENTION[0003]Digital to analog converters (DAC) are used at the end of a digital processing chain where analog signal reproduction is required. Such uses include digital audio devices such as Compact Disc / MP3 players, HD radio and digital telephones. In all these applications, it is highly desirable to achieve a high signal to noise ratio (SNR) at the analog output while achieving the required, maximum high output signal level. In DAC applications, SNR is defined as the ratio between RMS of maximum amplitude output divided by the RMS of the integrated noise floor with no signal present and integrated within the frequency band of interest. SNR is usually specified in decibels (dB). For e...

AI Technical Summary

Benefits of technology

The patent describes a method and apparatus for digital to analog conversion. The method involves receiving a digital input signal, determining a digital gain factor and an analog gain factor, multiplying the digital input signal by the digital gain factor to provide an intermediate digital signal, converting the intermediate digital signal to a converted analog signal, and multiplying the converted analog signal by the analog gain factor to provide an output signal. The apparatus includes a digital to analog converter with a digital gain block, an analog gain block, a digital to analog conversion (DAC) block, and a controller. The controller determines the digital gain factor based on attributes of the digital input signal, such as level, amplitude, or derivative, and selects the appropriate digital amplifying path or adjusts the analog gain factor accordingly. The technical effects of the invention include improved accuracy and precision in digital to analog conversion and improved performance of the analog amplifying paths.

Problems solved by technology

Electronic noise is inherent in all analog circuits.

In mobile applications however, battery capacity limits available supply power and power consumption must be minimized.

Second there is the resistor noise, thermal and flicker, which is related to the value of the transimpedance.

Third there is the amplifier input referred noise that is created primarily in the input stages of the amplifier and which is not related to the value of the transimpedance.

This results in a practical limit to the noise floor when limited by DAC and amplifier power consumption.

In many cases the DAC architecture also imposes similar limits on its output voltage range.

The problem is that increased voltage gain also amplifies the noise at the output of the amplifier.

The need to meet the gain criteria using the transimpedance amplifier effectively sets a limit on the noise levels and the result is that the desired noise levels and hence the signal to noise ratio of the output signal for state-of-the-art applications and devices is difficult to meet.

In other cases of DAC architectures such as voltage-mode DACs, similar noise analysis can be performed and similar design issues limit SNR

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