95 results about "Flash ADC" patented technology

A ultra high speed photonic Analog to Digital Converted (ADC) for sampling and quantizing an electrical voltage signal, internally enabled by photonics uses coherent optical detection architectures for photonic quantization. Coherent light is phase modulated by the test signal. Using an interferometer, or an array of interferometers the phase of modulated light is compared with a reference light. Flash ADC, successive approximation ADC and delta-sigma ADC configurations are presented.

A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. Reducing power consumption of a SAR system can be readily accomplished by reducing comparator supply voltage. For a SAR converter architecture using a CAPDAC array or CAPDAC (capacitor array DAC), fairly large variations in comparator input voltage can be expected under these circumstances. If the input voltage variation becomes too large, damage to the comparator input devices can occur, or inaccuracies may develop. In one embodiment of the invention, the most significant bits are provided by sampling the input signal through a flash ADC that does not suffer from the input voltage restriction described above.

A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency F_S and the chopping switches can operate at F_S or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.

Broadband access networks are driving the upgrade of DWDM networks from 10 Gb/s per channel to more spectrally-efficient 40 Gb/s or 100 Gb/s. Signal quality degradation due to linear and non-linear impairments are significant and error control coding and signal processing solutions play increasingly key roles in meeting increasing demand, providing improved quality of service, and reduced cost. It would be beneficial to reduce the power consumption of optical receivers for optical links exploiting for example LPDC encoding. Accordingly, the inventors have established a low complexity soft-decision front-end compatible with deployable LDPC codes in next-generation optical transmission systems. Beneficially the optical receiver design can be retro-fitted into deployed hard-decision based optical systems and replaces the 3-to-2 encoder of the prior art in the electrical portion of the receiver with a single gate design. Further, the design may act as a 2-bit Flash ADC in multimode fiber based optical receivers.

A thermometer code to sign and magnitude converter that is particularly useful in a flash ADC is provided. This comprises two conversion units. The first is a thermometer code to Gray code converter and the second a Gray code to sign and magnitude converter. Preferably, the Gray code is of a kind that has a sign bit and has the other bits symmetrically disposed about zero. This form is easily converted to a sign and magnitude code, which is advantageous as it reduces the latency of the converter, which is particularly useful at high data rates.

A method for providing dynamic element matching of capacitors in a pipelined analog to digital converter (ADC). Instead of randomizing the output of a flash ADC before providing the output of the ADC to the capacitor array, the threshold voltages from a reference ladder are randomized. This eliminates multiple, series connected switches of a randomizer between the output of a comparator bank and the capacitor array, and may be done during the time the output of the comparator bank of the flash ADC is latched, thereby not negatively impacting the speed of operation of the pipelined ADC.

A differential analog-to-digital data converter (ADC) is disclosed for receiving a positive input signal and a negative input signal. A distributed resistive device is provided having taps associated therewith. A plurality of comparators each having a signal input and a reference input are provided, the signal input connected to one of the positive and negative input signals and the reference input connected to a tap on said distributed resistive device. A driver drives current through the distributed resistive device with one of the taps of the distributed resistive device disposed at substantially the other of the positive and negative input signals. A current varying device varys the current through the distributed resistive device to vary the voltage between taps.

Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency. In the multi-bit pipeline ADC, an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency, so that power consumption can be minimized under the corresponding operating condition and signals can be processed in a variety of ways.

A hybrid Analog-to-Digital Converter (ADC) has multiple stages. A first stage and a final stage each use a Successive-Approximation Register (SAR) ADC to generate the Most-Significant-Bits (MSBs) and the Least-Significant-Bits (LSBs) over successive internal cycles. Middle stage(s) use a faster flash ADC with multiple comparators in parallel to generate the middle binary bits, which are then re-converted by a Digital-to-Analog Converter (DAC) and subtracted from the stage's input analog voltage to generate a difference that is amplified by a residual amplifier that outputs an amplified voltage to the next stage. The first stage also has this multiplying DAC structure to convert the MSBs to an amplified voltage to the first of the middle stages. Finally, digital error correction logic removes redundant binary bits between stages. Initial and final SAR stages of 4 and 8 bits with a 4-bit middle stage provide a hybrid ADC of 14-bit precision.

Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.

The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n−k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

A field programmable gate array based multi-channel flash ADC unit combined with a high speed multi-lane data communications channel/Ethernet-like modular intercommunication providing a complete but easily expandable high-speed data acquisition system. This apparatus and method permits high-speed pulse-shape digitalization allowing position resolution imaging of particles having a range of energies and is scalable to achieve the efficient capture of coincident data from large electromagnetic detector arrays.

Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

The invention discloses a 12-bit high speed streamline analog-to-digital converter with a background calibration function. The 12-bit high speed streamline analog-to-digital converter with a background calibration function utilizes a sample hold circuit structure without a front end and the whole streamline has five levels, wherein the first streamline level is 3.5-bit; the second streamline level to the fourth streamline level are 2.5-bit; and the fifth streamline level is 3-bit flash ADC. The 12-bit high speed streamline analog-to-digital converter with a background calibration function is featured in that in the streamline, the first streamline level utilizes a 3.5-bit MDAC structure with overflow bit and is integrated with a sampling time deviation calibration module which is used for realizing correction of the sampling time deviation of two sampling networks including an MDAC and a sub ADC; besides, the analog-to-digital converter also includes a reference voltage generation circuit which is used for providing stable reference voltage for each streamline level, a clock generation circuit which is used for providing a accurate clock for each streamline level, and a redundancy correction circuit for misalignment addition of output coding. The 12-bit high speed streamline analog-to-digital converter with a background calibration function of the invention has the advantages of being low in power consumption, and being able to realize high speed application when the process size is small.