17 results about "Flash ADC" patented technology

The present application relates to the technical field of CMOS image sensor design, and in particular to a two-step ADC circuit and module based on Flash architecture optimization. The present application provides a two-step ADC circuit based on Flash architecture optimization, which comprises a data input unit, a comparator unit, a Flash-ADC unit, a voltage lifting unit, an SS-ADC unit, and a result output unit. The present application combines SS ADC and Flash ADC to form a two-step ADC, and further splits the quantization of the Flash-ADC unit, so that the number of comparators is reduced from 7 to 4 while keeping the quantization time unchanged, effectively reducing the circuit area.

The application relates to a dual-mode FLASH-SAR ADC conversion circuit and method, the circuit comprising a FLASH ADC module, a SAR ADC module, a clock control module and an encoding module. In reference mode one, the FLASH ADC module is a single-end structure, the FLASH ADC module samples the voltage division of a first reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the voltage division of the first reference voltage and an input signal respectively in a sampling stage, and all the sampling capacitors in the SAR ADC module sample the input signal. In reference mode two, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of a second reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the second reference voltage and the input signal respectively in a sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal. The ADC circuit resources are greatly saved, and the application cost is saved.

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

An apparatus as discussed herein can be configured to include a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal. Additionally, the apparatus can be configured to include an integrator function as well as a digital to analog converter. The integrator function is operable to produce a digital value representative of an analog input voltage, the digital value adjusted based on samples of the digital error voltage signal generated by the delay line analog-to-digital converter. The digital-to-analog converter operative to convert the digital value received from the integrator function into a second analog voltage, the analog error voltage being a difference between the input voltage and the second analog voltage.

The application provides a high-speed Flash-SAR hybrid analog-digital converter and belongs to the technical field of chips.The application comprises a sampling switch, a Flash ADC, a comparator, a capacitive digital-analog converter, a successive approximation register and a digital error correction circuit.The application adopts a full-differential structure, an input signal is rapidly converted into a 3-digit code through the Flash ADC, meanwhile, the conversion of a high 3-digit capacitor corresponding switch of the capacitive digital-analog converter is controlled, and the conversion of the following digit is completed through the comparator.The capacitive array is divided into two sections, each section of capacitors adopts a capacitive architecture design based on binary error compensation, so that the errors caused by the imbalance of the comparator, the incomplete establishment of the top plate voltage and the thermal noise of the conversion switch itself are reduced;and due to the existence of the encoding circuit in the Flash ADC, the conversion from the thermometer code to the binary code is realized, the area of the chip is saved, and the power consumption is reduced.

The application relates to a power supply voltage detection circuit, an electronic device and a detection method. The power supply voltage detection circuit comprises a first switch, a control circuit and a detection circuit. One end of the first switch is connected with a power supply end, and the other end of the first switch is connected with the ground. The control circuit is used for keeping the first switch on during detection and controlling the detection circuit to work, and is used for controlling the first switch to be turned off after the detection is completed. The first switch is used for inputting a target voltage into the detection circuit when being turned on and stopping the generation of the target voltage when being turned off. The detection circuit is used for obtaining a detection result according to the target voltage and a preset reference voltage. The target voltage is related to the power supply voltage. The method can reduce the static power consumption of a Flash ADC.

The invention relates to the technical field of CMOS (Complementary Metal Oxide Semiconductor) image sensor design, in particular to a two-step ADC (Analog to Digital Converter) circuit and module based on Flash architecture optimization. The invention provides a two-step ADC (Analog to Digital Converter) circuit based on Flash architecture optimization. The two-step ADC circuit comprises a data input part, a comparator part, a Flash-ADC part, a voltage boosting part, an SS-ADC part and a result output part. According to the invention, the SS ADC and the Flash ADC are combined to form the two-step type ADC, and further splitting is carried out on the quantization of the Flash-ADC part, so that the number of comparators is reduced from 7 to 4 under the condition that the quantization time is kept unchanged, and the circuit area is effectively reduced.

The invention belongs to the field of integrated circuits, and particularly relates to an ADC circuit based on an RRAM quantizer and a neural network encoder. An OTA circuit is adopted to convert input voltage into current and output the current to a current mirror circuit, a plurality of comparison and judgment circuits complete quantization of the input voltage by comparing charging current of a fixed size with discharging current of different sizes, and a quantization result is a 01 sequence of a specific length; inputting the 01 sequence into a neural network model to output and generate a new comparative judgment circuit control voltage; and secondary quantization is carried out through a neural network model, so that the ADC precision is improved. The temperature can also be used as an input variable of the neural network, and errors caused by the temperature are further calibrated. According to the invention, the RRAM and the neural network are combined, two rounds of calibration are continuously carried out through the neural network module and then final output is carried out, the quantization and calibration process is optimized, the conversion speed, PVT robustness and precision of the ADC circuit are effectively improved, and the problems of the traditional Flash ADC circuit are solved.

A galvanically isolated current sensor for power converters is disclosed. The sensor includes a package housing a first integrated circuit (IC), a light emitting layer, an optical waveguide, a photosensing layer, and a second IC. The light emitting layer emits light proportional to a reference current. The optical waveguide modulates the light based on a magnetic field generated by the current to be sensed. The photosensing layer generates a photocurrent representative of the modulated light's intensity. The second IC outputs a sense current based on the photocurrent. The optical waveguide includes polarizers and a Faraday rotator material to effectuate the modulation. Different embodiments of control circuitry for processing the sense current are described, including a flash ADC-based system, a voltage-controlled oscillator with a high-speed counter, and a current-controlled delay line with a low-speed counter.

This invention discloses a reinforcement learning-based dynamic baseline and threshold adaptive adjustment system for a Flash ADC, comprising a signal acquisition module, a state feature extraction module, a reinforcement learning agent, an execution control module, a reward function calculation module, and a learning update module. This invention also provides a method for operating the reinforcement learning-based dynamic baseline and threshold adaptive adjustment system for a Flash ADC. This scheme, through interaction between the reinforcement learning agent and the ADC system, autonomously makes decisions based on real-time state to adjust the baseline and threshold voltages, dynamically optimizing multiple performance indicators such as signal-to-noise ratio, baseline stability, and detection efficiency. This solves the problems of insufficient adaptability and performance imbalance of traditional methods in complex time-varying environments, significantly improving measurement accuracy and reliability.

In an example, a system (100) includes a pipelined analog-to-digital converter (ADC) having a primary path (120) and a secondary path (122). The main path (120) includes a first stage (102) having a sampling switch (110), a flash ADC (112) having an input coupled to the sampling switch (110), a digital-to-analog converter (DAC) (114) having an input coupled to an output of the flash ADC (112), and a first amplifier (118) having an output coupled to the DAC (114) and an input of the sampling switch (110). The main path (120) includes a second stage (104) coupled to the first stage (102) and an input of a second amplifier. The main path (120) also includes a back-end ADC (106) having an input coupled to an output of the second amplifier. The auxiliary (122) path includes a plurality of metastable state comparators (124) coupled to the flash ADC (112).

The application discloses a low-temperature high-energy-efficiency in-memory computing accelerator.The application has the following innovations: a high-retention-time low-temperature 3T memory cell design: the application proposes a low-temperature 3T memory cell design based on eDRAM, which can significantly improve the retention time without any word line voltage boosting scheme, and realize full-swing data transmission during the write operation process; a low-temperature adaptive reconfigurable sensitive amplifier design: the application develops a low-temperature on-chip adaptive reconfigurable sensitive amplifier design, which can realize accurate on-chip Boolean logic calculation by configuring the reference voltage of ARSA; a low-temperature optimized Flash ADC design: the application uses the designed ARSA to adaptively generate 15 ARSA reference voltages on the chip and reconfigure them into 4bit Flash ADCs.Through the adaptive configuration of the reference voltage and the storage mode on the chip, the design can ensure the realization of fast and low-power consumption convolution calculation.

This application discloses a processing chip, a digital low-dropout regulator, and an electronic device, relating to the field of integrated circuit technology. The processing chip includes a processing circuit and a digital low-dropout regulator. The digital low-dropout regulator includes a flash analog-to-digital converter (ADC), a first switching circuit, and a second switching circuit. The flash ADC drives the second switching circuit in response to a voltage output terminal voltage less than a threshold voltage, causing at least a portion of the second switches in the second switching circuit to conduct. This allows for rapid charging of the voltage output terminal through the conducted second switches, promptly raising the voltage output terminal and improving voltage drop. This results in higher transient response speed and improved performance in mitigating voltage transient drops, ensuring the normal operation of the processing circuit. Furthermore, in response to a voltage output terminal voltage greater than or equal to the threshold voltage, the second switching circuit is driven to disconnect each of the second switches, reducing power consumption.

In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.

Systems and methods for analog-to-digital conversion are described. A device can include a successive approximation register (SAR) analog-to-digital converter (ADC) and a flash ADC with a fractional bit resolution. The flash ADC can determine a digital code that encodes a voltage range of an input voltage, provide redundancy for digital error correction and output the digital code to the SAR ADC. The SAR ADC can decode the digital code to obtain a first set of bit values of a set of most significant bits (MSBs) of a digital output that is a digital representation of the input voltage, determine a second set of bit values of a set of least significant bits (LSBs) of the digital output, and generate the digital output based on the first set of bit values and the second set of bit values.

The application discloses a digital LDO structure, comprising: a 3-bit continuous-time flash ADC, which is used for comparing an output power voltage Vreg with 7 reference voltages to generate a 7-bit digital signal COMP<6:0>, wherein 7 is a positive integer; a digital control logic, an N-bit decimal index array, which is connected with a load circuit and the digital control logic respectively; and the load circuit is grounded. The digital control logic is used for controlling the switch quantity of a PMOS tube of the N-bit decimal index array by detecting the change of the 7-bit digital signal COMP<6:0>, and then adjusting the size of the output power voltage Vreg. The application has the advantages of accelerating the response speed, having no output capacitor, improving the dynamic range and reducing the steady-state power consumption.