98 results about "Offset calibration" patented technology

An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier, a reading circuit and a module based on bit line switch and capacitance coupling. The invention discloses a DRAM (Dynamic Random Access Memory) sensitive amplifier based on bit line switch and capacitance coupling. The DRAM sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors Cc1-Cc2. The SCSA is designed and matched with corresponding control logic, so that a pre-charging stage, an offset calibration stage, a charge sharing stage, a pre-induction stage and a main induction stage are designed when the SCSA reads a DRAM storage unit, the potential of a bit line BLT or BLB can be correctly changed, and the SCSA reading amplification function is guaranteed. Compared with a traditional DRAM sensitive amplifier, the SCSA provided by the invention has the advantages that the offset voltage index is greatly reduced under the condition that the number of elements is not greatly increased, and the sensing margin is effectively increased.

In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.

The invention discloses a dual-mode offset calibration circuit applied to a comparator of a high-speed time domain interleaving ADC (Analog to Digital Converter). The dual-mode offset calibration circuit comprises a calibration logic, n channels and a configurable resistor string, wherein the calibration logic comprises detection logic and compensation logic; each channel is respectively connected with the calibration logic and the configurable resistor string; any one of the n channels comprises a switch array, a latch array and a comparator. The noise influence in the comparator imbalance detection process is reduced through the detection logic provided by the invention; a calibration logic and a configurable resistor string are multiplexed by a plurality of channels, so that the power consumption and the area of the circuit are greatly reduced; the configurable resistor string correspondingly selects a coarse calibration mode or a fine calibration mode according to the obtained external signal MODESEL, the coarse calibration mode has a larger calibration range and a higher convergence speed compared with the fine calibration mode, and the fine calibration mode has higher calibration precision compared with the coarse calibration mode.

The invention provides a novel time offset calibration circuit and method, and belongs to the technical field of analog ICs. Comprising a buffer A and a buffer B which are connected in sequence, the output node of the buffer A is grounded through a capacitor, the output node of the buffer A is grounded through a resistor and a current source set controlled by a switch, and the output end of the buffer B is connected with a time offset detection circuit. According to the clock offset calibration circuit provided by the invention, a novel topological structure is adopted, and the calibration range of time offset can be greatly expanded without a lengthy buffer chain, so that the introduction of noise is reduced. The time offset adjustment step length of the circuit structure is not limited by the minimum size of the capacitor, and has no extremely high matching requirement on the capacitor. The time offset calibration with a small step length can be realized by controlling the extracted current, and the calibration precision is ensured while the calibration range is improved.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

The present invention proposes a dynamic comparator offset calibration circuit based on an adjustable charge pump, comprising: a comparator, a charge pump circuit, and a logic control circuit. The calibration input of the comparator serves as the output of the circuit, the output of the comparator is connected to the input of the charge pump circuit, and the control end of the charge pump circuit is connected to the output of the logic control circuit. Whenever the output of the comparator changes, the logic control circuit generates a corresponding pulse to control the on / off switching of the charge pump circuit to adjust the charge and discharge rate of the charge pump. The present invention implements a novel calibration technique for high-speed dynamic comparators. The circuit utilizes an adjustable charge pump circuit based on capacitor charge sharing to control the calibration process, thereby reducing the offset voltage of the comparator. The selection of such a value provides a sufficient calibration range and generates negligible calibration noise.

This invention discloses a dynamic comparator for a successive approximation analog-to-digital converter (ADC), relating to the field of comparator technology. The dynamic comparator includes: a cascaded pre-amplifier circuit and a latch circuit; the pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; the differential input pair is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair; the first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair; the positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit. This invention addresses the problems of large footprint and difficult offset calibration in existing successive approximation ADCs.

The invention discloses a voltage buffer, a voltage buffering method, a display driving chip and electronic equipment, and belongs to the technical field of display. The voltage buffer comprises a voltage buffer module and an offset calibration module. The voltage buffer module comprises a first output stage and a second output stage. The voltage buffer module is used for outputting a first output voltage to a load through the first output stage in a non-calibration mode; or in the calibration mode, a second output voltage is output to the imbalance calibration module through the second output stage; and the offset calibration module is used for performing current compensation on the voltage buffer module based on the second output voltage under the condition that the second output voltage is received so as to calibrate the direct current offset of the voltage buffer module. Therefore, the direct current offset of the voltage buffer module is calibrated in a current compensation mode, and due to the fact that the establishment time of the second output voltage in the calibration mode is short, the offset calibration speed is increased.

A receiver circuit and a method of operating the receiver circuit are provided. The receiver circuit includes: a first stage circuit configured to perform a waveform adjustment or amplification operation on first and second input differential signals; a replica circuit configured to receive a common mode voltage and perform a waveform adjustment operation or amplification operation on the common mode voltage; a multiplexer that is configured to output one of an output of the first stage circuit and an output of the replica circuit as first and second intermediate differential signals based on an offset calibration enable signal; and an offset calibration logic configured to receive a digital signal generated based on the first and second intermediate differential signals, and perform an offset calibration operation based on the digital signal.

The invention provides an offset calibration method and device, and the method comprises the steps: detecting at least one time period in which a DDR controller forbids to access SDRAM particles, and then carrying out the offset calibration operation on the data transmission delay on a whole data transmission link in the at least one time period, thereby not needing to independently occupy the bandwidth resources of a system, and improving the data transmission efficiency. The bandwidth utilization rate can be improved, and the stability of data transmission is improved.

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

The invention relates to a radio frequency power detector with offset and temperature compensation. Wireless circuitry may include a transmit line carrying a signal and a power detector measuring the signal. The detector may include a rectifier coupled to the comparator through a differential path. An offset calibration digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may generate an offset compensation voltage by superimposing different offset voltages over time to a voltage on the second line. The reference generator may generate a set of threshold voltages by superimposing different reference voltages to the offset compensation voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to the negative input of the comparator.

The invention provides an OPA linear offset calibration circuit, and the circuit is characterized in that the circuit comprises a comparison module which compares the voltages of the positive and negative input ends of an operational amplifier, and obtains an offset voltage; the positive end calibration module is used for calibrating by adopting a decoding calibration mode when the offset voltage is less than zero; and the negative end calibration module is used for calibrating by adopting a binary calibration mode when the offset voltage is greater than zero. According to the invention, decoding calibration is adopted for negative offset, binary calibration is adopted for positive offset, continuous linear calibration is realized, decoding calibration is only adopted for negative offset, one high bit b < it > is omitted, logic control units required by decoding calibration are reduced, and decoding is simpler.

Disclosed are an offset calibration method and circuit applied to a comparator array. The offset calibration circuit includes a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits; an entire comparator array shares the single global calibration voltage generation module, and each of the comparators only needs to introduce an integrator circuit, such that a large calibration range and a small calibration step are achieved, a long calibration cycle and a large circuit area are required, and the requirements for a low area are satisfied. The offset calibration method provided by the present disclosure is similar to a binary search algorithm, which is adopted to search for the offset voltage, the calibration step of12N⁢Vrefcan be realized by only N cycles, and short calibration time is thus realized.

The invention discloses a common-mode compensation and offset calibration circuit, a chip and equipment, and belongs to the technical field of integrated circuits. The circuit comprises a common mode compensation circuit used for injecting a constant first common mode compensation current to an output node ON of a differential amplifier and injecting a constant second common mode compensation current to an output node OP of the differential amplifier; the equalizer tap is used for adjusting tap current according to a control word TAP, the tap current is respectively connected with two nodes ON and OP through two switch tubes, and the two switch tubes are controlled by feedback signals Dn and Dp output by a decision device; an offset calibration circuit comprising a first current branch connected to the node ON and a second current branch connected to the node OP; wherein the current on the two current branches is regulated and controlled according to the tap current, so that the sum of the tap current and the current on the offset calibration circuit is equal to the current injected by the common mode compensation circuit. According to the invention, the magnitude of the common-mode compensation current does not change along with the change of the tap current of the equalizer.

The application provides a low-cost design scheme suitable for common-mode recovery of an XGS-PON OLT BM-LA. A DCOC module calibration circuit is composed of a low-pass filter, an amplifier, a comparator, a digital controller and a current differential DAC. The low-pass filter and the amplifier respectively extract and scale the DC offset; the comparator distinguishes the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the CMP until the DC offset calibration is completed.

The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

The invention provides an offset calibration method and an OLDI interface test method and device. Relates to the technical field of data transmission. According to the specific implementation scheme, a first data stream is input into a first register and a second register of a control chip in sequence, and a target processing signal output by the first register or the second register is obtained; calibrating the first data stream based on a target instruction in the target processing signal and then inputting the first data stream to a corresponding data channel in the OLDI interface; wherein the target instruction is determined according to a display result which comprises calibration information and is output by the display after the Lth round of data transmission is finished. According to the embodiment of the invention, the offset among the plurality of data channels in the interface is calibrated, so that the condition of data transmission errors caused by the offset can be effectively eliminated, and the accuracy of data transmission can be improved.

The invention is suitable for the technical field of offset calibration, and provides a programmable gain amplification circuit and an offset calibration method thereof. The programmable gain amplification circuit comprises an operational amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, a first adjustable resistor, a second adjustable resistor, a first input end, a second input end and a controller, one end of the first adjustable resistor is connected with the non-inverting input end of the operational amplifier, the other end is connected with common voltage, one end of the second adjustable resistor is connected with the inverting input end of the operational amplifier, and the other end is connected with the common voltage; the controller adjusts the resistance value of the first adjustable resistor and / or the resistance value of the second adjustable resistor, so that the output voltage difference of the operational amplifier is smaller than a preset voltage difference threshold value. According to the embodiment of the invention, the influence caused by the voltage offset of the pre-stage circuit can be effectively eliminated, and meanwhile, only two adjustable resistors are added, so that excessive chip area is not occupied, and excessive power consumption is not consumed.

The present disclosure relates to a semiconductor device performing offset calibration. A semiconductor device includes a calibration control circuit, a first data input / output block, and a second data input / output block. The calibration control circuit generates a master clock signal and a calibration control signal for an offset calibration operation. The first data input / output block adjusts an offset of the first data input / output block based on the master clock signal, the calibration control signal, and a reference voltage. The second data input / output block adjusts an offset of the second data input / output block based on the master clock signal, the calibration control signal, and the reference voltage.

This invention relates to the field of robot navigation technology, specifically to a dynamic zero-bias calibration method for robot navigation based on multi-sensor fusion. The technical solution includes: acquiring IMU measurements and velocity data; determining whether the current operating state is stationary based on the IMU measurements; if so, entering a static calibration mode, continuously acquiring IMU data in the stationary state and processing it to obtain an initial zero bias; if not, calculating the fusion residual value between the current IMU measurement and the multi-sensor fusion estimate; validating the acquired key constraint information by determining whether it exceeds the corresponding threshold range; if not, no correction is performed; if so, progressive zero-bias correction is applied to the IMU measurements to obtain corrected measured values, and subsequent IMU measurements are then used for zero-bias compensation correction. This invention uses a two-level calibration architecture of static calibration and online estimation, combined with a multi-sensor fusion algorithm and a progressive correction strategy with a minimal learning rate, to achieve accurate, real-time, and stable calibration of IMU zero bias.

The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

This invention relates to the field of metrology calibration, and more particularly to an adaptive calibration method, apparatus, device, and storage medium for a metrology box. The method includes the following steps: powering on the metrology box normally, performing self-operating noise detection, and constructing a self-operating noise feature set; performing initial calibration and real-time metrological detection on the metrology box based on the self-operating noise feature set, outputting multiple metrological data sequences; performing sequence-by-sequence feature analysis and differential calculation of adjacent time periods based on the multiple metrological data sequences to obtain a feature difference value sequence; synchronously acquiring environmental monitoring parameters of the metrology box; tracing environmental interference sources based on the environmental monitoring parameters and marking interference sources; performing offset calibration based on the interference sources to obtain offset calibration reference parameters; and performing real-time operating condition metrological detection based on the offset calibration reference parameters. This invention achieves accurate and efficient metrology box detection and calibration.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

An analog-to-digital converter (ADC) and a method for calibrating a comparator within the ADC are provided. The ADC includes a sampling capacitor array, the comparator, an offset calibration control switch and a control logic, where the offset calibration control switch is coupled between the sampling capacitor array and the comparator. In a sampling phase, the sampling capacitor array samples an input signal, the offset calibration control switch is turned off, input terminals of the comparator are pulled to a same level, and the control logic performs calibration of the comparator according to a comparison result generated by the comparator. In a conversion phase, the offset calibration control switch is turned on, and the control logic output an analog-to-digital conversion result of the input signal according to the comparison result.

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.

A method of using an oscillator circuit is disclosed. The method includes: with an oscillator, generating a plurality of output clock signals based on an override control signal; with a phase detector circuit, generating a phase error signal based on the output clock signals; with a gain stage circuit, modifying a feedback control signal based on the phase error signal and an offset compensation code; with a controller, modifying the offset compensation code; with a comparator, generating an equality signal indicating that the feedback control signal is equal to the override control signal; and with the controller, in response to the equality signal, causing the modified offset compensation code to be stored.

An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.