58 results about "Offset calibration" patented technology

In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

This invention discloses a dynamic comparator for a successive approximation analog-to-digital converter (ADC), relating to the field of comparator technology. The dynamic comparator includes: a cascaded pre-amplifier circuit and a latch circuit; the pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; the differential input pair is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair; the first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair; the positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit. This invention addresses the problems of large footprint and difficult offset calibration in existing successive approximation ADCs.

The invention discloses a voltage buffer, a voltage buffering method, a display driving chip and electronic equipment, and belongs to the technical field of display. The voltage buffer comprises a voltage buffer module and an offset calibration module. The voltage buffer module comprises a first output stage and a second output stage. The voltage buffer module is used for outputting a first output voltage to a load through the first output stage in a non-calibration mode; or in the calibration mode, a second output voltage is output to the imbalance calibration module through the second output stage; and the offset calibration module is used for performing current compensation on the voltage buffer module based on the second output voltage under the condition that the second output voltage is received so as to calibrate the direct current offset of the voltage buffer module. Therefore, the direct current offset of the voltage buffer module is calibrated in a current compensation mode, and due to the fact that the establishment time of the second output voltage in the calibration mode is short, the offset calibration speed is increased.

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

The invention relates to a radio frequency power detector with offset and temperature compensation. Wireless circuitry may include a transmit line carrying a signal and a power detector measuring the signal. The detector may include a rectifier coupled to the comparator through a differential path. An offset calibration digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may generate an offset compensation voltage by superimposing different offset voltages over time to a voltage on the second line. The reference generator may generate a set of threshold voltages by superimposing different reference voltages to the offset compensation voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to the negative input of the comparator.

The invention discloses a common-mode compensation and offset calibration circuit, a chip and equipment, and belongs to the technical field of integrated circuits. The circuit comprises a common mode compensation circuit used for injecting a constant first common mode compensation current to an output node ON of a differential amplifier and injecting a constant second common mode compensation current to an output node OP of the differential amplifier; the equalizer tap is used for adjusting tap current according to a control word TAP, the tap current is respectively connected with two nodes ON and OP through two switch tubes, and the two switch tubes are controlled by feedback signals Dn and Dp output by a decision device; an offset calibration circuit comprising a first current branch connected to the node ON and a second current branch connected to the node OP; wherein the current on the two current branches is regulated and controlled according to the tap current, so that the sum of the tap current and the current on the offset calibration circuit is equal to the current injected by the common mode compensation circuit. According to the invention, the magnitude of the common-mode compensation current does not change along with the change of the tap current of the equalizer.

The application provides a low-cost design scheme suitable for common-mode recovery of an XGS-PON OLT BM-LA. A DCOC module calibration circuit is composed of a low-pass filter, an amplifier, a comparator, a digital controller and a current differential DAC. The low-pass filter and the amplifier respectively extract and scale the DC offset; the comparator distinguishes the polarity of the DC offset; the digital controller increases or decreases the output value of the current differential DAC according to the comparison result of the CMP until the DC offset calibration is completed.

The present invention discloses a computer-implemented method for offset calibration and an integrated circuit (IC) memory controller for offset calibration. Said method comprises the step of: performing offset calibration of a receiver read-data strobe replica; conditioning pad voltages of a receiver read-data strobe and the receiver read-data strobe replica based on an offset calibration value of the receiver read-data strobe replica; and performing offset calibration of the receiver read-data strobe based on an offset calibration value of the pad voltages; wherein disabling differential inputs of transmission gate from a differential strobe signal pins to the receiver read-data strobe replica during receiver read-data strobe replica offset calibration.

The present disclosure relates to a semiconductor device performing offset calibration. A semiconductor device includes a calibration control circuit, a first data input / output block, and a second data input / output block. The calibration control circuit generates a master clock signal and a calibration control signal for an offset calibration operation. The first data input / output block adjusts an offset of the first data input / output block based on the master clock signal, the calibration control signal, and a reference voltage. The second data input / output block adjusts an offset of the second data input / output block based on the master clock signal, the calibration control signal, and the reference voltage.

This invention relates to the field of robot navigation technology, specifically to a dynamic zero-bias calibration method for robot navigation based on multi-sensor fusion. The technical solution includes: acquiring IMU measurements and velocity data; determining whether the current operating state is stationary based on the IMU measurements; if so, entering a static calibration mode, continuously acquiring IMU data in the stationary state and processing it to obtain an initial zero bias; if not, calculating the fusion residual value between the current IMU measurement and the multi-sensor fusion estimate; validating the acquired key constraint information by determining whether it exceeds the corresponding threshold range; if not, no correction is performed; if so, progressive zero-bias correction is applied to the IMU measurements to obtain corrected measured values, and subsequent IMU measurements are then used for zero-bias compensation correction. This invention uses a two-level calibration architecture of static calibration and online estimation, combined with a multi-sensor fusion algorithm and a progressive correction strategy with a minimal learning rate, to achieve accurate, real-time, and stable calibration of IMU zero bias.

This invention relates to the field of metrology calibration, and more particularly to an adaptive calibration method, apparatus, device, and storage medium for a metrology box. The method includes the following steps: powering on the metrology box normally, performing self-operating noise detection, and constructing a self-operating noise feature set; performing initial calibration and real-time metrological detection on the metrology box based on the self-operating noise feature set, outputting multiple metrological data sequences; performing sequence-by-sequence feature analysis and differential calculation of adjacent time periods based on the multiple metrological data sequences to obtain a feature difference value sequence; synchronously acquiring environmental monitoring parameters of the metrology box; tracing environmental interference sources based on the environmental monitoring parameters and marking interference sources; performing offset calibration based on the interference sources to obtain offset calibration reference parameters; and performing real-time operating condition metrological detection based on the offset calibration reference parameters. This invention achieves accurate and efficient metrology box detection and calibration.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

An analog-to-digital converter (ADC) and a method for calibrating a comparator within the ADC are provided. The ADC includes a sampling capacitor array, the comparator, an offset calibration control switch and a control logic, where the offset calibration control switch is coupled between the sampling capacitor array and the comparator. In a sampling phase, the sampling capacitor array samples an input signal, the offset calibration control switch is turned off, input terminals of the comparator are pulled to a same level, and the control logic performs calibration of the comparator according to a comparison result generated by the comparator. In a conversion phase, the offset calibration control switch is turned on, and the control logic output an analog-to-digital conversion result of the input signal according to the comparison result.

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.

A comparison circuit includes a comparator and a multiplexer. The comparator includes at least one transistor and generates a first output signal based on a first input signal, a second input signal, and an operating clock signal. The multiplexer, in a normal mode, outputs a first clock signal as the operating clock signal based on a control signal, and in an offset calibration mode, outputs a second clock signal different from the first clock signal as the operating clock signal based on the control signal. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degrading the at least one transistor based on the first and second input signals having the same voltage level and the operating clock signal.

This invention discloses an intelligent MOSFET device with overcurrent protection, relating to the field of semiconductor power device technology. The device includes a main chip with a main MOSFET, a sampling MOSFET, and a drifting thin-film resistor fixed on it. The sampling MOSFET has a differential offset calibration area and an overcurrent detection and protection drive area on its left side, with a high-precision reference area between them. A self-recovery block is located on the right side of the overcurrent detection and protection drive area. The main MOSFET integrates a channel region and other structures internally. The sampling MOSFET is connected in parallel with the main MOSFET. The drifting thin-film resistor connects to the sampling circuit. The differential offset calibration area performs signal calibration and amplification. The high-precision reference area provides a stable reference voltage. During overcurrent, the drive signal is quickly cut off. After the fault is cleared, the self-recovery block automatically resets. This device has a compact structure, high detection accuracy, and requires no manual intervention, making it suitable for scenarios with high safety requirements, such as lithium battery protection boards and motor drive circuits.

The invention provides an offset calibration method and system for a multi-comparator structure SAR ADC, and the method comprises the steps: sequentially carrying out the following calibration steps on each comparator according to a sequence from the highest comparator to the lowest comparator: obtaining the statistical information of a digital code outputted by the current comparator in the quantization process of the multi-comparator structure SAR ADC; judging the polarity of the offset voltage corresponding to the current comparator according to the statistical information of the digital code output by the current comparator; and adjusting the offset voltage of the current comparator according to the polarity of the offset voltage corresponding to the current comparator. According to the method, the defects that the quantization time is occupied and the conversion speed is limited in a traditional method are overcome, meanwhile, calibration is conducted in sequence from the highest comparator to the lowest comparator, it is ensured that high-order imbalance is corrected preferentially, interference of the high-order imbalance to low-order calibration is prevented, and therefore the accuracy of overall calibration of the SAR ADC of the multi-comparator structure is improved.

Provided are an optical power measurement method, an offset calibration method, and an optical power meter suitable for applying the offset calibration method. The optical power measurement method, the offset calibration method, and the optical power meter are characterized by two temperature sensors for more accurately predicting optical power offset. The first temperature sensor is positioned to read the temperature of a photodiode, and the second temperature sensor is positioned to read the temperature of a PCB ground plane.

A system comprising an actuator configured to couple to a closing link and to a frame of an agricultural row unit, a monitoring system comprising a sensor, and a controller comprising a memory and a processor. The closing link is configured to pivotally couple to the frame and the actuator is configured to drive the closing link to rotate relative to the frame to control a closing depth of a closing disc rotatably coupled to the closing link. The sensor is configured to output a sensor signal indicative of an extension length of the actuator. The controller is communicatively coupled to the sensor, and the controller is configured to determine the extension length of the actuator based on the sensor signal.

This application discloses a digital-to-analog converter (DAC), an offset calibration method, and an electronic device. The DAC includes an operational amplifier, a control unit, an offset calibration unit, and a resistor network. The operational amplifier includes a non-inverting input terminal, an inverting input terminal, a control terminal, and an output terminal. The control unit outputs a first control signal to control the operational amplifier to enter comparator mode and performs offset calibration on the operational amplifier based on the signal output from the output terminal. The offset calibration unit generates a reference voltage when the operational amplifier is in comparator mode. The resistor network outputs an inverting input voltage when the operational amplifier is in comparator mode. The technical solution of this application generates a reference voltage by adding an offset calibration unit and processes the offset voltage of the operational amplifier based on the reference voltage, thereby achieving rapid calibration of the circuit in a specific operating mode.

The invention belongs to the field of integrated circuits, and particularly relates to a high-speed dynamic comparator for offset calibration and a high-precision ADC. The circuit comprises a comparator, an accelerating tube, an executing tube and an offset calibration module. Wherein the comparator adopts a double wake tube comparator. The accelerating tube is used for forming a complementary CMOS input tube pair with the input tube of the comparator. The execution tube is used as an input port of offset correction voltage in the in-phase side and the anti-phase side of the comparator. The offset calibration module comprises an in-phase correction voltage generation circuit and an inverted correction voltage generation circuit. The comparator and the comparator are respectively used for calibrating an enable signal and a reset signal according to the outputs of the in-phase output end and the inverted output end of the comparator and a group of inverted calibration signals; generating a voltage signal which is input into an execution tube and is used for compensating the offset voltage in the comparator; and the imbalance calibration module generates required correction voltage in a self-adaptive manner by using a charge pump and a discharge pump which alternately work. The problem that the reset rate and the offset calibration effect of an existing high-speed comparator are difficult to consider at the same time is solved.

A method and a system for improving measurement accuracy of a meter previously calibrated are provided. A region over a measurement range of the meter is defined based at least in part on a plurality of calibration points utilized to previously calibrate the meter, where the region includes a first calibration constant and a second calibration constant. A quantity output of the meter is recalibrated by: selecting one or more recalibration points within the region; measuring one or more corresponding error factors at the one or more recalibration points; and determining a revised second calibration constant based on the one or more corresponding error factors and the second calibration constant. The recalibrated quantity output of the meter is then generated based on a measured quantity output by the meter, the first calibration constant, and the revised second calibration constant.

A comparison circuit performing comparator offset calibration and a method of operating the comparison circuit are provided. The comparison circuit comprises a comparator and a multiplexer. The comparator includes at least one transistor, and generates a first output signal based on a first input signal, a second input signal, and an operation clock signal. The multiplexer outputs a first clock signal as an operation clock signal based on the control signal in a normal mode, and outputs a second clock signal different from the first clock signal as the operation clock signal based on the control signal in an offset calibration mode. In the offset calibration mode, the comparison circuit is configured to perform an offset calibration operation by degenerating at least one transistor based on first and second input signals having the same voltage level and an operation clock signal.

The invention relates to a high-precision current sampling integrated circuit offset calibration method and system, and relates to the technical field of current detection, and the method comprises the steps: obtaining a reference sampling resistance, a real-time voltage and an effective sampling voltage range; calculating a real-time current based on the reference sampling resistor and the real-time voltage; when the real-time current is larger than a preset heating current threshold value, the minimum sampling resistance is calculated based on the effective sampling voltage range and the real-time current; the adjustable sampling resistor is controlled to be adjusted to the minimum sampling resistor for sampling, and the minimum sampling voltage is measured; calculating a sampling current based on the minimum sampling voltage and the minimum sampling resistance; when the real-time current is smaller than a preset sampling current threshold value, the maximum sampling resistance is calculated based on the real-time current and the effective sampling voltage range; the adjustable sampling resistor is controlled to be adjusted to the maximum sampling resistor for sampling, and the maximum sampling voltage is measured; a sampling current is calculated based on the maximum sampling voltage and the maximum sampling resistance. The invention has the effect of reducing the drifting of the resistance value of the resistor.

A parallel e-fuse device including: a first e-fuse to receive an input voltage and transfer a first fuse current to an output terminal; and a second e-fuse to receive the input voltage and transfer a second fuse current to the output terminal, the first e-fuse includes: a power transistor to control the first fuse current according to a gate voltage; a clamp amplifier to provide a charging current to charge a gate of the power transistor, the charging current being obtained by monitoring a feedback voltage; a balance amplifier to provide a first sinking current to discharge the gate of the power transistor, the first sinking current being obtained by comparing a current sensing signal with a current monitoring signal, wherein the clamp amplifier generates the charging current according to a differential voltage between the feedback voltage and a reference voltage.

The application relates to the technical field of integrated circuits and provides a training device and a training method for high-speed differential signal offset. The device comprises an offset calibration module configured to provide offset compensation for two-phase signals of a differential signal at an adjustment precision, wherein the offset compensation is configured to reduce offset between the two-phase signals; and a delay training module configured to train the offset calibration module so that the adjustment precision provided by the offset calibration module is adapted to an operating frequency, a data transmission rate and a bandwidth, wherein the differential signal is a data strobe signal, and the operating frequency, the data transmission rate and the bandwidth are all associated with the data strobe signal. In this way, the high-speed differential signal offset is compensated, the available eye diagram size is increased, the margin from the edge of the eye diagram is increased, and thus the drift caused by voltage temperature and the like can be better resisted.

The disclosure herein relates to systems and methods for offset calibration in a successive approximation analog-to-digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of a plurality of bits corresponding to an input voltage, and to accumulate or average at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, to provide a second offset signal to control a second offset associated with a second comparator, or to reduce an offset difference associated with the first offset and the second offset.