Offset calibration circuit for comparer in asynchronous successive approximation register analog-to-digital converter

Abstract

The invention discloses an offset calibration circuit for a comparer in an asynchronous successive approximation register analog-to-digital converter. The offset calibration circuit comprises a calibration clock generation module, a basic dynamic comparer with calibration pair transistors, a calibration signal generation circuit, a calibration control circuit and a comparer clock selection circuit. The calibration clock generation module is used for generating a global clock control signal for controlling offset calibration of the dynamic comparer. The basic dynamic comparer with calibration pair transistors comprises a basic single-level dynamic comparer, the calibration pair transistors connected with input pair transistors in parallel, a first switch S1 and second switch S2. The calibration signal generation circuit is used for generating a gate control voltage Vcal for one MOS transistor in the calibration pair transistors. The calibration control circuit is used for generating a control signal for the calibration signal generation circuit. The comparer clock selection circuit is used for generating a comparison and reset clock CK of the dynamic comparer. The offset calibration circuit is applied to offset calibration of the comparer of the asynchronous SAR ADC in a SoC system and is convenient and efficient.

Description

technical field [0001] The invention relates to the field of analog-digital hybrid integrated circuits, in particular to an offset calibration circuit of a comparator in an asynchronous successive approximation analog-to-digital converter. Background technique [0002] The asynchronous successive approximation analog-to-digital converter (SAR ADC) is integrated into the SoC system due to its low power consumption, high digitization, and no need for multiple frequency clocks, so as to enhance the ability of the SoC system to perceive external signals. Dynamic comparators are widely used in SAR ADCs due to their advantages of high speed and low power consumption. However, the offset voltage caused by circuit mismatch deteriorates the accuracy of SAR ADCs. Therefore, the offset calibration of the dynamic comparator is of great significance in the field of low power consumption, high speed and high precision. [0003] The traditional offset voltage storage (self-calibration zer...

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Problems solved by technology

[0003] The traditional offset voltage storage (self-calibration zero) technology introduces a large storage capacitor on the signal path, which is not conducive to high-speed applications; the method of increasing the input calibration pair and adjusting the gate voltage difference to offset the offset voltage of the comparator is widely used Comparator offset calibration circuit in the

There are mainly charge pump type, charge average type, and resistance type DAC to generate the grid voltage of the calibration pair. After each comparison of the comparator, the grid voltage is updated. Noise affects it greatly, making the calibration highly unlikely to be monotonic

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