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Energy harvesting computer device in association with a communication device configured with apparatus for boosting signal reception

ActiveUS20130157729A1Improve consumer electronics hybrid consumer electronics performanceLow densityMaterial nanotechnologyEnergy efficient ICTCellular telephoneCommunication device
Disclosed embodiments comprise an energy harvesting computer device in association with a communication device comprising interactive user interface operatively configured with CMOS multiple antennas on chip for boosting signal receptions and for providing faster data transmission speed. Disclosed embodiment encompasses three modes of communications—the Cell phone, wireless Internet applications, and Global communication and media information. Embodiments provide communication apparatus operable to enhance mobile communication efficiency with touch sensitive display comprising energy harvesting platform in communication with a charging circuit board configured with memories, processors, sensors, and modules. Embodiments further provide a gaming device, a wireless media device configured with touch pads comprising sensors being embedded in silicon substrate and fused in nano-fiber/microfiber material having excellent electrical characteristics. Certain embodiments provide communication apparatus configured for voice enabled applications comprising human voice auditory operable to convert text into voice auditory and/or voice auditory into text applications.
Owner:TABE JOSEPH AKWO

Selective lossless, lossy, or no compression of data based on address range, data type, and/or requesting agent

An integrated memory controller (IMC) including MemoryF/X Technology which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably selectively uses a combination of lossless, lossy, and no compression modes. Data transfers to and from the integrated memory controller of the present invention can thus be in a plurality of formats, these being compressed or normal (non-compressed), compressed lossy or lossless, or compressed with a combination of lossy and lossless. The invention also indicates preferred methods for specific compression and decompression of particular data formats such as digital video, 3D textures and image data using a combination of novel lossy and lossless compression algorithms in block or span addressable formats. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high speed parallel decompression operation. The IMC also preferably uses a special memory allocation and directory technique for reduction of table size and low latency operation. The integrated data compression and decompression capabilities of the IMC remove system bottle-necks and increase performance. This allows lower cost systems due to smaller data storage, reduced bandwidth requirements, reduced power and noise.
Owner:INTELLECTUAL VENTURES I LLC

Method of fabricating a fast programmable flash E2PROM cell

InactiveUS6034896ALarge capacitySuitable for battery operated portable equipmentTransistorRead-only memoriesElectric fieldHot electron
PCT No. PCT/CA96/00446 Sec. 371 Date Jun. 24, 1998 Sec. 102(e) Date Jun. 24, 1998 PCT Filed Jul. 3, 1996 PCT Pub. No. WO97/02605 PCT Pub. Date Jan. 23, 1997A flash E2PROM cell having source and drain regions disposed in a substrate, a channel region intermediate to the source and drain regions, a tunnel dielectric layer overlying the channel region, a floating gate overlying the tunnel dielectric layer, an inter-poly dielectric layer overlying the floating gate, and a control gate overlying the inter-poly dielectric layer. The flash E2PROM cell further having a highly doped p+ pocket implant covering a portion of the cell width and adjacent to at least one of the drain and source regions. The flash E2PROM cell is comprised of two sections butted together. The portion (width-wise) that is covered by the highly doped p+ pocket implant is referred to as a program section. The remaining portion (width-wise) not covered by the highly doped p+ pocket implant resembles a conventional flash E2PROM cell and is referred to as a sense section. The highly doped p+ pocket implant and the n+ drain and/or source regions create a junction having narrow depletion width so that when the junction is reversed biased, an electric field is created for generating hot electrons for storage on the floating gate, thereby programming the flash E2PROM cell when a high positive potential is applied to the control gate.
Owner:UNIV OF TORONTO INNOVATIONS FOUND THE
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