An apparatus for receiving an
asynchronous data signal may include a
clock generator that generates a
clock signal having a frequency approximately equal to the
bit rate of the
asynchronous data signal. An
edge detector may detect transitions of the
asynchronous data signal. A dead-band
detector may detect when a transition of the
clock signal used to sample the
data signal occurs within a predetermined amount of time of a transition of the asynchronous
data signal so that data sampled on that transition of the
clock signal may be invalid. The phase of the
clock signal may be adjusted if the transition of the
clock signal occurs within this predetermined amount of time. The
clock generator may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the
bit rate of the asynchronous
data signal, and the other programmed with a phase-
delay value so that it generates a sample clock signal at a phase
delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first
shift register configured to shift a data word in serially and output the data word in parallel and a second
shift register configured to track when the data word had been completely shifted into the first
shift register.