The invention provides an anti-surge-
voltage planar gate
silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing
metal on the lower side surface of a
silicon carbide substrate, and forming a drain
metal layer; epitaxially growing on the upper side surface of the
silicon carbide substrate to form a drift layer; forming a
barrier layer on the drift layer, and performing
etching and
ion implantation to form a protection region, a
current sharing region, a second P-type well region, a Schottky region, a first P-type well region and a lug boss; a
barrier layer is formed again,
etching and
ion implantation are carried out, and an N-type source region is formed; forming a
barrier layer again,
etching and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing
metal, and forming a gate metal layer; the method comprises the following steps: preparing a source
electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source
electrode metal layer, removing the barrier layer, and completing preparation. The reliability of the device is improved, the
conduction loss of the device is reduced, and the
surge voltage resistance is improved.