Surge protection circuit

Abstract

The invention discloses a surge protection circuit, which belongs to the field of semiconductor surge protection devices, and comprises a plurality of resistors, a plurality of voltage stabilizing diodes and a plurality of transistors, the first end of the first resistor is connected with a bus voltage, the first end of the first transistor and the second end of the second transistor; the second end of the first resistor is connected with the third end of the first transistor and the cathode of the first Zener diode, and the anode of the first Zener diode is connected with the cathode of the second Zener diode and the third end of the third transistor. The anode of the second voltage stabilizing diode is connected with the second end of the third resistor, the second end of the third transistor, the first end of the second transistor and the ground, the second end of the first transistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the first end of the third resistor, the first end of the third transistor and the third end of the second transistor. According to the invention, the problems of surge voltage such as electrostatic discharge, electrical fast transient pulse train, lightning stroke, peak and the like, transient voltage generated in a hot plug process and the like can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor surge protection devices, and in particular to a surge protection circuit. Background Art

[0002] In the power supply system of airborne electronic equipment, the airborne power port is a key interface for energy transmission. Its working stability directly affects the reliable operation of the subsequent circuits and the entire equipment. In actual applications, this port usually has the following typical working conditions: First, under normal working conditions, the port busbar bears the typical input voltage; Second, because airborne power ports are usually exposed to the external environment to achieve connection functions, they are susceptible to various transient interferences, including but not limited to electrostatic discharge (ESD), electrical fast transient pulse groups (EFT), lightning induction, and surge voltages such as spike voltages generated within the power system; Third, during the assembly and maintenance of airborne power systems, the front-end power supply and the back-end circuits are often electrically connected through connectors. Inserting and removing connectors puts the ports into a hot-swappable state. Under this condition, the bus voltage will experience a rapid rise, and the sudden voltage change may cause abnormal circuit response. Taking a typical 28V airborne power system as an example, its bus voltage typically reaches a maximum of 36V. Therefore, the voltage withstand capability of downstream components only needs to be above 36V with a certain safety margin. However, the amplitudes of surge voltages such as electrostatic discharge, electrical fast transients (EFTS), lightning strikes, spikes, and transient voltages generated during hot-plugging often far exceed 36V. Without protective measures, these can easily cause overvoltage damage to downstream circuits. Therefore, appropriate protection circuitry must be added at the ports. Summary of the Invention The present invention aims to provide a surge protection circuit.

[0003] To achieve the above object, the technical solution of the present invention is: A surge protection circuit includes multiple resistors, multiple voltage-stabilizing diodes, and multiple transistors, wherein the first end of a first resistor is connected to a bus voltage, the first end of a first transistor, and the second end of a second transistor, the second end of the first resistor is connected to the third end of the first transistor and the cathode of the first voltage-stabilizing diode, the anode of the first voltage-stabilizing diode is connected to the cathode of the second voltage-stabilizing diode and the third end of the third transistor, the anode of the second voltage-stabilizing diode is connected to the second end of a third resistor, the second end of the third transistor, the first end of the second transistor, and ground, the second end of the first transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the first end of the third resistor, the first end of the third transistor, and the third end of the second transistor.

[0004] In a specific embodiment, the working characteristics of the third transistor are: when V GS_Q3 <V GS(th)_Q3 When V GS_Q3 ≥V GS(th)_Q3 When the third transistor is turned off, V GS(th)_Q3 >0, V GS_Q3 is the gate-source voltage of the third transistor, V GS(th)_Q3 is the gate-source threshold voltage of the third transistor.

[0005] Furthermore, the first transistor and the second transistor are MOSFETs.

[0006] Furthermore, the first transistor is a P-type MOSFET, and the second transistor is an N-type MOSFET.

[0007] Furthermore, the third transistor is a JFET.

[0008] Furthermore, the third transistor is a P-type JFET.

[0009] Further, when the bus voltage is lower than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned off, the first transistor is turned off, the second transistor is turned off, and the third transistor is turned on.

[0010] Further, when the bus voltage is higher than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned on, the first transistor is turned on, the second transistor is turned on, and the third transistor is turned off.

[0011] Further, when the bus voltage has a fast rising edge, the first zener diode and the second zener diode are turned off, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned on.

[0012] Furthermore, the first end of each transistor is its source, the second end of each transistor is its drain, and the third end of each transistor is its gate.

[0013] Beneficial effects: When the bus voltage is lower than the sum of the breakdown voltages of the first and second zener diodes, the surge protection circuit of the present invention does not operate. In this operating mode, the third transistor remains normally on. When the bus voltage rises and exceeds the sum of the breakdown voltages of the first and second zener diodes, the third transistor changes from a normally on state to a cut-off state without affecting the normal operation of the surge protection circuit. At this time, the second transistor turns on, discharging the bus current and playing a role in surge protection. When the bus voltage has a fast rising edge, the third transistor is in a normally on state, which can effectively prevent the second transistor from being mistakenly turned on at a lower bus voltage and prevent the second transistor from being damaged by overpower. The present invention can significantly solve problems such as surge voltages such as electrostatic discharge, electrical fast transient pulse groups, lightning strikes, spikes, and transient voltages generated during hot plugging.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure is a circuit diagram of a surge protection circuit of the present invention.

[0016] Figure 2 A schematic diagram of a current path of a surge protection circuit according to the present invention.

[0017] Figure 3 The figure is a schematic diagram of a simulation circuit of a surge protection circuit of the present invention.

[0018] Figure 4 The figure is a comparison diagram of the simulation waveforms of a traditional surge protection circuit and a surge protection circuit of the present invention. DETAILED DESCRIPTION

[0019] To make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Figure 1 FIG. 1 is a schematic diagram of a surge protection circuit according to the present invention. Figure 1 As shown, a surge protection circuit includes multiple resistors, multiple voltage-stabilizing diodes and multiple transistors. The first end of the resistor R1 is connected to the bus voltage V BUS, the first end of the transistor Q1 and the second end of the transistor Q2, the second end of the resistor R1 is connected to the third end of the transistor Q1 and the cathode of the Zener diode D1, the anode of the Zener diode D1 is connected to the cathode of the Zener diode D2 and the third end of the transistor Q3, the anode of the Zener diode D2 is connected to the second end of the resistor R3, the second end of the transistor Q3, the first end of the transistor Q2 and ground, the second end of the transistor Q1 is connected to the first end of the resistor R2, the second end of the resistor R2 is connected to the first end of the resistor R3, the first end of the transistor Q3 and the third end of the transistor Q2.

[0021] Optionally, the transistor Q1 and the transistor Q2 are MOSFETs, the transistor Q3 is a JFET, the first end of each transistor is its source, the second end of each transistor is its drain, and the third end of each transistor is its gate.

[0022] More specifically, the transistor Q1 is a P-type MOSFET, the transistor Q2 is an N-type MOSFET, and the transistor Q3 is a P-type JFET.

[0023] More specifically, the operating characteristics of transistor Q3 are: when V GS_Q3 <V GS(th)_Q3 When V GS_Q3 ≥V GS(th)_Q3 When transistor Q3 is turned off, V GS(th)_Q3 >0, V GS_Q3 is the gate-source voltage of transistor Q3, V GS(th)_Q3 is the gate-source threshold voltage of transistor Q3.

[0024] Figure 2 This is a schematic diagram of the current path of a surge protection circuit of the present invention. Figure 2 The working process of a surge protection circuit of the present invention when in use is described in three working modes.

[0025] When the bus voltage V BUS When the voltage is lower than the sum of the breakdown voltages of the Zener diodes D1 and D2, the Zener diodes D1 and D2 are cut off, and no current flows through the path. The gate-source voltage V GS_Q1 =0, transistor Q1 is turned off, and the gate-source voltage V GS_Q2 There is no charging current, transistor Q2 is cut off, and the surge protection circuit of the present invention does not work. In this working mode, transistor Q3 remains normally open.

[0026] When the bus voltage V BUS The voltage is higher than the sum of the breakdown voltages of the Zener diodes D1 and D2, that is, V BUS >V BR_D1 +V BR_D2 When VGS_Q3 = V BR_D2 , where V BR_D1 is the breakdown voltage of diode D1, V BR_D2 is the breakdown voltage of diode D2. Select reasonable parameters of Zener diode D2 and set V BR_D2 >V GS(th)_Q3 , so the transistor Q3 changes from the normally open state to the cut-off state. Figure 2 As shown, since the current follows the first path by the bus voltage V BUS , the gate-source capacitance C of transistor Q1 GS_Q1 , Zener diode D1, Zener diode D2 flows through, the gate-source voltage of transistor Q1 V GS_Q1 Greater than the gate-source threshold voltage V of transistor Q1 GS(th)_Q1 , transistor Q1 is turned on, and the current flows along the second path from the bus voltage V BUS , transistor Q1, resistor R2, gate-source capacitance C of transistor Q2 GS_Q2 Flows through, the gate-source voltage of transistor Q2 V GS_Q2 Greater than the gate-source threshold voltage V of transistor Q2 GS(th)_Q2 , transistor Q2 is turned on, discharging bus current and playing a role in surge protection. It can be seen that under this working condition, transistor Q3 will not affect the normal operation of the surge protection circuit.

[0027] When the bus voltage V BUS When there is a fast rising edge, the current flows along the third path from the bus voltage V BUS , the drain-source junction capacitance C of transistor Q1 DS-Q1 , resistor R2, transistor Q3 flows through, the drain-source junction capacitance C of transistor Q1 DS-Q1 Because of the fast rising edge, the coupling current is generated. BUS Low, the Zener diodes D1 and D2 are both in the cut-off state, and the gate-source voltage V GS_Q3 is less than the gate-source threshold voltage V of transistor Q3 GS(th)_Q3 , transistor Q3 is in the normally open state, discharging the coupled current, and the gate-source voltage V GS_Q2 Always lower than the gate-source threshold voltage V of transistor Q2 GS(th)_Q2 , transistor Q2 remains off. Without transistor Q3, transistor Q2 would mistakenly turn on at a lower bus voltage. Because the bus voltage's source internal resistance is generally low, premature turn-on would cause the bus voltage to release excessive energy into the surge protection circuit, leading to overpower damage to transistor Q2 in the circuit.

[0028] Figure 3 FIG. 1 is a schematic diagram of a simulation circuit of a surge protection circuit of the present invention. Figure 3As shown, the first end of the resistor R1 is the terminal voltage V of the surge protection circuit z , the second end of resistor R2 is the driving voltage V gs I ds is the discharge current. BUS The terminal voltage of the surge protection circuit V z When directly connected, the terminal voltage of the surge protection circuit is V z Always equal to the bus voltage V BUS , it is impossible to display the real terminal voltage of the surge protection circuit, so the bus voltage V BUS Add the internal resistance R of the power supply between the surge protection circuit and the i , set to a fixed value of 2ohm in the simulation.

[0029] Use LTSPICE software for simulation verification. Figure 4 This is a comparison diagram of the simulated waveforms of a traditional surge protection circuit and a surge protection circuit of the present invention. BUS is the bus voltage, V z_before To improve the terminal voltage of the traditional surge protection circuit, I ds_ before To improve the discharge current of transistor Q2 in the traditional surge protection circuit, V gs_ before To improve the driving voltage of transistor Q2 in the conventional surge protection circuit; V z_after The terminal voltage of a surge protection circuit of the present invention is improved, I ds_ after To improve the transistor Q3 discharge current of a surge protection circuit of the present invention, V gs_ after The driving voltage of transistor Q3 of a surge protection circuit of the present invention is improved, wherein V BUS The rise rate is set to 28V / 30ns. It can be seen that before the improvement measures are taken, the surge protection circuit is opened prematurely, and V z_before Lower than V for a long time BUS , for a long time, I ds_ before is not 0, the surge protection circuit is exposed to power for a long time due to the mistaken opening. After taking improvement measures, the mistaken opening phenomenon is significantly improved, V z_after Rise rate and V BUS Almost identical, I ds_ after The duration and peak value of V gs From the waveform, V gs_ after Compared with V gs_ before The circuit has a slower rising edge and amplitude, so the transistor Q3 is turned on at a lower level. The simulation results show that this method can effectively suppress the problem of false turn-on caused by hot plugging in the surge protection circuit.

[0030] In summary, when the bus voltage V BUSWhen the voltage is lower than the sum of the breakdown voltages of the Zener diodes D1 and D2, the surge protection circuit of the present invention does not work. In this working mode, the transistor Q3 remains normally open. When the bus voltage V BUS When the voltage of the bus voltage V BUS When a fast rising edge occurs, transistor Q3 is in a normally-on state, effectively preventing transistor Q2 from erroneously turning on at low bus voltages and overpower damage. This invention significantly addresses surge voltages such as electrostatic discharge, electrical fast transients (EFTS), lightning strikes, spikes, and transient voltages generated during hot-swap operations.

[0031] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent applications.

Claims

1. A surge protection circuit, characterized in that: The invention comprises a plurality of resistors, a plurality of voltage-stabilizing diodes and a plurality of transistors, wherein the first end of the first resistor is connected to the bus voltage, the first end of the first transistor and the second end of the second transistor, the second end of the first resistor is connected to the third end of the first transistor and the cathode of the first voltage-stabilizing diode, the anode of the first voltage-stabilizing diode is connected to the cathode of the second voltage-stabilizing diode and the third end of the third transistor, the anode of the second voltage-stabilizing diode is connected to the second end of the third resistor, the second end of the third transistor, the first end of the second transistor and ground, the second end of the first transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the first end of the third resistor, the first end of the third transistor and the third end of the second transistor.

2. A surge protection circuit according to claim 1, characterized in that: The working characteristics of the third transistor are: GS_Q3 <V GS(th)_Q3 When V GS_Q3 ≥V GS(th)_Q3 When the third transistor is turned off, V GS(th)_Q3 >0, V GS_Q3 is the gate-source voltage of the third transistor, V GS(th)_Q3 is the gate-source threshold voltage of the third transistor.

3. A surge protection circuit according to claim 2, characterized in that: The first transistor and the second transistor are MOSFETs.

4. A surge protection circuit according to claim 3, characterized in that: The first transistor is a P-type MOSFET, and the second transistor is an N-type MOSFET.

5. A surge protection circuit as claimed in claim 4, characterized in that: The third transistor is a JFET.

6. A surge protection circuit according to claim 5, characterized in that: The third transistor is a P-type JFET.

7. A surge protection circuit according to claim 1, characterized in that: When the bus voltage is lower than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned off, the first transistor is turned off, the second transistor is turned off, and the third transistor is turned on.

8. A surge protection circuit according to claim 7, characterized in that: When the bus voltage is higher than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned on, the first transistor is turned on, the second transistor is turned on, and the third transistor is turned off.

9. A surge protection circuit according to claim 8, characterized in that: When the bus voltage has a fast rising edge, the first Zener diode and the second Zener diode are turned off, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned on.

10. A surge protection circuit according to claim 9, characterized in that: The first terminal of each transistor is its source, the second terminal of each transistor is its drain, and the third terminal of each transistor is its gate.

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