Closed-loop control surge suppression circuit based on NMOS (N-channel Metal Oxide Semiconductor) tube

Abstract

The invention discloses a closed-loop control surge suppression circuit based on an NMOS tube, and belongs to the technical field of power electronics, the circuit is bridged between a power supply and a load, the protection threshold of surge voltage is changed by adjusting the resistance value of a resistor, and when the surge voltage in the power supply exceeds the protection threshold, the surge suppression circuit is turned off. The output voltage is changed through closed-loop control of an NMOS tube in the voltage division suppression sub-circuit, and then the working state of the closed-loop control surge suppression circuit based on the NMOS tube is adjusted to suppress the surge voltage. The boost circuit is introduced into the power supply sub-circuit, and the output end of the boost circuit is connected with the second end of the fourth resistor and the second end of the second resistor in the feedback control sub-circuit, so that closed-loop feedback is completed by taking an NMOS tube as a core and utilizing discrete devices which are relatively low in cost and easy to obtain, and a protection threshold value of surge voltage can be accurately set by adjusting reference voltage; and the voltage higher than the protection threshold is clamped, so that the voltage on the load is not higher than the protection threshold to protect the load.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a closed-loop control surge suppression circuit based on an NMOS tube. Background Art

[0002] In industrial and other special power supply occasions, some positive high voltage pulses lasting tens of milliseconds are often superimposed on the DC power supply line, which is called voltage surge. These high voltage pulses can damage the load, so surge suppression circuits are needed for protection.

[0003] The common surge suppression circuit is a simple single or combined TVS (Transient Voltage Suppressor) diode, which has low cost and simple circuit, but the breakdown voltage consistency of this special diode is very poor, and the actual breakdown voltage is also affected by temperature and supply voltage. In use, to ensure that the TVS diode does not break down when the voltage is normal, the breakdown voltage of the TVS diode often needs to be significantly higher than the maximum supply voltage. In this way, when the surge voltage in the power supply circuit is close to the maximum supply voltage, it is difficult to find a suitable TVS diode. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a closed-loop control surge suppression circuit based on NMOS tube. The technical problem to be solved by the present invention is achieved through the following technical solutions: The present invention provides a closed-loop control surge suppression circuit based on an NMOS tube, comprising: a voltage division suppression subcircuit; the closed-loop control surge suppression circuit based on the NMOS tube is connected across a power supply and a load, and changes a surge voltage protection threshold by adjusting a resistor value, and when a surge voltage in the power supply exceeds the protection threshold, changes an output voltage by closed-loop control of the NMOS tube in the voltage division suppression subcircuit, and then adjusts a working state of the closed-loop control surge suppression circuit based on the NMOS tube to suppress the surge voltage; The NMOS-based closed-loop control surge suppression circuit further includes a feedback subcircuit, a feedback control subcircuit and a voltage divider subcircuit; the feedback control subcircuit is used to control the control voltage fed back to the voltage divider suppression subcircuit according to the third output voltage; wherein the third output voltage is generated by the feedback subcircuit based on the voltage difference between the second output voltage and the reference voltage, and the second output voltage is generated by the voltage divider subcircuit based on the first output voltage output by the voltage divider suppression subcircuit; The NMOS-based closed-loop control surge suppression circuit also includes a power supply subcircuit, and the feedback control subcircuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NPN transistor Q1, and a second NPN transistor Q2; wherein, a first end of the first resistor R1 is connected to the output end of the feedback subcircuit, and a second end is connected to the base of the first NPN transistor Q1, the emitter of the first NPN transistor Q1 is grounded, and the collector of the first NPN transistor Q1 is respectively connected to the first ends of the second resistor R2 and the third resistor R3; a second end of the second resistor R2 is connected to the boost circuit in the power supply subcircuit and the first end of the fourth resistor R4; a second end of the third resistor R3 is connected to the base of the second NPN transistor Q2, the emitter of the second NPN transistor Q2 is grounded, and the collector of the second NPN transistor Q2 serves as the output end of the feedback control subcircuit, and is connected to the feedback input end of the voltage divider suppression subcircuit and the second end of the fourth resistor R4.

[0005] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a closed-loop control surge suppression circuit based on an NMOS tube. The circuit is connected across a power supply and a load. The protection threshold of the surge voltage is changed by adjusting the resistance value of a resistor. When the surge voltage in the power supply exceeds the protection threshold, the output voltage is changed by closed-loop control of the NMOS tube in a voltage-dividing suppression subcircuit, thereby adjusting the working state of the closed-loop control surge suppression circuit based on the NMOS tube to suppress the surge voltage. Considering that the gate voltage of the NMOS tube is always higher than the source voltage when working, the present invention introduces a boost circuit in the power supply subcircuit. The output end of the boost circuit is connected to the fourth resistor in the feedback control subcircuit and the second end of the second resistor. Thus, the closed-loop feedback is completed with the NMOS tube as the core and discrete devices with low cost and easy to obtain. The protection threshold of the surge voltage can be accurately set by adjusting the reference voltage. The voltage higher than the protection threshold is clamped so that the voltage on the load is not higher than the protection threshold to protect the load. When the surge voltage in the power supply does not exist, the output characteristics of the power supply are not affected.

[0006] In addition, in the closed-loop control surge suppression circuit based on NMOS tubes, the voltage suppression subcircuit adopts NMOS tubes, which have larger power capacity than PMOS tubes and are more suitable for high-power applications.

[0007] Furthermore, in the feedback control subcircuit, the first NPN tube and the second NPN tube are connected in series in the form of common emitter, ensuring that the output voltage of the operational amplifier in the feedback subcircuit has the same change trend as the collector voltage of the second NPN tube, thereby achieving a phase-invariant structure.

[0008] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a structural schematic diagram of a closed-loop control surge suppression circuit based on an NMOS tube provided in an embodiment of the present invention; Figure 2 1 is another structural schematic diagram of a closed-loop control surge suppression circuit based on an NMOS tube provided in an embodiment of the present invention; Figure 3 is a schematic structural diagram of a power supply circuit provided by an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a reference voltage generating sub-circuit provided in an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of a feedback network in a feedback subcircuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0011] Figure 1-2 Schematic diagram of the structure of the closed-loop control surge suppression circuit based on NMOS tube provided by the embodiment of the present invention. Figure 1-2 The embodiment of the present invention provides a closed-loop control surge suppression circuit based on an NMOS tube, including: a voltage division suppression subcircuit 10; the closed-loop control surge suppression circuit based on the NMOS tube is connected across the power supply and the load, and the protection threshold of the surge voltage is changed by adjusting the resistance value of the resistor, and when the surge voltage in the power supply exceeds the protection threshold, the output voltage is changed by the closed-loop control of the NMOS tube (Negative channel Metal Oxide Semiconductor, N-channel Metal Oxide Semiconductor) in the voltage division suppression subcircuit 10, thereby adjusting the working state of the closed-loop control surge suppression circuit based on the NMOS tube to suppress the surge voltage; The closed-loop control surge suppression circuit based on NMOS tube also includes a feedback sub-circuit 20, a feedback control sub-circuit 30 and a voltage divider sub-circuit 40; the feedback control sub-circuit 30 is used to control the control voltage that is fed back to the voltage divider suppression sub-circuit 10 according to the third output voltage; wherein the third output voltage is generated by the feedback sub-circuit 20 based on the voltage difference between the second output voltage and the reference voltage, and the second output voltage is generated by the voltage divider sub-circuit 40 based on the first output voltage output by the voltage divider suppression sub-circuit 10.

[0012] It can be seen that the above-mentioned closed-loop control surge suppression circuit based on the NMOS tube adopts a closed-loop feedback method. By adjusting the voltage value of the reference voltage, the protection threshold of the surge voltage can be accurately set, and then the surge voltage higher than the protection threshold is clamped, so that the voltage on the subsequent load is not higher than the protection threshold, thereby achieving the purpose of protecting the load; at the same time, for the voltage not higher than the protection threshold, no matter what its value is, no interference is made, and the NMOS tube is in a straight-through state.

[0013] Please continue to see Figure 2 The closed-loop control surge suppression circuit based on the NMOS tube also includes a power supply subcircuit 50, and the feedback control subcircuit 30 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NPN tube Q1 and a second NPN tube Q2; wherein the first end of the first resistor R1 is connected to the output end of the feedback subcircuit 20, the second end is connected to the base of the first NPN tube Q1, the emitter of the first NPN tube Q1 is grounded, and the collector of the first NPN tube Q1 is respectively connected to the first ends of the second resistor R2 and the third resistor R3; the second end of the second resistor R2 is connected to the boost circuit in the power supply subcircuit 50 and the first end of the fourth resistor R4; the second end of the third resistor R3 is connected to the base of the second NPN tube Q2, the emitter of the second NPN tube Q2 is grounded, and the collector of the second NPN tube Q2 is used as the output end of the feedback control subcircuit 30, and is connected to the feedback input end of the voltage division suppression subcircuit 10 and the second end of the fourth resistor R4.

[0014] Optionally, the voltage division suppression subcircuit 10 is specifically used to control the magnitude of the first output voltage output to the load and the voltage division subcircuit 40 under different working states under the influence of the surge voltage in the power supply and the control voltage of the feedback control subcircuit 30 .

[0015] In the above-mentioned closed-loop control surge suppression circuit based on NMOS tube, Figure 2 As shown, the voltage division suppression sub-circuit 10 includes a fifth resistor R5, a sixth resistor R6 and an NMOS tube Q3; Among them, the source of the NMOS tube Q3 serves as the output end of the voltage divider suppression sub-circuit 10, connected to the load, the input end of the voltage divider sub-circuit 40 and the first end of the fifth resistor R5, the gate of the NMOS tube Q3 is connected to the second end of the fifth resistor R5 and the first end of the sixth resistor R6, the drain of the NMOS tube Q3 is connected to the power supply and the input end of the power supply sub-circuit 50, and the second end of the sixth resistor R6 serves as the feedback input end of the voltage divider suppression sub-circuit 10, connected to the output end of the feedback control sub-circuit 30.

[0016] It should be noted that the voltage division suppression sub-circuit 10 includes at least one NMOS transistor. If it includes multiple NMOS transistors, these NMOS transistors are connected in parallel.

[0017] Furthermore, the NMOS-based closed-loop control surge suppression circuit further includes a reference voltage generating subcircuit 60; The reference voltage generating subcircuit 60 is specifically used to generate a reference voltage under the power supply of the power supply subcircuit 50, and output it to the non-inverting terminal of the operational amplifier in the feedback subcircuit 20; The voltage divider subcircuit 40 is specifically used to control the magnitude of the second output voltage output to the inverting terminal of the operational amplifier in the feedback subcircuit 20 according to its own resistance value under the action of the first output voltage; The feedback subcircuit 20 is specifically used to control the magnitude of the third output voltage fed back to the feedback control subcircuit 30 according to the voltage difference between the second output voltage and the reference voltage; The power supply subcircuit 50 is specifically used to supply power to the feedback subcircuit 20 , the feedback control subcircuit 30 and the reference voltage generation subcircuit 60 .

[0018] Alternatively, if Figure 2 As shown, the voltage divider subcircuit 40 includes a seventh resistor R7, a first capacitor C1 and an eighth resistor R8; Among them, the first end of the seventh resistor R7 is the input end of the voltage divider sub-circuit 40, connected to the load, the output end of the voltage divider suppression sub-circuit 10 and the first end of the first capacitor C1; the second end of the seventh resistor R7 is connected to the second end of the first capacitor C1, the first end of the eighth resistor R8 and the inverting end of the feedback sub-circuit 20, and the second end of the eighth resistor R8 is grounded.

[0019] In the voltage divider subcircuit 40, the seventh resistor R7, the first capacitor C1 and the eighth resistor R8 are used to sample the first output voltage of the source of the NMOS tube Q3 and then send it to the inverting terminal of the operational amplifier. The first capacitor C1 is a feedforward capacitor that can accelerate the sampling process. The resistance values ​​of the seventh resistor R7 and the eighth resistor R8 are adjustable, and the protection threshold for suppressing the surge voltage in the power supply is adjusted by adjusting the seventh resistor R7 and the eighth resistor R8.

[0020] Figure 3 Schematic diagram of the structure of the power supply circuit provided by the embodiment of the present invention. Figure 3 As shown, the power supply circuit 50 includes an inductor L1, a second capacitor C2, a first voltage regulator D1, a ninth resistor R9, a second voltage regulator D2, a third NPN transistor Q4, a boost circuit and a linear regulator; Among them, the input end of the boost circuit is connected to the power supply, the output end is connected to the first end of the fourth resistor R4 and the second end of the second resistor R2 in the feedback control subcircuit 30, the first end of the inductor L1 is connected to the power supply, the second end of the inductor L1 is connected to the collector of the third NPN tube Q4, the first end of the ninth resistor R9, the first end of the first voltage regulator D1, the first end of the second capacitor C2 and the input end of the linear regulator; the second end of the ninth resistor R9 is connected to the base of the third NPN tube Q4 and the first end of the second voltage regulator D2; the second end of the second capacitor C2, the second end of the first voltage regulator D1 and the second end of the second voltage regulator D2 are all grounded, the emitter of the third NPN tube Q4 is used as the first power supply end, and is connected to the input end of the reference voltage generation subcircuit 60; the second end of the linear regulator is grounded, and the third end of the linear regulator is used as the second power supply end, which is connected to the power supply end of the feedback subcircuit 20; the output end of the boost circuit is used as the third power supply end to provide a bias voltage for the feedback control subcircuit 30.

[0021] In this embodiment, the first voltage regulator D1 is a TVS tube, the second voltage regulator D2 is a voltage regulator diode, and the third NPN tube Q4 is a Darlington type NPN transistor. Of course, the third NPN tube Q4 can also be replaced by an NPN transistor according to different power supply voltage ranges and surge voltage rise time requirements.

[0022] In this embodiment, the power supply voltage of the power supply is simultaneously sent to the power supply subcircuit 50 and the feedback control subcircuit 30. On the one hand, the power supply voltage of the power supply is converted into three-way stabilized power supply by the power supply subcircuit 50, and is respectively sent to the power supply end of the reference voltage generation subcircuit 60 (i.e., the first end of the tenth resistor R10) and the power supply end of the operational amplifier to supply power to both; on the other hand, the power supply voltage of the power supply is sent to the feedback control subcircuit 30 to provide bias for the feedback control subcircuit 30. Of course, the power supply voltage of other internal components of the closed-loop control surge suppression circuit based on NMOS tube provided by the present invention is also taken from the power supply voltage.

[0023] Specifically, the power supply circuit 50 can be divided into two parts: the first part is a boost circuit, which can be a BOOST boost circuit with very low output power, or can be implemented in a charge pump form; the second part is a buck regulator module, which can be implemented in a BUCK type switching power supply circuit, a linear regulator circuit, or a simple linear regulator circuit composed of an NPN transistor and a voltage regulator tube. Figure 3 The case where the electronic circuit 50 adopts a simple linear regulator is taken as an example.

[0024] Figure 4 Schematic diagram of the structure of the reference voltage generation subcircuit provided by an embodiment of the present invention. Figure 4 As shown, the reference voltage generating sub-circuit 60 includes a tenth resistor R10 and a third voltage regulator tube D3; The first end of the tenth resistor R10 is connected to the first power supply end of the power supply subcircuit 50, the second end of the tenth resistor R10 is connected to the first end of the third voltage regulator D3 and the non-inverting end of the operational amplifier in the feedback subcircuit 20, and the second end of the third voltage regulator D3 is grounded.

[0025] Optionally, the third voltage regulator D3 is a diode or a voltage regulator.

[0026] In this embodiment, the input of the reference voltage generation subcircuit 60 is the stable power supply voltage from the power supply subcircuit 50, and the output is a voltage value with a lower value. The function of the reference voltage generation subcircuit 60 is to provide a stable reference voltage in the closed-loop control process. The implementation method depends on the cost and performance requirements. For example, a voltage reference chip such as TL431 can be used to achieve higher performance, or a voltage divider network composed of two resistors can be used to achieve lower performance. Of course, the generation of the reference voltage can also be simply achieved by resistor voltage division.

[0027] The feedback subcircuit 20 further includes a feedback network; The feedback network is connected between the inverting terminal and the output terminal of the operational amplifier. The output terminal of the operational amplifier is the output terminal of the feedback subcircuit 20 . The non-inverting terminal of the operational amplifier is connected to the output terminal of the reference voltage generating subcircuit 60 .

[0028] Optionally, the operational amplifier is a high-bandwidth operational amplifier. The high-bandwidth operational amplifier uses a single-ended power supply. The bandwidth parameter determines the system response speed and dynamic performance. The higher the bandwidth, the better the performance.

[0029] Figure 5 Schematic diagram of the structure of the feedback network in the feedback subcircuit provided in the embodiment of the present invention. Figure 5 As shown, the feedback network includes an eleventh resistor R11, a third capacitor C3 and a fourth capacitor C4; Among them, the first end of the eleventh resistor R11 is connected to the output end of the feedback sub-circuit 20 and the first end of the fourth capacitor C4, the second end of the eleventh resistor R11 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are connected to the inverting end of the operational amplifier in the feedback sub-circuit 20.

[0030] The closed-loop control surge suppression circuit based on NMOS tube provided by the present invention can stabilize the voltage on the load when the power surge arrives. It should be understood that when the NMOS tube Q3 is working, its gate voltage is always higher than the source voltage, so the power supply sub-circuit 50 must have a boost circuit to divide the voltage through the fourth resistor R4 and the second NPN tube Q2 and then add it to the gate of the NMOS tube Q3 through the sixth resistor R6, while the characteristic of the PMOS when working is that the gate voltage is always lower than the source voltage, and no boost circuit is required; further from the control point of view, in the closed-loop control surge suppression circuit based on NMOS tube, the output voltage of the operational amplifier and the change trend of the collector voltage of the second NPN tube Q2 must be the same, so two triodes (i.e., the first NPN tube Q1 and the second NPN tube Q2) connected in series in a common emitter form are required to realize a phase-invariant structure, but in the closed-loop control surge suppression circuit based on PMOS tube, the output voltage of the operational amplifier and the change trend of the collector voltage of the second NPN tube Q2 are opposite, so only one triode connected in a common emitter form is needed to change the phase to 180°. In addition, compared with PMOS tubes, NMOS tubes have a larger power capacity and are more suitable for high-power applications.

[0031] The working principle of the closed-loop control surge suppression circuit based on NMOS tube provided by the present invention is further described below.

[0032] After the power supply is powered on, when the power supply voltage is within the normal range and there is no surge voltage, the NMOS tube Q3 is not turned on temporarily, so there is no voltage at the source of the NMOS tube Q3, that is, the first output voltage is 0, but the power supply voltage of the power supply sub-circuit 50 is not affected. The power supply sub-circuit 50 supplies power to the reference voltage generation sub-circuit 60 and the operational amplifier. The reference voltage generation sub-circuit 60 outputs a stable reference voltage and sends it to the non-inverting terminal of the operational amplifier. Since there is no voltage at the source of the NMOS tube Q3, the output voltage of the voltage divider sub-circuit 40 is 0, that is, the magnitude of the second output voltage is 0, resulting in the voltage at the inverting terminal of the operational amplifier being 0, and the third output voltage of the operational amplifier is close to its power supply voltage. The third output voltage turns on the first NPN tube Q1 through the first resistor R1, which also causes the second NPN tube Q2 to turn off. After the power supply voltage is divided by the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6, a sufficient voltage difference is generated across the fifth resistor R5, so that the NMOS tube Q3 is fully turned on. The power supply output is all added to the load after passing through the NMOS tube Q3. The voltage difference between the source and the drain of the NMOS tube Q3 is close to 0V. At this time, the voltage divided by the seventh resistor R7 and the eighth resistor R8 of the voltage divider subcircuit 40 is still lower than the reference voltage. Therefore, the output of the operational amplifier still maintains a high voltage, the first NPN tube Q1 remains fully turned on, the second NPN tube Q2 remains fully turned off, and a sufficient voltage difference is maintained across the fifth resistor R5. The NMOS tube Q3 remains fully turned on. In the absence of a surge voltage, the power supply voltage can be fully added to the load, and the closed-loop control surge suppression circuit based on the NMOS tube does not affect the power supply to the load.

[0033] On the other hand, when the power supply output has a surge voltage higher than the critical value of surge voltage suppression, the voltage on the source of the NMOS tube Q3 rises to the critical value, the first capacitor C1 acts as a feedforward capacitor, the voltage on the eighth resistor R8 is equal to the reference voltage and has a trend of continuing to rise, then the third output voltage of the operational amplifier drops sharply, causing the first NPN tube Q1 to exit the saturated conduction state and enter the amplification state, and the second NPN tube Q2 to exit the closed state and also enter the amplification state, and the first capacitor C1 as a feedforward capacitor accelerates this process. A voltage difference appears between the collector and emitter of the second NPN tube Q2, causing the voltage across the fifth resistor R5 to decrease, and the NMOS tube Q3 also exits the saturated conduction state, the voltage between its source and drain increases, and the voltage on the source decreases, achieving negative feedback, suppressing the voltage value rise on the load, and the surge voltage is "peak clipped", achieving the purpose of surge voltage suppression.

[0034] It can be seen from the above embodiments that the beneficial effects of the present invention are: The present invention provides a closed-loop control surge suppression circuit based on an NMOS tube. The circuit is connected across a power supply and a load. The protection threshold of the surge voltage is changed by adjusting the resistance value of a resistor. When the surge voltage in the power supply exceeds the protection threshold, the output voltage is changed by closed-loop control of the NMOS tube in a voltage-dividing suppression subcircuit, thereby adjusting the working state of the closed-loop control surge suppression circuit based on the NMOS tube to suppress the surge voltage. Considering that the gate voltage of the NMOS tube is always higher than the source voltage when working, the present invention introduces a boost circuit in the power supply subcircuit. The output end of the boost circuit is connected to the fourth resistor in the feedback control subcircuit and the second end of the second resistor. Thus, the closed-loop feedback is completed with the NMOS tube as the core and discrete devices with low cost and easy to obtain. The protection threshold of the surge voltage can be accurately set by adjusting the reference voltage. The voltage higher than the protection threshold is clamped so that the voltage on the load is not higher than the protection threshold to protect the load. When the surge voltage in the power supply does not exist, the output characteristics of the power supply are not affected.

[0035] In addition, in the closed-loop control surge suppression circuit based on NMOS tubes, the voltage suppression subcircuit adopts NMOS tubes, which have larger power capacity than PMOS tubes and are more suitable for high-power applications.

[0036] Furthermore, in the feedback control subcircuit, the first NPN tube and the second NPN tube are connected in series in the form of common emitter, ensuring that the output voltage of the operational amplifier in the feedback subcircuit has the same change trend as the collector voltage of the second NPN tube, thereby achieving a phase-invariant structure.

[0037] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0039] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the present application for which protection is sought, a person skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims.

[0040] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A closed-loop control surge suppression circuit based on NMOS tube, characterized in that: include: The voltage-dividing suppression subcircuit; the NMOS-based closed-loop control surge suppression circuit is connected across the power supply and the load, and the surge voltage protection threshold is changed by adjusting the resistance value of the resistor, and when the surge voltage in the power supply exceeds the protection threshold, the output voltage is changed by the closed-loop control of the NMOS tube in the voltage-dividing suppression subcircuit, and then the working state of the NMOS-based closed-loop control surge suppression circuit is adjusted to suppress the surge voltage; The NMOS-based closed-loop control surge suppression circuit further includes a feedback subcircuit, a feedback control subcircuit and a voltage divider subcircuit; the feedback control subcircuit is used to control the control voltage fed back to the voltage divider suppression subcircuit according to the third output voltage; wherein the third output voltage is generated by the feedback subcircuit based on the voltage difference between the second output voltage and the reference voltage, and the second output voltage is generated by the voltage divider subcircuit based on the first output voltage output by the voltage divider suppression subcircuit; The NMOS-based closed-loop control surge suppression circuit also includes a power supply subcircuit, and the feedback control subcircuit includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first NPN transistor (Q1) and a second NPN transistor (Q2); wherein the first end of the first resistor (R1) is connected to the output end of the feedback subcircuit, the second end is connected to the base of the first NPN transistor (Q1), the emitter of the first NPN transistor (Q1) is grounded, and the collector of the first NPN transistor (Q1) is respectively connected to the first ends of the second resistor (R2) and the third resistor (R3); the second end of the second resistor (R2) is connected to the boost circuit in the power supply subcircuit and the first end of the fourth resistor (R4); the second end of the third resistor (R3) is connected to the base of the second NPN transistor (Q2), the emitter of the second NPN transistor (Q2) is grounded, and the collector of the second NPN transistor (Q2) is used as the output end of the feedback control subcircuit and is connected to the feedback input end of the voltage division suppression subcircuit and the second end of the fourth resistor (R4).

2. The closed-loop control surge suppression circuit based on NMOS tube according to claim 1 is characterized in that: The voltage division suppression subcircuit is specifically used to control the magnitude of the first output voltage output to the load and the voltage division subcircuit under different working states under the influence of the surge voltage in the power supply and the control voltage of the feedback control subcircuit.

3. The closed-loop control surge suppression circuit based on NMOS tube according to claim 2 is characterized in that: The voltage division suppression subcircuit comprises a fifth resistor (R5), a sixth resistor (R6) and an NMOS tube (Q3); The source of the NMOS tube (Q3) serves as the output end of the voltage division suppression subcircuit, connected to the load, the input end of the voltage division subcircuit and the first end of the fifth resistor (R5); the gate of the NMOS tube (Q3) is connected to the second end of the fifth resistor (R5) and the first end of the sixth resistor (R6); the drain of the NMOS tube (Q3) is connected to the power supply and the input end of the power supply subcircuit; the second end of the sixth resistor (R6) serves as the feedback input end of the voltage division suppression subcircuit, connected to the output end of the feedback control subcircuit.

4. The closed-loop control surge suppression circuit based on NMOS tube according to claim 2 is characterized in that: Also included is a reference voltage generating subcircuit; The reference voltage generating subcircuit is specifically used to generate a reference voltage under power supply of the electronic circuit, and output it to the non-inverting terminal of the operational amplifier in the feedback subcircuit; The voltage divider subcircuit is specifically used to control the magnitude of the second output voltage output to the inverting terminal of the feedback subcircuit according to its own resistance value under the action of the first output voltage; The feedback subcircuit is specifically configured to control the magnitude of the third output voltage fed back to the feedback control subcircuit according to the voltage difference between the second output voltage and the reference voltage; The power supply subcircuit is specifically used to supply power to the feedback subcircuit, the feedback control subcircuit and the reference voltage generation subcircuit.

5. The closed-loop control surge suppression circuit based on NMOS tube according to claim 4, characterized in that: The voltage divider subcircuit includes a seventh resistor (R7), a first capacitor (C1) and an eighth resistor (R8); Wherein, the first end of the seventh resistor (R7) is the input end of the voltage divider subcircuit, connected to the load, the output end of the voltage divider suppression subcircuit and the first end of the first capacitor (C1); the second end of the seventh resistor (R7) is connected to the second end of the first capacitor (C1), the first end of the eighth resistor (R8) and the inverting end of the operational amplifier in the feedback subcircuit, and the second end of the eighth resistor (R8) is grounded.

6. The closed-loop control surge suppression circuit based on NMOS tube according to claim 5, characterized in that: The resistance values ​​of the seventh resistor (R7) and the eighth resistor (R8) are adjustable, and the protection threshold for suppressing surge voltage in the power supply is adjusted by adjusting the seventh resistor (R7) and the eighth resistor (R8).

7. The closed-loop control surge suppression circuit based on NMOS tube according to claim 5, characterized in that: The power supply circuit includes an inductor (L1), a second capacitor (C2), a first voltage regulator tube (D1), a ninth resistor (R9), a second voltage regulator tube (D2), a third NPN tube (Q4), a boost circuit and a linear regulator; The input end of the boost circuit is connected to the power supply, the output end is connected to the first end of the fourth resistor (R4) and the second end of the second resistor (R2) in the feedback control subcircuit, the first end of the inductor (L1) is connected to the power supply, the second end of the inductor (L1) is connected to the collector of the third NPN tube (Q4), the first end of the ninth resistor (R9), the first end of the first voltage regulator tube (D1), the first end of the second capacitor (C2) and the input end of the linear regulator; the second end of the ninth resistor (R9 ... The base of the linear regulator (Q4) and the first end of the second voltage regulator (D2); the second end of the second capacitor (C2), the second end of the first voltage regulator (D1) and the second end of the second voltage regulator (D2) are all grounded, and the emitter of the third NPN tube (Q4) serves as a first power supply end and is connected to the input end of the reference voltage generation subcircuit; the second end of the linear regulator is grounded, and the third end of the linear regulator serves as a second power supply end and is connected to the power supply end of the feedback subcircuit; the output end of the boost circuit serves as a third power supply end to provide a bias voltage for the feedback control subcircuit.

8. The closed-loop control surge suppression circuit based on NMOS tube according to claim 7, characterized in that: The reference voltage generating subcircuit comprises a tenth resistor (R10) and a third voltage regulator tube (D3); Wherein, the first end of the tenth resistor (R10) is connected to the first power supply end of the power supply subcircuit, the second end of the tenth resistor (R10) is connected to the first end of the third voltage regulator tube (D3) and the in-phase end of the operational amplifier in the feedback subcircuit, and the second end of the third voltage regulator tube (D3) is grounded.

9. The closed-loop control surge suppression circuit based on NMOS tube according to claim 8, characterized in that: The feedback subcircuit also includes a feedback network; The feedback network is connected between the inverting terminal and the output terminal of the operational amplifier, the output terminal of the operational amplifier is the output terminal of the feedback subcircuit, and the non-inverting terminal of the operational amplifier is connected to the output terminal of the reference voltage generating subcircuit.

10. The closed-loop control surge suppression circuit based on NMOS tube according to claim 9, characterized in that: The feedback network includes an eleventh resistor (R11), a third capacitor (C3) and a fourth capacitor (C4); Wherein, the first end of the eleventh resistor (R11) is connected to the output end of the feedback sub-circuit and the first end of the fourth capacitor (C4), the second end of the eleventh resistor (R11) is connected to the first end of the third capacitor (C3), and the second end of the third capacitor (C3) and the second end of the fourth capacitor (C4) are connected to the inverting end of the operational amplifier in the feedback sub-circuit.

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