66 results about "Circuit reliability" patented technology

The invention discloses a pulse wave signal detection-oriented transimpedance amplifier circuit with input voltage clamping and current offset functions, and relates to the technical field of integrated circuit design, the pulse wave signal detection-oriented transimpedance amplifier circuit comprises a pseudo-differential structure, a current offset module and a photosensitive diode, the pseudo-differential structure is composed of two independent operational amplifiers with double-end input and single-end output, the trans-impedance amplifier of a pseudo-differential structure composed of two independent operational amplifiers with double-end input and single-end output is used, the same voltage is connected to the same-direction input end of the trans-impedance amplifier, voltage clamping is carried out on double-end input, the differential mode precision and low-frequency stability of an input virtual site are improved, differential mode imbalance and flicker noise caused by operational amplifier mismatch are eliminated, and the stability of the trans-impedance amplifier is improved. The dynamic range of the pulse wave detection system is improved, and the pulse wave detection system has the advantages of high-precision and wide-range ambient light suppression effect, high circuit reliability, low circuit complexity, easy implementation, high loop stability, small area and low power consumption.

The invention provides a power-limited resonant converter and converter equipment, and relates to the technical field of electronic circuits. The power-limited resonant converter comprises a primary side circuit, a secondary side circuit, a transformer module and a resonant module, the resonant module comprises at least one resonant capacitor, two ends of each resonant capacitor are reversely connected in parallel with a clamping unit, the clamping units are used for being disconnected when the current of the resonant converter is lower than a preset current, and the resonant converter works in a resonant state. When the current of the resonant converter is not lower than the preset current, the resonant capacitor is conducted and bypassed, and the resonant converter works in a non-resonant state. According to the invention, the voltage of the resonant cavity is limited to the preset value through the clamping units which are reversely connected in parallel, so that the current of the resonant cavity is reduced, the current of a switching tube can be fundamentally prevented from rapidly rising, the primary side current is always in a safe range, a conventional overcurrent protection scheme that primary side driving is blocked by overcurrent of a middle circuit does not need to be adopted, and the reliability of the circuit is improved.

This invention discloses a frequency self-calibration circuit based on a voltage-mode RC relaxation oscillator, belonging to the field of integrated circuits. By storing time errors, it performs negative feedback control on the trigger times of the rising and falling edges of the output clock signal, automatically calibrating the output signal frequency. Furthermore, it achieves DC deviation elimination in the self-calibrating operational amplifier, significantly reducing offset voltage. This invention solves the problem of unstable signal output frequency in voltage-mode RC relaxation oscillator circuits due to changes in ambient temperature. It can be applied to Delta-Sigma ADC circuits, filter circuits, phase-locked loop circuits, etc., improving resistance to ambient temperature changes and compensating for comparator switching delays. t d This improves the linearity of the clock oscillator, enhances circuit reliability, and meets the accuracy requirements of highly integrated signal chain acquisition systems.

The application provides a VCO digital circuit control method and system with temperature compensation, relates to the technical field of circuit control, and comprises the following steps: obtaining a VCO output frequency and real-time temperature, and calculating an initial frequency deviation; correcting the frequency deviation based on a temperature compensation coefficient, and generating a temperature-frequency deviation characteristic curve; determining an optimal compensation factor through Monte Carlo sampling; dynamically adjusting the compensation factor by using a Bayesian iteration to calculate a compensation parameter adaptive weight; and generating a control signal through a digital integrator to realize frequency calibration. The application realizes high-precision frequency stability of the VCO under the condition of temperature change, and improves circuit reliability.

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

The utility model discloses a kind of switch power supply over-voltage and under-voltage protector based on magnetic latching relay, it is related to electric power control field, solve the circuit reliability insufficient and cannot be applicable to wide voltage range scene by conventional relay.Between the input end of switch power supply circuit connects live wire and zero line, its output end is connected voltage control circuit in turn, voltage signal circuit input end is parallel between live wire and zero line, and its output end is accessed voltage control circuit;Relay action circuit is electrically connected with voltage control circuit, for executing on-off action when the voltage signal output by voltage control circuit exceeds or is lower than set threshold value.Switch power supply circuit as front-end processing unit, it can adapt to the conversion demand of wide range ac input voltage, magnetic latching relay is more advantageous in power consumption, action stability, can accurately and timely execute protection action according to the instruction of voltage control circuit under the condition that input voltage fluctuation is larger.

This invention discloses a complete set of high-current, wide-power-range, all-dielectric-isolated BCD-on-SOI integrated technology and ESD-protected VDMOS devices. The integration steps are as follows: 1) Forming an N-type buried layer and a P-type buried layer on the surface of the substrate silicon wafer. 2) Forming a DTI deep trench isolation region. 3) Forming a vertical DMOS drain-side-well N+-N-type buried layer interconnect structure. 4) Forming an insulating silicon top-side-well P+-P-type buried layer interconnect structure. 5) Forming an ESD-protected vertical DMOS device structure. 6) Completing the planarization of the device-metal inter-dielectric layer. 7) Completing the through-hole tungsten plug structure fabrication. 8) Sputtering aluminum-copper film layers and completing the metal interconnect etching process. The device includes a P-type substrate silicon wafer, an N-type buried layer, a P-type buried layer, an insulating silicon dioxide buried layer, a P-type device layer, a dielectric isolation trench region, an N-type epitaxial layer, a P-type epitaxial layer, a gate dielectric layer, a polycrystalline thin film, an oxide thin film, a tungsten plug, and a metal thin film layer. This invention solves the integration problem of high-current vertical DMOS with BCD-on-SOI process, as well as the challenge of high-density standard device integration, thereby improving the circuit reliability of the process.

The invention belongs to the technical field of power electronics, and discloses a BUCK upper tube driving circuit, which comprises a fast voltage domain conversion circuit, a slow voltage domain maintenance circuit, a secondary voltage domain conversion circuit, a driving signal detection circuit and a power level circuit, the fast voltage domain conversion circuit and the slow voltage domain maintenance circuit are connected in parallel, and the corresponding output ends are jointly connected to the input end of the secondary voltage domain conversion circuit; the output end of the secondary voltage domain conversion circuit is connected to the input end of the driving signal detection circuit and the input end of the power level circuit. The output end of the power level circuit serves as the driving output end TGDRV of the whole driving circuit. Through the structural design of the BUCK upper tube driving circuit, the upper tube driving of the BUCK circuit in the working range of 6-120V power supply voltage can be realized, the switching frequency is supported to 2MHz, when the circuit is in a static state, no theoretical static power consumption exists, the design requirement of low power consumption can be met, and meanwhile, the circuit is provided with a driving signal detection circuit, so that the circuit reliability is improved.

The invention discloses a circuit aging overcoming method based on a post-silicon regulation technology, and relates to the field of digital integrated circuit reliability design, and the circuit aging overcoming method comprises the steps: determining a slow path in a plurality of data paths in a monitored circuit, the target trigger in each low-speed path is connected with an establishment time violation early-warning unit, and the establishment time violation early-warning unit generates an establishment time early-warning signal when monitoring that the connected trigger is about to generate an establishment time violation; the target triggers of the multiple low-speed paths are divided into multiple trigger groups, each trigger group corresponds to one clock adjusting unit, and the target trigger of each low-speed path in each trigger group is connected with the corresponding clock adjusting unit; and the clock adjusting unit configures the clock edge delay arrival time of the connected trigger based on the establishment time early warning signal so as to realize the effect of overcoming circuit aging. The method can effectively overcome circuit aging and improve circuit reliability.

The invention relates to the technical field of energy storage power supplies, and mainly provides a photovoltaic insulation detection fault positioning circuit and an energy storage system. The circuit comprises a detection module, a first control module, at least one second control module and at least two positioning modules. The first control module and the second control modules are connected with the detection module and the corresponding photovoltaic input sources respectively, control signals are output in sequence, the corresponding photovoltaic input sources are connected into the detection module, insulation detection of multiple paths of photovoltaic input sources through a single detection module is achieved, and the circuit cost is reduced. The detection module detects the insulation impedance of the accessed photovoltaic input source when receiving the driving signal, and outputs a fault signal when the impedance is lower than a preset range, thereby responding to the fault in time, and improving the reliability of the circuit. And after the positioning module receives the corresponding control signal and the fault signal, an indication signal is output, the fault photovoltaic input source is accurately positioned, the troubleshooting time is shortened, the labor cost is reduced, and the operation and maintenance efficiency is improved.

The invention discloses a switching power supply and a power tube driving circuit for the switching power supply, and the power tube driving circuit comprises a logic control module which is used for generating a conduction control signal and a turn-off control signal according to a received switching control signal; the driving module is used for generating a gate driving signal of the power tube according to the turn-on control signal and the turn-off control signal, the gate driving signal has a first slope and a second slope which are related to time in the turn-off process of the power tube, and the first slope is larger than the second slope; the voltage detection module is used for detecting drain-source voltage of the power tube when the power tube is turned off so as to obtain a voltage detection signal; the variable slope control module is used for comparing the voltage detection signal with the reference voltage and adjusting the time duration of the first slope of the gate driving signal in the next switching period according to the obtained comparison result, so that the turn-off loss of the power tube cannot be increased while the voltage stress in the turn-off process of the power tube is reduced; and meanwhile, high-efficiency driving and circuit reliability are considered.

The invention relates to the technical field of power electronics, and discloses a self-driven rectifying circuit. Comprising a rectifier tube, a follow current tube, a third switch tube, a fourth switch tube, a dead zone adjusting circuit comprising a first capacitor and a first voltage-regulator tube, a main transformer comprising a first induction coil and a second induction coil, a first amplitude limiting circuit comprising a sixth switch tube, and a second amplitude limiting circuit comprising a fifth switch tube. According to the technical scheme, self-driving is achieved through the main transformer driving winding, the simplified peripheral circuit design is adopted, the component cost is effectively reduced, a safe dead zone is set through the dead zone adjusting circuit, the risk that a rectifier tube and a follow current tube are communicated together is completely eradicated through the interlocking circuit, and driving signal overshoot is restrained through the amplitude limiting circuit; the low cost is maintained while the high performance is ensured, so that the switching loss is effectively reduced, the circuit reliability, the anti-interference capability and the overall efficiency are improved, and the defects of large conduction loss, low reliability and high cost of traditional diode rectification are overcome.

This invention discloses an industrial RFID reader / writer suitable for high-temperature and high-pressure environments and its data transmission method. The RFID reader / writer includes a shell, a PCB board, and a memory. The shell has a heat insulation layer on the inside. The PCB board includes a high-temperature circuit module, a dual-mode communication module, a pressure compensation system, and a power supply module. The high-temperature circuit module, dual-mode communication module, and pressure compensation system are installed inside the heat insulation layer. The high-temperature circuit module includes a main control unit, an RFID radio frequency unit, a temperature monitoring unit, and a power management unit. This invention has strong tolerance to extreme environments, high circuit reliability, and a continuous working life of ≥10,000 hours, which is more than 5 times that of traditional readers / writers. It has no dead zones in communication, long working time, and meets the long-term use requirements of highly corrosive media environments. The RFID communication submodule supports the ISO18000-6C protocol, has a maximum identification distance of 8 meters, and can identify 50 tags per second simultaneously.

The application provides an analog light MOS relay, and belongs to the technical field of integrated circuits, and comprises: a first clamping circuit used for clamping the voltage of an input end; an LC resonant oscillator comprising an active nonlinear load, a transformer and a capacitor circuit; a rectifier circuit connected with the LC resonant oscillator and used for rectifying the alternating current signal output by the LC resonant oscillator into a direct current signal; a voltage boosting module connected with the rectifier circuit and used for boosting the direct current signal; and an output circuit comprising a first power device and a second power device. The first clamping circuit is used to realize the function of an analog diode, the voltage drop of the first clamping circuit is more stable, and the consistency is better; the transformer, the active nonlinear load and the capacitor circuit jointly form the LC resonant oscillator, the LC resonant oscillator can automatically resonate to the resonant frequency, and the circuit has high reliability.

This invention proposes a CML level driving circuit and electronic device. The sampling terminal of the control unit is connected to the positive and negative output terminals of the CML level driving circuit, and the output terminal of the control unit is connected to a second current source. The control unit detects the output swing of the CML level driving circuit and adjusts the output current of the second current source based on the output swing. The output current of the second current source changes with the output swing; the larger the output swing, the larger the output current of the second current source, which increases the common-mode voltage at the output terminal, enabling the circuit to drive and amplify normally and ensuring the quality of the output signal. The smaller the output swing, the smaller the output current, reducing circuit power consumption, simplifying heat dissipation design, and increasing circuit reliability.

The application provides a SSPC motor forward and reverse rotation control circuit with dead zone isolation driving, four control signals are output by a single master control unit, four MOSFETs are driven through two double-channel gate drivers, and the forward and reverse rotation of the motor is controlled. Double interlocking and protection of forward and reverse rotation control is realized by using a dead zone generation module in a CPLD and a dead zone setting of an isolation driving chip, and the reliability and stability of the circuit are improved.

The utility model discloses an integrated circuit reliability test device, which relates to the technical field of integrated circuit test and comprises a power supply module used for accessing alternating current electric energy, processing the electric energy, transmitting the electric energy and supplying power to an integrated circuit connected with an integrated circuit module; the temperature detection module is used for detecting temperature and controlling the timing control module to be electrified; the over-temperature detection module is used for controlling the alarm module to give an alarm when the temperature is over-high; the timing control module is used for controlling the sampling and holding module to carry out sampling transmission processing within the sampling time and controlling the sampling and holding module to carry out signal holding processing within the detection time; and the temperature change detection module is used for calculating a temperature difference and controlling the alarm module to give an alarm when the temperature difference is greater than a set difference threshold value. The integrated circuit reliability test equipment can carry out temperature change abnormity alarm or over-temperature alarm, can conveniently and effectively detect the temperature change degree of the integrated circuit, and then judges the reliability degree of the integrated circuit.

The invention specifically discloses an AES encrypted circuit-oriented anti-radiation soft error analysis method based on CVPI, and relates to the technical field of integrated circuit reliability testing. The method comprises the following steps: S1, inputting single-particle soft error simulation parameters; s2, synthesizing a register transfer level RTL code of the AES encryption circuit into a netlist; s3, the RTL and the gate-level netlist of the AES encrypted circuit are analyzed, and RTL instance representation information and netlist unit information are extracted; s4, constructing a single-particle soft error database; s5, based on the upset section model and Poisson distribution time modeling, generating a single-particle soft error injection list; s6, performing batch single-particle soft error injection on the AES encrypted circuit based on the user-defined CVPI interface; and S7, generating an AES encrypted circuit single-particle soft error analysis report. According to the method, the precision and efficiency of anti-radiation soft error analysis of the AES encryption circuit are improved, and support is provided for design of a high-reliability encryption chip.

This application relates to the field of terminal technology, providing a signal transmission method, a transmission circuit, an RF chip, and related products. The method is applied to a transmission circuit and includes: in a first state, transmitting a first signal through a transmission path in the transmission circuit, the transmission power of the first signal being a first transmission power; in the first state, a signal fed back by a feedback path in the transmission circuit is used to indicate that the transmission power of the first signal is a second transmission power, the second transmission power being greater than the first transmission power, and the difference between the second transmission power and the difference between the second transmission power and the first transmission power, and the difference between the second transmission power and the first transmission power and a first power error, is less than a first error threshold. The first power error corresponds to a first voltage difference, the first voltage difference being the difference between a first driving voltage and a second driving voltage, and the first driving voltage being greater than the second driving voltage. This method can prevent power amplifier module failure and improve circuit reliability.

This invention belongs to the field of secondary equipment testing and maintenance technology in power distribution networks. Specifically, it relates to a portable automatic testing method, system, and device for protection circuits adapted to FTUs, DTUs, and sectionalizing switch terminals. Relying on handheld equipment, it is compatible with dual-condition testing and completes fully automatic testing through five steps: preliminary screening of appearance and insulation, coarse screening of circuit continuity and impedance, fine screening of electrical steady-state characteristics, fault condition logic verification, and risk rating and archiving. The fine screening stage employs differential scanning, multi-parameter acquisition, noise removal, and fingerprint database comparison to achieve pin-level fault location. Combined with fault simulation and risk rating models, it completes circuit reliability verification. This invention features an integrated hardware and software design, effectively solving the pain points of traditional testing methods. It offers precise positioning, portability, and interference resistance, is suitable for on-site power distribution network operations, and has engineering promotion value.

The invention relates to a high-input reverse voltage-withstanding four-channel high-speed photoelectric coupler, and belongs to the technical field of semiconductor devices and packaging. The device comprises a ceramic shell, and four high-speed photosensitive integrated circuit chips which are isolated from one another are arranged in the ceramic shell; the number of the ceramic carriers is four, and each ceramic carrier is provided with a light-emitting diode chip and a reverse voltage-resistant protection diode chip; one surface, provided with the light-emitting diode chip and the protection diode chip, of each ceramic carrier faces the interior of the ceramic shell and is fixed above the high-speed photosensitive integrated circuit chip, and the light-emitting diode chip and the high-speed photosensitive integrated circuit chip are oppositely arranged; and the cover plate is arranged on the ceramic shell and is used for packaging the device. According to the invention, the input reverse voltage endurance capability of the device is improved, a protection circuit is not needed, the circuit complexity is reduced, the PCB space is saved, and the circuit reliability is improved.

The application relates to a pre-stabilization circuit based on a band gap reference core, which comprises a driving tube, a high-gain feedback, an impulse protection circuit, a multi-path starting and biasing unit, a band gap reference core and a voltage dividing feedback resistor. When the circuit is powered on, the output DC voltage will completely depend on the band gap reference core and the voltage dividing feedback resistor and will not be related to the input voltage. When the output voltage changes, the error voltage will be transmitted to the band gap reference core through the voltage dividing feedback resistor, the state of the high-voltage PMOS driving tube is adjusted through the high-gain feedback path, and stable output is realized. The application solves the problems of low output voltage precision, weak load driving capacity and low circuit reliability existing in the prior art, and can be used as a high-voltage pre-stabilization circuit of a general high-voltage power supply integrated circuit including an LDO and a DC-DC.

The application discloses an interface circuit with hysteresis and level shift characteristics, comprising a VCC power supply end, a COM end, an amplification circuit and a load circuit arranged in sequence between the VCC power supply end and the COM end, and a bias generation circuit connected with the amplification circuit and the load circuit; the bias generation circuit is also connected with the VCC power supply end and the COM end; the amplification circuit and the load circuit are connected with an output node VO; the output node VO is connected with an input end of an inverter or a Schmidt trigger; and an output end of the inverter or the Schmidt trigger is connected with the amplification circuit and the load circuit. The application can realize the hysteresis characteristic of the interface circuit, improve the noise resistance and interference resistance of the interface circuit, directly realize the level shift operation of signals, greatly simplify the circuit structure, improve the circuit reliability, and has the characteristics of simple structure, few required devices and low circuit design difficulty.

The application provides a power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. In the application, a main power VDMOS cell array, a sampling power VDMOS cell and at least one discharge path control LDMOS cell are integrated on a SiC epitaxial layer. When the power semiconductor device is in a working state, the sampling power VDMOS cell is used to obtain a real-time electrical signal of a JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold value, a low-resistance discharge path is turned on to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, the short-circuit resistance time of the application is improved by integrating a short-circuit protection structure, and the short-circuit reliability of the device is improved.

The invention discloses a design method of a pin-free chip type integrated circuit electrified vibration device and a clamp thereof, and belongs to the technical field of integrated circuit reliability test. A to-be-tested pin-free chip-type integrated circuit is placed in a positioning groove, a bottom pin of the to-be-tested pin-free chip-type integrated circuit faces downwards, the pin is electrically connected with a test circuit board below the pin through an ejector pin, an elastic silica gel sheet is additionally arranged between the top surface of the to-be-tested pin-free chip-type integrated circuit and a pressing mechanism, and the elastic silica gel sheet is arranged on the top surface of the to-be-tested pin-free chip-type integrated circuit. The pin-free chip integrated circuit to be tested is elastically and horizontally pressed, and the ejector pin is upwards pressed and contacted from the bottom, so that the bottom surface pin of the device to be tested is tightly contacted with the ejector pin. The problems that in the prior art, a spring probe or a metal elastic piece is used for making contact with a pin at the bottom of a device to achieve electrical connection, then the device is pressed through a pressing mechanism, the end of the spring probe shifts in the vibration environment, and even a chip or the probe is damaged are solved. The device can be widely applied to live-line vibration tests in the fields of aerospace, military industry and the like, and is compatible with screening tests such as live-line temperature circulation.

The application discloses an IC integrated circuit reliability test machine and a test method, and belongs to the technical field of circuit testing.The IC integrated circuit reliability test machine comprises a rack, a conveying assembly is installed in the rack, supporting seats are fixed on the two sides of the rack, an installation assembly is fixedly installed on the supporting seat, a test assembly is installed on the installation assembly, side supporting plates are installed on the upper surfaces of the two sides of the rack, and a cleaning assembly is installed on the side supporting plate.The application solves the problem that the test port of an integrated circuit may be contaminated by impurities in the actual use process of the prior art, and the application cleans dust and impurities on the IC integrated circuit through the set wiping sponge and brush, guarantees the cleanliness of the surface of the IC integrated circuit, ensures that the IC integrated circuit is not interfered by impurities during the test, improves the reliability of the IC integrated circuit test, guarantees the accuracy of IC integrated circuit wiring, and makes the test result more reliable.

The utility model belongs to the technical field of high-power switching power supplies, and particularly discloses a circuit board structure for a high-power switching power supply, which comprises a substrate, a first laminated plate and a second laminated plate. The substrate is provided with a circuit layer, an insulating layer and a metal base layer, a wiring area is arranged in the middle of the circuit layer, and element arrangement areas are arranged on the two sides of the circuit layer and used for installing MOSFETs. The first laminated plate is used for mounting a rectifying device, and the second laminated plate is used for mounting a driving device. According to the design, the element layout is optimized, the rectification circuit design is simplified, the space utilization rate is improved, current and signal transmission is more direct and efficient, the transmission loss and temperature rise are reduced, the circuit reliability and stability are enhanced, the design complexity is simplified, and the circuit integration level and the power density are improved; the problems of heat dissipation, installation, current sharing and driving design in a high-power switching power supply are effectively solved.

The utility model discloses a kind of quick braking circuit and dental hollow cup brushless motor, including the six-arm full-bridge drive circuit of adaptation three-phase brushless motor;Schottky diode is respectively connected in parallel between the input end and output end of three high-side bridge arms, and the conduction direction is opposite with the conduction direction of the high-side bridge arm;Discharge resistance, one end is connected with the input common end of three low-side bridge arms, the other end connects the cathode common end of three schottky diodes.The utility model significantly reduces the energy loss of braking current path, reduces the heat on the discharge path, improves circuit reliability;Discharge resistance concentrates and dissipates motor kinetic energy, avoids overheating problem caused by energy dispersion on bridge arm device, greatly shortens motor stop time, especially suitable for high-speed dental motor, can be reduced from 3-5 seconds to sub-second level;Without changing original drive logic, only by adding new device to realize quick braking, strong adaptability.

This invention provides a power semiconductor device and its fabrication method, relating to the field of semiconductor technology. In this application, the power semiconductor device integrates a main power VDMOS cell array, sampling power VDMOS cells, and at least one discharge path control LDMOS cell on a SiC epitaxial layer. When the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold, it conducts a low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, this application improves its short-circuit withstand time by integrating a short-circuit protection structure, thereby enhancing the short-circuit reliability of the device.

The invention discloses a clock signal level shifting circuit with an initial starting module by utilizing edge triggering, which is applied to a high-voltage circuit, and comprises a low-voltage domain digital unit, a first low-voltage clock signal and a second low-voltage clock signal, a second low-voltage domain digital unit, a first low-voltage domain digital unit, a first low-voltage domain digital unit, a second low-voltage domain digital unit and a second low-voltage domain digital unit, the high-voltage domain level conversion module is used for generating a first high-voltage clock signal and a second high-voltage clock signal according to the first low-voltage clock signal and the second low-voltage clock signal; the initial starting module is used for providing initial potential for the high-voltage domain level conversion module; wherein the low-voltage domain digital unit and the high-voltage domain level conversion module are connected through a first high-voltage-resistant capacitor C3 and a second high-voltage-resistant capacitor C4; and the low-voltage domain digital unit, the high-voltage domain level conversion module and the initial starting module all adopt low-voltage MOS (Metal Oxide Semiconductor) tubes. The circuit can be integrated, the chip area is small, the anti-interference capability of the circuit is strong, and the circuit reliability is high.