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Circuit reliability evaluating method based on signal probability

A technology of signal probability and reliability, applied in electronic circuit testing and other directions, can solve problems such as large space-time complexity and difficulty in evaluating large-scale circuits.

Inactive Publication Date: 2014-12-17
SHANGHAI UNIVERSITY OF ELECTRIC POWER
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AI Technical Summary

Problems solved by technology

The model used in this method is accurate and complete, but because the scale of the matrix increases exponentially with the increase of the number of circuit signal terminals, the time and space complexity is too large to be used for evaluating large-scale circuits.

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  • Circuit reliability evaluating method based on signal probability

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Embodiment Construction

[0029] Aiming at the problems existing in the original PTM method, the present invention proposes an optimization scheme for large-scale circuits to calculate its reliability based on PTM, and adopts the following strategies:

[0030] 1. Read the integrated circuit gate-level netlist (such as ISC format or BLIF format), analyze the netlist to obtain the connection structure between each gate node, and use the segmentation algorithm to divide the circuit into a group of appropriate size and overlapping each other. Fewer modules (see below for the segmentation algorithm);

[0031] 2. Each module is a sub-circuit, and the PTM method is used for the sub-circuit to calculate the reliability of each module in turn;

[0032] 3. Based on the idea of ​​calculating the joint probability of independent events, the reliability of the entire circuit is evaluated by the product of module reliability.

[0033] Strictly speaking, the premise of the above scheme is that the reliability of eac...

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Abstract

The invention relates to a circuit reliability evaluating method based on the signal probability. The method includes reading an integrated circuit gate level netlist, analyzing the netlist to acquire connection structures of gate nodes, and providing a segmentation algorithm to segment the circuit into a plurality of modules; allowing each module to be one sub circuit, utilizing the PTM method onto the sub circuits, and calculating the reliability of each module sequentially; evaluating the reliability of the entire circuit according to the principle of calculating the independent event joint probability through the module reliability product. By the aid of the segmentation algorithm, the majority of modules are guaranteed being free of redundancy on functions and overlap on structures. The problem that only small-scale circuits can be evaluated by a PTM method is optimized, and the evaluating method can be applied to large-scale circuits; in addition, the TP method, the EPP method and the optimized PTM method are integrated to develop a circuit reliability evaluating platform which can be applied to the circuit designing step to calculate the reliability, and the designed structure can be adjusted conveniently and timely.

Description

technical field [0001] The invention relates to a circuit detection technology, in particular to a circuit reliability evaluation method based on signal probability. Background technique [0002] The traditional integrated circuit reliability evaluation is oriented to the chip manufacturing process, and its reliability is analyzed through reliability tests (such as environmental tests, life tests, screening tests, field use tests, etc.), or the manufactured electronic components are tested by testing methods. Device reliability is measured and analyzed. With the development of VLSI circuit technology and the improvement of reliability level, this kind of evaluation method has exposed problems such as "hysteresis" and too many samples. [0003] Reliability evaluation for circuits at a higher abstraction level (including gate level, RTL level and system level) can be applied in the circuit design stage, that is, to estimate the reliability of the circuit before tape-out packa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 王真雷景生
Owner SHANGHAI UNIVERSITY OF ELECTRIC POWER
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