34 results about "Scaling circuits" patented technology

Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

The disclosed computing device can include video scaling circuitry configured to generate scaled video data by scaling decoded video data. The computing device can also include film grain noise generation circuitry configured to generate film grain noise data based on one or more parameters included with encoded video data from which the decoded video data is generated. The computing device can further include film grain noise application circuitry configured to apply the film grain noise data to the scaled video data. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses an Alliance tool chain logic synthesis method based on multiple logic domains. The method comprises the following steps that an intermediate representation structure of a target circuit is obtained; mapping a Boolean expression in the intermediate representation structure into an XMG network equivalent to the logic function of the target circuit; logic optimization with the optimization logic hierarchy as the target is executed on the XMG network obtained through mapping; converting the XMG network after logic hierarchy optimization into an AIG network; logic optimization with optimization of the number of nodes as a target is executed on the AIG network obtained through conversion, and the optimized AIG network is output as an aig file; and reading the aig file, analyzing the aig file, outputting the analyzed aig file as a VHDL file, inputting the VHDL file to the Alliance tool chain, and generating a gate-level netlist corresponding to the optimized target circuit. According to the method, the logic optimization efficiency and expandability can be greatly improved, the performance bottleneck of an existing Alliance tool chain is effectively solved, and the large-scale circuit design processing capacity of the Alliance tool chain is remarkably improved.

The invention relates to the technical field of electronic design automation, and discloses a performance optimization method and system for an integrated circuit debugging tool, and the method comprises the steps: analyzing a design file, constructing an analysis database, carrying out the dynamic complexity evaluation of each module in the design based on a plurality of preset complexity indexes, and generating a module complexity classification result; according to the module complexity classification result, dividing the module into a complex module, a top-layer module and a lightweight module, and executing pre-refining processing on the complex module and the top-layer module to generate a core refining database; in the user interaction process, according to user operation behaviors, dynamically triggering refinement processing on an unloaded module, and supplementing a refinement result to the core refinement database as required; a user interface is updated in real time based on the core refinement database, a non-delay module hierarchical structure and signal information display are provided, tool initialization time and memory consumption are remarkably reduced, and large-scale circuit debugging efficiency is improved.

The embodiment of the invention discloses an electromagnetic transient simulation method, device and equipment for topological reconstruction of a basic element, and the method comprises the steps: determining an equivalent element circuit corresponding to a newly-added circuit assembly when receiving an assembly adding signal for introducing the newly-added circuit assembly into a main circuit; wherein the equivalent element circuit is composed of a plurality of basic elements with element configuration parameters; connecting the equivalent element circuit to the main circuit to obtain a target main circuit, and determining a node admittance matrix corresponding to the target main circuit; carrying out electromagnetic transient simulation operation on a target main circuit based on the node admittance matrix, automatically mapping a newly-added circuit component into an equivalent circuit formed by a standardized basic element and configuration parameters thereof, and automatically generating a unified node admittance matrix on the basis; model inconsistency caused by personal errors and subjective experience is remarkably reduced, the problems of node index conflicts and unstable matrix numerical values are avoided, and the simulation efficiency and precision of a large-scale circuit system are remarkably improved.

The invention discloses a DTCO circuit structure optimization method and system based on deep learning and heuristic search, and the method comprises the steps: obtaining a circuit netlist of a target circuit for analysis, and dividing the target circuit into a plurality of independent function modules based on function demands; predicting the performance of different devices in the target circuit under a plurality of target process conditions based on a pre-trained deep learning model; searching an optimal circuit connection mode of the target circuit based on a heuristic search algorithm so as to carry out circuit structure layout topology; performing parameter optimization on the target circuit based on the optimal circuit connection mode; and based on the parameter optimization, evaluating the topological circuit through an SPICE simulation tool, verifying whether an optimization result meets a design requirement or not, and if the optimization result meets the design requirement, completing the optimization. Through a deep learning model and a heuristic search algorithm, with the guidance of agile design methodology, rapid and efficient optimization of an advanced process node large-scale circuit structure is realized.

The invention discloses a critical path standard cell-oriented transistor-level time sequence prediction method and system. The method comprises the following steps of: obtaining a transistor-level intrinsic characteristic of a standard cell and a state characteristic of the standard cell; carrying out feature fusion on the transistor-level intrinsic feature and the state feature of the standard unit to obtain a standard unit time sequence feature; analyzing based on the time sequence characteristics of the standard cell, and predicting the time sequence data of the transistor level of the standard cell; and training the time sequence analysis model based on the time sequence data of the transistor level of the standard cell to obtain a trained time sequence analysis model so as to predict the predicted standard cell and obtain a time sequence prediction result. According to the method, the time sequence prediction problem in the super-large-scale circuit design, especially a standard unit in an undefined library, can be efficiently solved; through automation and optimization of time sequence prediction, the design period is shortened, the consumption of computing resources is reduced, and the time sequence optimization process is accelerated.

The invention relates to a directional scaling system and method. An electronic device may include scaling circuitry to scale input pixel data to a greater resolution. The directional scaling circuit may include a first interpolation circuit to receive optimal mode data, the optimal mode data including one or more angles corresponding to content of an image, and interpolating a first pixel value at a first pixel position diagonally offset from an input pixel position from the input pixel data based on the optimal mode data and an input pixel value corresponding to the input pixel position. The directional scaling circuit may also include a second interpolation circuit to receive the optimal mode data and the input pixel value, and to interpolate a second pixel value based at least in part on the optimal mode data and the input pixel value at a second pixel position that is horizontally or vertically offset from the input pixel position.

The application discloses a circuit pre-training method and device based on a graph neural network and electronic equipment, comprising the following steps: for a large-scale circuit, a circuit network graph is constructed, a random walk road is generated, and the road is used as a sample for model training; a node2vec model is trained using the road sample; a model with the minimum loss function value is selected as an optimal model; and the optimal model is loaded, and representation vectors of all nodes are output and saved. In the application, the node2vec pre-training model of the graph neural network is used, the information of a long-distance standard unit is fully absorbed to absorb local circuit structure features, deep representation of nodes is automatically learned from the circuit structure, and tedious manual feature engineering is avoided, thereby providing high-quality representation vectors for a downstream model. The node representation learned by the node2vec model is a task-independent general feature, can be flexibly applied to various downstream tasks, and provides support for subsequent circuit analysis and optimization design work.

The invention relates to a large-scale circuit partitioning method and device based on a space filling curve, and the method comprises the steps: dividing component entities recorded by a netlist according to attribute requirements after the netlist is imported, taking the connection relation recorded by the netlist as the basis, and optimizing the circuit partitioning process through employing various characteristics of the space filling curve. And the efficiency of circuit physical design is improved. As the whole geometric space of the actual circuit partition space can be filled with the space filling curve, the partition sequence after sorting and partitioning can be directly mapped into the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the assistance of the size of the component. In addition, the partitioning process is combined with the number of the components, it can be guaranteed that the number of the components in all the partitions is balanced, the density of the components is reasonably controlled, the partitioning quality is improved, and all the partitions can execute follow-up partitioning content in parallel so as to accelerate the partitioning process and reduce time expenditure.

The invention discloses a large-scale circuit division method based on artificial intelligence adaptive weight allocation, and belongs to the technical field of integrated circuit computer aided design, and the method specifically comprises the following steps: firstly, building a graph structure, and obtaining data containing circuit topology features; thirdly, the input is converted into the uniform length in a cubic interpolation mode, and the universality of the model is improved; a gating mechanism is introduced, structures of an input gate, an output gate and a forgetting gate are established, and the model is helped to better perceive the dependency relationship between inputs; training the data with the circuit topology characteristics obtained by the above processing to obtain a weight distribution model, and updating the division weight; and finally, dividing a large-scale circuit by adopting the updated weight to realize multi-index balanced parallel system simulation. According to the method, the circuit simulation process is accelerated, and the parallel benefit is improved.

A radio frequency (RF) receiver is described, the RF receiver comprising: a plurality of analog mixing circuits including circuits for down-converting an input RF signal; a plurality of analog combining and scaling circuits operably connected to the analog mixing circuits and for generating a plurality of intermediate signals; a digital combining and scaling circuit operably connected to the analog combining and scaling circuits, the digital combining and scaling circuit comprising: in-phase signal component (I) circuitry for performing a first combining and scaling operation on a set of two or more of the plurality of intermediate signals to generate an in-phase signal component of a baseband signal; quadrature phase signal component (Q) circuitry for performing a second combining and scaling operation on another set of two or more of the plurality of intermediate signals to generate a quadrature phase signal component (Q) of the baseband signal.

This invention discloses a rapid assessment method for soft error rate caused by single-event effects based on an analytical function library. It addresses the problems of low efficiency and difficulty in supporting large-scale circuit evaluation in traditional TCAD simulation. The method constructs and calibrates device models based on process design kits to obtain accurate electrical characteristics of the calibration device model. Based on multidimensional key irradiation variables, dense TCAD sampling and parametric fitting are performed on the calibration device to construct a response function library. Based on the actual integrated circuit layout, particle transport simulation under radiation conditions is performed in Geant4 to extract the secondary particle set. The corresponding transient current is rapidly synthesized by querying the response function library and interpolating. The current is injected into the SPICE circuit netlist for simulation to determine whether single-event upset has occurred and to calculate the soft error rate. This method achieves an order-of-magnitude improvement in simulation efficiency while maintaining accuracy, making it suitable for rapid radiation resistance assessment and design hardening of complex integrated circuits.

The invention relates to the technical field of circuit simulation waveform data visualization, and particularly discloses a circuit simulation waveform sampling method based on MinMaxLTTB. The method aims at solving the problems of display lagging and waveform distortion caused by the fact that data volume simplification and key feature point reservation cannot be considered in mass waveform data visualization in a traditional sampling technology. The method comprises the following steps: (1) dynamic bucket division: adaptively creating data buckets with different sizes based on target resolution and simulation duration; (2) MinMax extremum pre-extraction: extracting extremum points in each bucket in a layered manner to form a simplified data set; (3) sampling LTTB characteristic values, and selecting an optimal characteristic point based on a triangle area maximum principle; and (4) integrating the sampling points in sequence to generate visual special data. According to the method, dynamic bucket division and a two-stage sampling strategy are combined, the data volume is greatly reduced, meanwhile, the waveform key features are accurately reserved, the real-time visualization performance and accuracy of large-scale circuit simulation waveforms are remarkably improved, and the method is suitable for waveform display modules of various EDA tools.

The present invention provides a circuit schematic wiring data processing method, computer device, and storage medium, including: configuring two-dimensional grid data used to express circuit schematic wiring data into four sub-data types; dividing the data of each sub-data type into internal attribute data and external attribute data, with the internal attribute data storing data with read and write permissions and the external attribute data not distinguishing between read and write permissions; providing a data router to achieve grouped distribution of data of each sub-data type; configuring data processing operations to access or modify target data using data of any sub-data type as input; dividing the data processing operations into multiple ordered operations, and scheduling the ordered operations through an operation pipeline. This solution can achieve efficient access and processing of wiring data of large-scale circuit schematics, has universal applicability and scalability, and is conducive to improving the market competitiveness of products.

The invention discloses a self-adaptive hyperdimensional computing (HDC) accelerator supporting incremental learning, and belongs to the technical field of artificial intelligence hardware acceleration. The accelerator comprises a feature extraction and coding circuit, an incremental prototype-like storage resource pool, a parallel reasoning array and a confidence perception retraining circuit. Wherein the incremental prototype-like storage resource pool comprises a pre-allocated BRAM array and a write enable gating logic, and class expansion during operation is realized through logic-physical address decoupling; the confidence perception retraining circuit is integrated with a double-threshold comparator group and a barrel-shaped shift scaling circuit without a multiplier, and monitors the minimum Hamming distance in real time through a hardware comparator and drives a barrel-shaped shifter to dynamically generate an update weight. According to the method, low-overhead incremental learning is realized on the premise that hardware does not need to be synthesized again through resource isolation and adaptive weight adjustment of a pure hardware level, the disastrous forgetting phenomenon is effectively inhibited, and the retraining efficiency is remarkably improved.

Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

The present invention discloses a logic synthesis method for an Alliance tool chain based on multiple logical domains, comprising the following steps: obtaining an intermediate representation structure of a target circuit; mapping a Boolean expression in the intermediate representation structure to an XMG network equivalent to the logical function of the target circuit; performing logic optimization aiming at optimizing the logic hierarchy on the mapped XMG network; converting the XMG network with optimized logic hierarchy into an AIG network; performing logic optimization aiming at optimizing the number of nodes on the converted AIG network, and outputting the optimized AIG network as an aig file; reading the aig file, parsing and outputting it as a VHDL file, and inputting the VHDL file to the Alliance tool chain to generate a gate-level netlist corresponding to the optimized target circuit. This method can greatly improve the efficiency and scalability of logic optimization, effectively solve the performance bottleneck of the existing Alliance tool chain, and significantly enhance the ability of the Alliance tool chain to process large-scale circuit designs.

The application discloses a process angle prediction method and system in static timing analysis based on ensemble learning, which combines multilayer perceptron and graph neural network for process angle prediction. Firstly, the MLP model is used for preliminary prediction, and then the prediction result of the MLP is input into the GNN model to optimize the prediction result in the form of graph structure data. The application also uses a generative adversarial network to generate synthetic data, thereby expanding the training set and improving the prediction ability of the model. The method of the application can significantly improve the prediction accuracy and is more efficient in running speed than the traditional method. The method not only reduces the calculation overhead of the traditional STA method, but also has good adaptability and high efficiency, and is particularly suitable for process angle prediction tasks of large-scale circuits. The system architecture of the application includes a data acquisition module, an MLP module, a GNN module and a GAN data generation module, and can realize efficient and accurate process angle prediction in industrial applications.

A hardware power estimator (HPE) configured to provide a power estimate for an electronic device includes a scaling circuit configured to receive an input and produce a scaled nonlinear output of the input, wherein the scaling circuit applies an approximation of an activation function to the input. The HPE further includes multiply-add circuitry (MADD) configured to produce an output indicative of a mathematical power estimate of the electronic device using the output of the scaling. The input to the scaling circuit includes data values representing state information or activity information of one or more components or intellectual property (IP) blocks of the electronic device.

The present invention relates to a large-scale circuit partitioning method and device based on space-filling curves. After importing a netlist, component entities recorded in the netlist are partitioned according to attribute requirements. This partitioning is based on the connection relationships recorded in the netlist, and various characteristics of space-filling curves are used to optimize the circuit partitioning process, improving the efficiency of circuit physical design. Since the space-filling curve itself can fill the entire geometric space of the actual circuit partitioning space, the partition sequence after sorting and partitioning can be directly mapped into the actual circuit partitioning space, and subsequent layout design in the actual circuit partitioning space can be automatically completed with the assistance of the sizes of components. In addition, by combining the number of components in the partitioning process, the number of components in each partition can be balanced, the component density can be reasonably controlled, and the partitioning quality can be improved. Each partition can execute subsequent partitioning content in parallel to accelerate the partitioning process and reduce time overhead.

The invention discloses a scale-adaptive logic comprehensive optimization circuit representation learning method, and belongs to the technical field of integrated circuit design automation. Comprising the following steps: constructing circuit diagram data, and extracting node features, edge connection relationships and node depth information; a scale adaptive graph encoder is constructed, a double-layer GCN and a multi-scale feature fusion module are adopted, and scale adaptive node representation is generated through multi-hop neighborhood aggregation, circuit perception gating and attention fusion; performing hierarchical pooling based on the node depth to construct a hierarchical graph sequence; carrying out embedded coding on the optimized sequence and injecting position information to obtain sequence representation; establishing bidirectional association between a circuit structure and optimization steps through a dynamic graph-sequence adaptive interaction module, and generating a context sensing target sequence; and a Transform decoder is used for carrying out sequence modeling and predicting a quality result track. According to the method, through scale self-adaption and a dynamic interaction mechanism, the problems of representation learning and optimization dynamic modeling of a heterogeneous scale circuit are solved.

The invention discloses a sub-threshold standard cell circuit optimization method, device and equipment, relates to the technical field of digital integrated circuits, and is used for solving the problem that a standard cell circuit is in non-Gaussian distribution in time delay under sub-threshold voltage in the prior art. Comprising the following steps: extracting common parameters of a subthreshold standard unit and analyzing the common parameters to obtain analysis data; selecting a subthreshold standard unit type according to the analysis data and carrying out structural design to obtain a subthreshold standard unit structure; determining a target size corresponding to the subthreshold standard unit structure to obtain a target subthreshold standard unit; and analyzing and optimizing the target sub-threshold standard unit to obtain an optimized sub-threshold standard unit circuit. According to the technical scheme provided by the invention, the problem that in the prior art, the time delay of a standard unit circuit is in non-Gaussian distribution under the subthreshold voltage can be solved. A large-scale circuit is closer to Gaussian distribution, and a guarantee is provided for realizing high-energy-efficiency design of a digital system.

The invention discloses a process corner prediction method and system in static time sequence analysis based on ensemble learning, and the method combines a multilayer perceptron and a graph neural network to carry out process corner prediction, firstly carries out the preliminary prediction through an MLP model, then inputs the prediction result of the MLP into a GNN model, and optimizes the prediction result through graph structure data. And the generative adversarial network is adopted to generate synthetic data, so that the training set is expanded, and the prediction capability of the model is improved. According to the method, the prediction accuracy can be remarkably improved, and the operation speed is more efficient than that of a traditional method. The method not only reduces the calculation overhead of a traditional STA method, but also has good adaptability and high efficiency, and is particularly suitable for process corner prediction tasks of large-scale circuits. The system architecture comprises a data acquisition module, an MLP module, a GNN module and a GAN data generation module, and can realize efficient and accurate process corner prediction in industrial application.

Embodiments herein relate to an interconnect architecture for a multi-transistor stack including channel structures in the form of nanoribbons or nanowires. In one aspect, a metal interconnect is routed between the transistors to provide between electrical connections for control gates and / or source / drain nodes of the transistors. The electrical connections can be provided between transistors in the same stack or in different stacks. In another aspect, control gates of transistors in a stack are independently controlled.

MCU Circuit Implementation Method for Synchronous Control of Large-Scale Discrete Neural Networks, aiming at the problems of difficult synchronous detection of existing neural networks, high FPGA resource occupancy, and insufficient large-scale circuit deployment. First, a large-scale neural network is constructed through chemical synapse coupling, and the stability of the synchronous manifold is analyzed using the master stability function to synchronously regulate the neural network. Then, a hardware circuit is designed based on the AT32 microcontroller. By optimizing DMA data transmission and the 12-bit DAC module, the efficient deployment of high-dimensional networks is completed at low hardware cost. Finally, a 200-dimensional Aihara neural network circuit is successfully implemented and the hardware feasibility is verified, providing a hardware foundation for fields such as brain disease mechanism research, the Internet of Things, and secure communication, and having the potential for engineering applications.

The application discloses a large-scale circuit partitioning method based on artificial intelligence adaptive weight distribution, and belongs to the technical field of integrated circuit computer-aided design, and specifically as follows: first, a graph structure is established to obtain data containing circuit topology characteristics; then, a cubic interpolation method is used to convert the input into a uniform length, improving the generality of the model; a gating mechanism is introduced to establish the structures of input gates, output gates and forget gates, helping the model better perceive the dependency relationship between inputs; the data with circuit topology characteristics obtained through the above processing are trained to obtain a weight distribution model, and the partitioning weight is updated; finally, the large-scale circuit is partitioned by using the updated weight, and multi-index balanced parallel system simulation is realized. The application helps to accelerate the circuit simulation process and improve the parallel benefit.

Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

The invention provides a superconducting integrated circuit and an electronic product. The superconducting integrated circuit comprises a logic chip, a substrate and a bump structure, a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate; wherein the logic chip and the bump structure are arranged on the upper surface of the substrate, and a bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected with the bias network through the bump structure. According to the invention, adverse effects on circuit performance caused by on-chip collection of current are avoided, and the stability of the circuit is improved; the problems that in the prior art, an inductor layout is large in occupied area, and large-scale circuit wiring is difficult are solved.