14 results about "Fall time" patented technology

This invention relates to a keyboard system and a method of operating the keyboard. The keyboard system includes: a key structure comprising a key switch having a light-emitting element and a phototransistor; and one or more processors driving the light-emitting element for a first pulse duration. The output of the phototransistor is determined when the first pulse duration ends, wherein if the output is lower than a first output value when the first pulse duration ends, it is determined that the key structure is pressed, and if the output of the phototransistor is higher than a second output value when the first pulse duration ends, it is determined that the key structure is not pressed. The fall time of the output during the first pulse duration is determined, and if the fall time is less than the first pulse duration, the first pulse duration is calibrated to a second pulse duration, the second pulse duration being greater than the fall time and less than the first pulse duration.

The application relates to the technical field of fault prediction, and specifically discloses a gate loop inductance detection method for fault prediction, which comprises the following steps: collecting voltage signals of a gate drive node in continuous multiple switching cycles, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times that a preset stable high level is greater than in the rising edge Si, and counting the number of times CS in all switching cycles; counting the number of times that a preset stable low level is less than in the falling edge Xi, and counting the number of times CX in all switching cycles; calculating the rising time and the falling time based on the voltage waveform, and averaging the rising slope and the falling slope; calculating the rising index and the falling index; and judging the fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. The application realizes early fault identification and root cause differentiation by counting the gate waveform features of multiple switching cycles, and improves the diagnostic accuracy and the system reliability.

The invention belongs to the technical field of high-speed data testing, and discloses a high-speed signal eye pattern testing method and system based on automatic testing equipment, and the method comprises the steps that a high-speed signal configuration vector is divided into a configuration section and an action section, the configuration section is used for rapidly configuring a testing environment, and the action section is used for controlling a testing action; in the action section, constructing a virtual clock as a reference Trigger signal, and synchronizing the virtual clock and a high-speed signal to be detected to the same sequence group; performing waveform capture on the synchronized high-speed signal to be detected, and generating a two-dimensional array formed by sampling time and level values; the two-dimensional array is processed by a difference peak-valley segmentation method, the eye height, the rising / falling time and the jitter are measured based on a processing result, automatic control, measurement and output of test data can be realized through testing of automatic test equipment, data analysis and processing are facilitated, the test efficiency is improved, and interference of human factors is avoided.

The invention discloses a high-speed channel signal integrity chip evaluation method and system, and the method comprises the steps: generating an excitation signal containing a plurality of frequency components and different amplitudes, and enabling the excitation signal to be used for simulating a complex signal scene in actual high-speed communication; inputting the excitation signal to a transmitting end of a to-be-evaluated signal integrity chip, and obtaining an actual transmitting signal output by the transmitting end of the chip; the actual transmitting signal is analyzed, characteristic parameters of the transmitting signal are obtained, and the characteristic parameters comprise overshoot, undershoot, rise time and fall time of the signal and spectrum distribution of the signal; the transmission process of the signal in different transmission environments is simulated through the transmission line model, the actual transmitting signal is input into the transmission line model to obtain the signal after simulation transmission, and the complex signal scene in actual high-speed communication can be simulated more truly by generating the excitation signal containing multiple frequency components and different amplitudes, so that the signal transmission efficiency is improved. Therefore, the signal integrity chip can be evaluated more comprehensively and accurately.

The invention relates to the technical field of motor control, in particular to a starting method of a single-phase BLDC motor. The method comprises the following steps: acquiring a preset initial rotating speed of a motor, and calculating to obtain a commutation period estimation value of an initial beat; according to the commutation period estimation value of the initial beat and a preset soft switching coefficient, an expected rising time period and an expected falling time period of the initial beat are obtained through calculation; reading a Hall signal of the motor, executing forced commutation according to the current state of the Hall signal, and starting PWM soft modulation according to the expected rising time period of the current beat; in response to the Hall signal change, performing PWM soft modulation according to an expected descent time period of the current beat; in response to an output duty ratio being 0, executing forced commutation according to a current Hall signal state, and calculating a commutation period estimation value, an expected rising time period and an expected falling time period of a next beat; and repeatedly executing the commutation and modulation steps until a preset starting completion condition is met.

Circuits and methods are disclosed for eliminating narrow pulses and compensating for the elimination, and compensating for dead time and non-ideal characteristics in converters, including voltage drops across switches and busbars, pulse distortions caused by delays, unequal rise and fall times, and DC busbar voltage drops. The method can be used for a converter with two complementary switches. A circuit embodiment includes three parts. The first portion calculates a deviation from a reference voltage using a dead time. The second portion includes a controller that adds a compensation value based on a difference between the converter output and the reference voltage. The third section cancels the narrow pulse and compensates for the cancellation by accumulating the difference between the reference signal and the output signal using an integrator, and adds a compensation value using a quantizer without introducing a new narrow pulse. The disclosed system eliminates narrow pulses to reduce loss, extend life, reduce EMI and improve output power quality.

The invention relates to the technical field of fault prediction, and particularly discloses a grid loop inductance detection method for fault prediction, which comprises the following steps of: acquiring voltage signals of a grid driving node in a plurality of continuous switching periods, converting the voltage signals into voltage values, and drawing a voltage waveform according to the voltage values; counting the number of times in the rising edge Si which is greater than a preset stable high level, and counting the number of times CS in all switching periods; counting the number of times smaller than a preset stable low level in the falling edge Xi, and counting the number of times CX in the whole switching period; calculating a rise time and a fall time based on the voltage waveform, and averaging a rise slope and a fall slope; calculating a rising index and a falling index; and determining a fault cause based on the rising index, the falling index, the number of times CS and the number of times CX. According to the invention, by counting the grid waveform characteristics of a plurality of switching periods, early fault identification and root cause distinguishing are realized, and the diagnosis accuracy and the system reliability are improved.

This invention provides a semiconductor device testing method, storage medium, device, and system, comprising at least: initiating detection; setting the detection voltage of an ATE (Automatic Test Equipment) device to low and high levels respectively; testing the semiconductor device; acquiring waveforms of a first signal and a second signal by the ATE device; removing DC components and combining them to obtain a third signal; setting the connection point between the ATE device and the transmission path to an open circuit state; superimposing the waveform of the third signal with the waveform of the signal reflected to the ATE device by the ATE device to obtain a fourth signal; stopping the superposition when the amplitude of the fourth signal waveform reaches a preset full-amplitude value; and outputting the detection result by detecting the rise time and fall time of the fourth signal waveform. The signal waveform conforms to the full-amplitude value, ensuring that the rise time and fall time can be accurately acquired within the same waveform, avoiding distortion, and providing objective and accurate results. The operation is simple, highly practical, and can greatly improve the yield of the device under test.

The present disclosure relates to quadrature (IQ) signal mismatch in RFDACs. IQ mismatch is a non-ideality which occurs whenever I and Q vectors deployed to modulate the phase and the amplitude of RFDAC output signals are not aligned to be offset 90 degrees between each other. IQ mismatch may result in EVM degradation, and may be especially problematic for the RFDAC architecture because the RFDAC operates its digital-to-analog conversion at RF rate. A system may be deployed in the RFDAC to measure and compensate for IQ mismatch. The system may enable full-CMOS digital integration of both the measurement and compensation procedures. The system uses a simple flip-flop structure and exploits the fact that phase-vectors in CMOS logic are eventually digital pulses, and as such the mismatch between I and Q pulses with identical rise-fall time is simply measured as a skewed rise-to-rise and fall-to-fall delay between phases.

A boost circuit is arranged to reduce rise and fall times of pulsed power used for pulsed control operation of electric machines. Magnetic energy present in the electric machine at the end of a pulse is extracted by the boost circuit to reduce the pulse fall time. The energy is stored by the boost circuit and then applied at the beginning of a subsequent pulse to reduce the rise time. By reducing rise and fall times compared to not using such a boost circuit, machine efficiency is improved.

A GIS defect identification method and system based on partial discharge envelope detection signals, a medium and equipment, in the method, the partial discharge UHF signals of the GIS equipment are collected; the UHF signals are envelope detection processed to obtain envelope signals; the envelope signals are denoised by wavelet transform; the peak voltage, the rise time, the fall time, the pulse width and the ratio of the rise time to the fall time are extracted from the denoised envelope signals as characteristic parameters; the support vector machine classifier is used to identify the GIS defect type according to the characteristic parameters, and the defect identification result is output.

A method for compensating settings in a pulsed X-ray system is provided. Current, voltage, and expected pulse width settings are selected for the X-ray pulse to be provided. Then, compensation is performed on the selected pulse width settings for the set voltage and tube current, taking into account the ambient temperature of the electronic circuitry of the X-ray vessel, based on one or more standardized values ​​stored at a predetermined temperature. In a calibration step, a standardized value is obtained based on the actual or effective pulse width and its difference from the expected width, and this value is standardized using the temperature of the circuitry supplying the pulse voltage and current to the source.

The present invention belongs to the technical field of signal rise / fall time correction, and specifically discloses a bit error test device and a signal rise / fall time correction method for the same. The signal rise / fall time correction method comprises: step S1: setting an input clock on a clock source according to the actual desired output signal; step S2: sequentially inputting the input clock in multiple channels into a pattern generator, a slope filter group, and an oscilloscope, wherein the oscilloscope displays and records the data of the rise / fall times of the multiple output signals; and step S3: using an enumeration method to compare the multiple channels of data one by one, determining a result for each channel so that the deviation between the channels is minimized, recording the parameters of the slope filter group corresponding to the minimum deviation, and setting the parameters in the corresponding slope filter group to achieve correction of the output signal rise / fall time. The present invention can solve the problem of difficulty in achieving consistency in signal rise / fall times between multiple transmission channels of a bit error test device.

The invention provides a rise time and fall time measuring method and device, a medium and equipment, and relates to the technical field of chip testing. According to the technical scheme provided by the invention, a high-precision time measurement problem is converted into a digital scanning problem with controllable delay amount, so that the dependence of related technologies on expensive equipment such as a high-speed sampling rate analog-to-digital converter and a high-bandwidth oscilloscope is avoided; accurate measurement can be achieved only through low-cost digital devices such as a comparator, a programmable delay circuit and a trigger, and therefore the test cost is remarkably reduced on the premise that the chip test precision is met.