4 results about "Error reduction" patented technology

This application relates to a method, electronic device, and storage medium for locating errors in a logic system design. The method includes: testing the logic system design using multiple test cases; dividing the multiple test cases into a pass case group and a fail case group based on the test results, the test results including coverage data of the multiple test cases; determining multiple key features based at least on the coverage data of the test cases in the fail case group; and locating the error in the logic system design based on the multiple key features. This method can reduce error location time and accurately pinpoint the source of errors in the logic system design.

Methods, systems, and devices for error reduction techniques for memory systems are described. A memory system may perform a first dummy read operation on a block of memory cells. The memory cells of the block may transition to a first state in accordance with performing the first dummy read operation. The memory system may determine whether a threshold is satisfied in response to performing the first dummy read operation, and the threshold may include a duration after performing the first dummy read operation that the memory cells remain in the first state. The memory system may perform a second dummy read operation on a first page of the block of memory cells in response to determining that the threshold is satisfied, and the memory cells remain in the first state in accordance with performing the second dummy read operation.

This invention discloses an artificial intelligence-based knowledge graph question-answering interaction method and system, belonging to the field of knowledge graph technology. It includes four steps: temporal knowledge validity screening, reasoning path quality assessment, causal attribute consistency verification, and reliable result output and closed-loop optimization. After receiving a user's natural language query, the system first extracts the query time interval, filters valid triples matching the time dimension in the knowledge graph, calculates the path time matching degree and candidate answer attribute matching degree based on the valid triples, and then calculates the credibility after fusion before outputting the qualified answer. This invention integrates multiple technologies, using dual verification to ensure the accuracy of the answer in terms of temporality and logic, reducing errors. The system continuously learns and improves based on application feedback, enhancing the accuracy of the knowledge graph and the quality of question answering. Furthermore, the data interaction between modules is standardized and logically clear, enabling flexible responses to various queries and providing users with traceable, high-quality answers to meet diverse needs.

The invention relates to a method for determining an error-corrected expectation value of an observable of a quantum system using a classical computer, comprising the following steps: • Providing a first expected value of an observable, which depends on a first distance measure, where the first distance measure specifies a spatial separation between a first qubit group and a second qubit group; • Providing at least one second expected value of the observable, which depends on a second distance measure; • Determining a customized fit function using the following steps: ◯ Provide a fit function that includes at least one fit parameter and depends on the distance measure; ◯ Adjusting the fit parameters of the fit function to the first expected value and the second expected value; • Determining an error-corrected expected value of the observable by evaluating the fitted function for the case where the distance measure takes on a value greater than the first distance measure and the second distance measure; • Providing the error-corrected expected value.