7results about "Delay lines pulse generation" patented technology

Embodiments provide a semiconductor integrated circuit, a semiconductor memory device, and a storage system capable of improving the measurement resolution of a pulse signal while suppressing the area and the consumed current. A semiconductor integrated circuit of one embodiment has an array circuit (52) of delay elements in which a plurality of delay elements each having a delay amount (Tw) are connected in series, a delay line group (530) having flip-flops (53β) of outputs of the delay elements corresponding to a plurality of inputs, a delay element group (540) that generates a plurality of output clock signals having a delay difference of a second delay amount smaller than the delay amount (Tw) from an input clock signal, and a delay section (55) capable of setting a third delay amount smaller than the second delay amount, the delay element group (540) and the delay section (55) being connected in series between an output terminal of an input signal (CLK_DET) and an input terminal of the delay line group (530).

A method of forming a semiconductor device includes forming a first row of transistors extending in a first direction and including dummy transistors and active transistors. The first row includes, in a sequence from a first end to a second end, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group. The first dummy group is formed of one or more dummy transistors. The second dummy group is formed of one or more dummy transistors. The first delay cell is formed of active transistors configured as a basic inverter and a float-resistant inverter. The second delay cell is formed of active transistors configured as at least one inverter. The first row is free of dummy transistors between the first delay cell and the second delay cell.

A pulse-rate multiplication system (20, 54) includes a pulse generator (24) and a delay line (32). The pulse generator is configured to generate a sequence of input pulses having a pulse duration and a Pulse Repetition Interval (PRI). The delay line includes an array of equally spaced reflectors (36), adjacent ones of the reflectors having a roundtrip time (RTT) therebetween. The delay line is configured to output a reflected signal including a sequence of output pulses whose rate is multiplied relative to the sequence of input pulses. M denotes a ratio between the RTT and the pulse duration, N denotes a number of the reflectors in the array, and M and N are set to be co-prime.

The invention provides a method of generating a burst of gigahertz laser pulses, wherein: 1) a time delay T2 of a delay section with respect to an undelayed portion of an input pulse is greater than a time period T1 between the input pulse and a next input pulse; 2) the burst of output pulses has an increasing number of pulses; 3) a burst-internal pulse spacing within the formed burst is equal to T3 = T2 - T1 and corresponds to an ultrahigh pulse repetition rate higher than 100 MHz. In another embodiment: 1) T2 is longer than M*T1, where M = 2, 3, etc.; 2) an output series of bursts consists of bursts of pulses, where M adjacent bursts have the same number of pulses; 3) T3 is equal to T3 = T2 - M*T1. A laser device for implementing the method is provided.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

The embodiment of the present application discloses a signal generation circuit. The circuit comprises a delay-locked loop module, a counting unit, a comparison unit, a first voltage-controlled delay line, a second voltage-controlled delay line, a gating unit and an output logic unit. The delay-locked loop module generates a control voltage according to a reference clock signal, which is used to adjust the delay amount of the first voltage-controlled delay line and the second voltage-controlled delay line; the comparison unit is used to output a period trigger signal and a duty cycle trigger signal; the gating unit selects the corresponding delay output according to the low bit value of the period control value and the duty cycle control value; the upper limit value of the counting unit and the duty cycle control value are dynamically adjusted according to whether the accumulated delay amount reaches a preset threshold. In the above manner, the embodiment of the present application can ensure stable performance of the delay line, reduce the maximum delay amount required by the delay line, reduce the chip area overhead, and realize generation of a pulse width modulation signal with adjustable duty cycle and adjustable period and high precision.

A semiconductor device and its manufacturing process are provided that are capable of designing the intended delay with high precision in just a few steps.The semiconductor device fabrication method disclosed herein arranges several circuits on one plane and connects a wiring system to each, comprising: a placement step of arranging a digital circuit operating on the basis of timing signals and a delay circuit configured with several delay paths having different input / output delay amounts, wherein one of the several delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay setting step of selecting one of the several delay paths by connecting a predetermined voltage as the selection signal and selecting the delay amount so that the input / output timing of the digital circuit satisfies predetermined conditions.