16results about "Delay lines pulse generation" patented technology

An electronic device and a method of operating the same are provided. The electronic device comprises a power-up circuit, a delay circuit and a plurality of power supply circuits. The power-up circuit is configured to control a power-up signal in accordance with a power supply voltage. The delay circuit is configured to provide a plurality of enable signals by delaying the power-up signal by different delay times. The plurality of power supply circuits are configured to be enabled by the plurality of enable signals, respectively.

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

Embodiments provide a semiconductor integrated circuit, a semiconductor memory device, and a storage system capable of improving the measurement resolution of a pulse signal while suppressing the area and the consumed current. A semiconductor integrated circuit of one embodiment has an array circuit (52) of delay elements in which a plurality of delay elements each having a delay amount (Tw) are connected in series, a delay line group (530) having flip-flops (53β) of outputs of the delay elements corresponding to a plurality of inputs, a delay element group (540) that generates a plurality of output clock signals having a delay difference of a second delay amount smaller than the delay amount (Tw) from an input clock signal, and a delay section (55) capable of setting a third delay amount smaller than the second delay amount, the delay element group (540) and the delay section (55) being connected in series between an output terminal of an input signal (CLK_DET) and an input terminal of the delay line group (530).

The present invention discloses a method for generating a pulse signal, a pulse generating device, and a partial discharge measurement system, which relates to the technical field of signal generating devices, and solves the problems of relatively low pulse peak values of existing pulse generators and relatively large rise times of output pulses. The main technical solution is as follows: An AC signal source is obtained; the AC signal source is subjected to two-stage in-phase signal amplification processing to obtain an AC electrical signal; the AC electrical signal is successively subjected to rectification, voltage reduction, and delay processing to generate a pulse signal. The present invention performs signal amplification processing on the AC signal source to reduce the relative influence of external interference, obtains an AC electrical signal, and based on the subsequent rectification, voltage reduction, and delay processing, which play the roles of edge sharpening of the AC electrical signal, allowing the generation of narrow pulses to maximize the signal bandwidth, and reducing ringing, so that when the rise time of the pulse front decreases, the overshoot pulse peak value increases.

An electronic device and an operating method thereof are provided. The electronic device comprises a power up circuit, a delay circuit, and a plurality of power supply circuits. The power up circuit is configured to control a power up signal according to a power voltage. The delay circuit is configured to provide a plurality of enable signals by delaying the power up signal with different delay times. The plurality of power supply circuits are configured to be respectively activated by the plurality of enable signals.

The invention provides a pulse generation method and system, electronic equipment and a storage medium, and relates to the technical field of pulse generation, through a mode of combining a digital phase-locked loop and analog delay control, the pulse generation system realizes fine pulse width regulation and control while maintaining high frequency stability, and the pulse generation efficiency is improved. And the accuracy of digital logic and the flexibility of analog regulation and control are both considered. Moreover, a high-quality differential square wave signal is generated through an amplitude limiting amplifier, and then fine phase difference regulation and control are realized in combination with a time delay module, so that a target pulse signal with narrow pulse width, fast edge and accurate pulse width is generated. The digital phase-locked loop and the delay module are controlled by the controller, so that the pulse width can be flexibly adjusted, the pulse period can be controlled, and diversified requirements of different application scenes on pulse parameters can be met. The introduction of the feedback processing module can provide real-time monitoring and correction functions for the controller, and effectively counteracts the influence caused by environment change and drift of each component in the pulse generation system.

A method of forming a semiconductor device includes forming a first row of transistors extending in a first direction and including dummy transistors and active transistors. The first row includes, in a sequence from a first end to a second end, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group. The first dummy group is formed of one or more dummy transistors. The second dummy group is formed of one or more dummy transistors. The first delay cell is formed of active transistors configured as a basic inverter and a float-resistant inverter. The second delay cell is formed of active transistors configured as at least one inverter. The first row is free of dummy transistors between the first delay cell and the second delay cell.

A pulse-rate multiplication system (20, 54) includes a pulse generator (24) and a delay line (32). The pulse generator is configured to generate a sequence of input pulses having a pulse duration and a Pulse Repetition Interval (PRI). The delay line includes an array of equally spaced reflectors (36), adjacent ones of the reflectors having a roundtrip time (RTT) therebetween. The delay line is configured to output a reflected signal including a sequence of output pulses whose rate is multiplied relative to the sequence of input pulses. M denotes a ratio between the RTT and the pulse duration, N denotes a number of the reflectors in the array, and M and N are set to be co-prime.

A delay chain comprises: delay stages connected in series, each delay stage comprising a driver device connected between an input node and an output node of the delay stage, and a capacitive digital-to-analog converter (CDAC) connected to the output node of the delay stage, wherein at least one of the CDACs is a separately adjustable (SA) CDAC (SA_CDAC) that is separately adjustable with respect to at least one other of the CDACs; and a controller configured to adjust the at least one CDAC.

The invention provides a method of generating a burst of gigahertz laser pulses, wherein: 1) a time delay T2 of a delay section with respect to an undelayed portion of an input pulse is greater than a time period T1 between the input pulse and a next input pulse; 2) the burst of output pulses has an increasing number of pulses; 3) a burst-internal pulse spacing within the formed burst is equal to T3 = T2 - T1 and corresponds to an ultrahigh pulse repetition rate higher than 100 MHz. In another embodiment: 1) T2 is longer than M*T1, where M = 2, 3, etc.; 2) an output series of bursts consists of bursts of pulses, where M adjacent bursts have the same number of pulses; 3) T3 is equal to T3 = T2 - M*T1. A laser device for implementing the method is provided.

To provide a ring oscillator-based Ising machine system.SOLUTION: One example includes an Ising machine system. The system includes a plurality of ring oscillators that are each configured to propagate an oscillation signal. Each of the ring oscillators can be cross-coupled with at least one other of the ring oscillators via a respective one of the oscillation signals to provide a respective phase coupling between the respective cross-coupled ring oscillators. The system also includes an Ising machine controller configured to generate control signals corresponding to parameters of an Ising problem and including a plurality of delay selection signals. The Ising machine controller can provide at least one of the delay selection signals to each of the ring oscillators. The delay selection signal can be configured to set a variable propagation delay of the ring oscillator to control the relative phase coupling of each of the ring oscillators to each of the at least one other of the ring oscillators.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

The embodiment of the present application discloses a signal generation circuit. The circuit comprises a delay-locked loop module, a counting unit, a comparison unit, a first voltage-controlled delay line, a second voltage-controlled delay line, a gating unit and an output logic unit. The delay-locked loop module generates a control voltage according to a reference clock signal, which is used to adjust the delay amount of the first voltage-controlled delay line and the second voltage-controlled delay line; the comparison unit is used to output a period trigger signal and a duty cycle trigger signal; the gating unit selects the corresponding delay output according to the low bit value of the period control value and the duty cycle control value; the upper limit value of the counting unit and the duty cycle control value are dynamically adjusted according to whether the accumulated delay amount reaches a preset threshold. In the above manner, the embodiment of the present application can ensure stable performance of the delay line, reduce the maximum delay amount required by the delay line, reduce the chip area overhead, and realize generation of a pulse width modulation signal with adjustable duty cycle and adjustable period and high precision.

A method for generating gigahertz bursts of laser pulses is provided, where: 1) time delay T2 of the delayed part with respect to the undelayed part of the input pulse is longer than a time period T1 between said input pulse and the next input pulse; 2) the bursts of output pulses have an incrementally increasing number of pulses; 3) intra-burst pulse separation inside the formed bursts is equal to T3=T2−T1 and corresponds to an ultra-high pulse repetition rate higher than 100 MHz. In another embodiment: 1) T2 is longer than M*T1, where M=2, 3, etc.; 2) output train of bursts is composed of bursts of pulses wherein M adjacent bursts have identical number of pulses; 3) T3 is equal to T3=T2−M*T1. The laser apparatus for implementing the method is provided.

A semiconductor device and its manufacturing process are provided that are capable of designing the intended delay with high precision in just a few steps.The semiconductor device fabrication method disclosed herein arranges several circuits on one plane and connects a wiring system to each, comprising: a placement step of arranging a digital circuit operating on the basis of timing signals and a delay circuit configured with several delay paths having different input / output delay amounts, wherein one of the several delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay setting step of selecting one of the several delay paths by connecting a predetermined voltage as the selection signal and selecting the delay amount so that the input / output timing of the digital circuit satisfies predetermined conditions.

An embodiment of a timing-based signal valley detection technique improves efficiency and reduces electromagnetic emissions due to ringing by controlling the off-time of a power switch in an LED driver or power converter application. The timing-based technique estimates a time of occurrence of a valley in the drain voltage of the power switch. The timing-based technique uses an analog comparator to sense the drain voltage of a power switch. The timing-based technique uses digital circuits to estimate the time of occurrence of the valley in the drain voltage and to adjust the duty cycle (e.g., adjusts the off-time by terminating the off-time) of a gate control signal of the power switch. The technique may use off-chip resistive voltage divider circuits to sense the drain voltage of the power switch and to generate a reference voltage and other circuits are integrated in an integrated circuit device.