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Semiconductor device

A semiconductor and signal technology, applied in signal transmission systems, instruments, analog-to-digital converters, etc., can solve the problems of large clock signal cycle, peripheral circuits cannot follow the internal clock, and cannot perform comparison operations, etc., to achieve the effect of accurate cycle

Active Publication Date: 2015-02-11
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the delay time is too large, the period of the internal clock signal becomes too large, and therefore, a desired number of comparison

Method used

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  • Semiconductor device
  • Semiconductor device
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Examples

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Comparison scheme
Effect test

no. 1 example

[0040] Such as figure 1 As shown, the wireless communication semiconductor device 1 according to the first embodiment of the present application includes an oscillator 2, a receiving system analog circuit 3, a transmission system analog circuit 4, an A / D interface circuit (ADI) 5, an RF (radio frequency) core 6 and CPU (Central Processing Unit) 7 . The oscillator 2 generates an oscillation signal having a predetermined frequency, and supplies the oscillation signal to the receiving system analog circuit 3 .

[0041] The reception system analog circuit 3 includes an LNA (Low Noise Amplifier) ​​10, a mixer 11, a BPF (Band Pass Filter) 12, ADCs (Analog to Digital Converters) 13 and 14, and a VCO (Voltage Controlled Oscillator) 15 and 16. The transmission system analog circuit 4 includes DACs (Digital to Analog Converters) 17 and 18 , an LPF (Low Pass Filter) 19 , a mixer 20 and a power amplifier 21 .

[0042] VCO 15 generates a local oscillation signal based on the oscillatio...

no. 2 example

[0136] Figure 16 is a circuit block diagram showing the configuration of the ADC according to the second embodiment of the present application, and is to be used with image 3 Schematic for comparison. exist Figure 16 In this ADC, the addition / subtraction circuit 31 is composed of a combinational logic circuit 85 , and the timing detection circuit 32 is composed of a flip-flop 90 . The combinational logic circuit 85 includes inverters 86 and 87 , an AND gate 88 and an OR gate 89 .

[0137] The delay control signal DCNT is a one-bit signal, and is supplied to the asynchronous successive approximation ADC 25 and one input node of the AND gate 88 . The output signal F2 of the delay circuit 30 is inverted by the inverter 86 and supplied to the other input node of the AND gate 88 . An output signal of the AND gate 88 is supplied to one input node of the OR gate 89 . The signal F1 is inverted by the inverter 87 and supplied to the other input node of the OR gate 89 . The out...

no. 3 example

[0144] Figure 17is a circuit block diagram showing the configuration of the ADC according to the third embodiment of the present application, and is to be used with image 3 Schematic for comparison. exist Figure 17 , the ADC with image 3 The ADC 13 is different in that the addition / subtraction circuit 31 and the timing detection circuit 32 are replaced by an addition / subtraction circuit 91 and a timing detection circuit 92, respectively. The bit width of the delay control signal DCNT is 4 bits.

[0145] The addition / subtraction circuit 91 generates the delay control signal DCNTN used in the next comparison period based on the delay control signal DCNT determined in the previous comparison period, and the logic levels of the signals F1 and F2. Here, each of the delay control signals DCNT and DCNTN is a thermometer code.

[0146] The thermometer code is a code expressed in a bit sequence of binary notation, and it changes sequentially from 0 to 1 from the smallest bit e...

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Abstract

To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Description

[0001] Cross References to Related Applications [0002] The entire disclosure of the publication of Japanese Patent Application No. 2013-164053 filed on Aug. 7, 2013 including specification, drawings and abstract is incorporated herein by reference. technical field [0003] The present invention relates to a semiconductor device, and is suitably used for, for example, a semiconductor device including an asynchronous successive approximation type A / D (analog / digital) converter. Background technique [0004] A synchronous successive approximation A / D converter can be implemented with a relatively simple circuit configuration, but requires a clock signal that oscillates multiple times during A / D conversion. However, in a high-speed system chip, a clock signal having a frequency several to several tens of times the frequency of the system clock signal is rarely obtained. [0005] Therefore, there has been proposed an asynchronous successive approximation type A / D converter whi...

Claims

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Application Information

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IPC IPC(8): H03M1/38
CPCH03M1/38H03K3/86H03M1/125H03K5/133H03K2005/00065H03M1/12H03M1/46H03M1/462H03M1/468
Inventor 藤原正树森木康夫松本阳史
Owner RENESAS ELECTRONICS CORP
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