34 results about "Delayed pulse" patented technology

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

Waveform characteristics of pulses in a pulse train configured to cause pulsed field tissue ablation may be varied in a manner that improves electromagnetic compatibility while retaining treatment efficacy. Such waveform characteristics may include pulse-to-pulse initiation intervals, inter-pulse delays, pulse on-times, pulse widths, inter-phase delays in the case of biphasic pulses, or a combination thereof. Such waveform characteristics may be varied in a random manner. Variations of waveform characteristics may be bounded by minimum, maximum, or both minimum and maximum differences between various pulses or pulse groups, or between various pulse trains or pulse train groups, for example, to help ensure sufficient stability of treatment signal waveforms while allowing sufficient variability, for example, to improve electromagnetic compatibility.

To provide a pulse width measuring circuit with which a measurement time is shortened.SOLUTION: A first programmable delay circuit 130 and a second programmable delay circuit 140 respectively delay a first pulse S1 and a second pulse S2 corresponding to an input pulse SIN and generate a first delay pulse Sd1 and a second delay pulse Sd2. A latch circuit 150 latches the first delay pulse Sd1 in response to an edge of the second delay pulse Sd2. A controller 160 continuously sweeps a delay amount τ2 of the second programmable delay circuit 140 in first processing, and detects a first delay mount τP when the output Q of the latch circuit 150 changes. In second processing, the delay amount τ2 of the second programmable delay circuit 140 is changed by a binary search and a second delay amount τn is detected when the output Q of the latch circuit 150 changes. The difference between the first delay amount τP and the second delay amount τn is made a pulse width Tp of the input pulse SIN.SELECTED DRAWING: Figure 1

The invention provides an experimental simulation system of an equivalent wind shear wind field. According to the system, pulse light signals emitted by a wind measurement laser radar are simulated through different delay optical fibers to reach atmospheric stratification at different positions, then delayed pulse light is emitted to different positions of the side face of a rotating disc rotating at a constant speed, and echo signals obtain Doppler frequency shifts of different sizes due to different radial speeds; based on this, the change of wind speed in wind shear is simulated. A required equivalent wind shear wind field can be customized by adjusting the length of the delay optical fiber, the diameter of the turntable and the incident position of light on the side surface of the turntable. The system is simple in structure and low in cost, and can provide an equivalent wind shear wind field with accurate and controllable wind speed and abundant changes.

The present invention relates to the field of spatial fault tolerance technology, and in particular to a reliability design method for a multi-dimensional COTS device intelligent computing system. The method includes: setting a corresponding fault detection and recovery module inside the intelligent computing module and each external interface module, and setting a long-delay system-level watchdog connected to the intelligent computing module and the external interface module respectively; the long-delay system-level watchdog includes a latching arbitration circuit and a multi-channel long-delay pulse generator, the latching arbitration circuit is used to receive the clear signal sent by the intelligent computing module and N external interface modules, and clear the timing of each long-delay pulse generator after latching and arbitration. If the timing exceeds the first set delay, a first reset signal is output to reset and restart the corresponding intelligent computing module or external interface module. This solution adopts a two-level reliability design, which can save space and computing resources compared to the backup design.

The application discloses a signal sampling method, device and equipment of digital PET, and a storage medium. The signal sampling method of the application comprises the following steps: performing delay processing on pulse signals input to multiple channels, and obtaining multiple delay pulse signals; switching the multiple channels based on the multiple delay pulse signals, and obtaining comparison signals; and performing time-to-digital conversion processing on the comparison signals to extract time information. According to the scheme of the embodiment of the application, the multiplexing of time-to-digital converters among multiple channels can be realized in the FPGA, information loss is not caused, the resource usage of the FPGA is reduced, and the time measurement precision and system integration are improved.

The present inventive concept provides a capacitance sensor array chip with programmable fusion pixels comprising: a programmable module for generating a choosing signal according to a first clock signal; a delay pulse module for generating a third clock signal according to a second clock signal and a sensing pulse signal; and multiple electrode array modules comprising a charging unit for generating a charging signal according to the sensing pulse signal; M×N electrode pixel units forming an array, wherein the electrode arrays chooses a certain pattern of the electrode units according to the choosing signal in orders and the certain pattern of the electrode units in the electrode array generates a sampling signal according to the charging signal; and a sampling unit for generating a sensing output signal according to the sampling signal and the third clock signal.

The invention relates to an inter-pulse double-path delay accurate modulation interference method and device based on SAR-GMTI, belongs to the technical field of radar signal processing interference, and solves the problem that in the prior art, false targets with high-degree-of-freedom position distribution cannot be generated in an interference weakening area. The method comprises the following specific steps: a ground jammer receives a signal transmitted by an aerial radar to obtain a received signal; the ground jammer performs interference enhancement region complementary modulation on the received signal to obtain a first interference signal; wherein the first interference signal is formed by superposing a path of echo signal in a direct forwarding form and a path of echo signal forwarded by delaying n pulses; doppler modulation is carried out on the first interference signal to compensate position lag of delay pulse forwarding, and a second interference signal is obtained; and two-dimensional frequency modulation is carried out on the second interference signal, and an obtained final interference signal is transmitted back to the aerial radar, so that the multichannel SAR-GMTI deception interference with high degree of freedom not being canceled is realized.

The present invention is applicable to the field of analog-to-digital conversion and provides a high-speed two-step time-domain analog-to-digital converter, comprising: a common-mode voltage conversion unit for converting a differential voltage signal into first and second time pulse signals; a conversion and selection unit for sequentially delaying and encoding the first and second time pulse signals to obtain a first code, and selecting and outputting a first signal and a second signal from the first and second time pulse signals and the multiple delayed pulse signals obtained by the delay processing; a one-step multi-bit successive approximation analog-to-digital conversion unit for continuously quantizing and encoding the first and second signals, outputting a second code, and extending or shortening the transmission time of the first and / or second signals based on the second code; and a quantization coding unit for obtaining a target quantization code using the first and second codes. The solution provided by the present invention can effectively shorten quantization time, improve quantization efficiency, and improve quantization accuracy.

A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.

The application provides a time coding compressed sensing imaging method and device based on FPGA and electronic equipment, the method is applied to the technical field of photoelectric detection and computational imaging, and the method comprises the steps of: calibrating an FPGA delay unit based on a reference clock, constructing a delay lookup table and writing a time coding sequence of random coding and a push-scan mode. In response to a synchronization signal, coarse and fine delay tap values are analyzed, a reference pulse is generated and is synchronized to the reference clock, a delay pulse is generated through fine delay, three alignment timing control signals are generated, and the excitation gate and exposure signals are cooperatively controlled. Discrete integral observation values are collected in an exposure window, a continuous observation operator is constructed in combination with the delay lookup table, a target function is constructed based on physical priori, and the target function is iteratively solved to obtain a high signal-to-noise ratio, a transient response curve and physical parameters. The method can solve the problems of slow sampling speed and lack of software flexibility due to dependence on modulation devices in traditional hyperspectral imaging technology.

Provided is a pulse generation circuit that receives a clock signal and outputs a delayed pulse signal, including: a first delay-locked loop circuit that receives the clock signal and generates a first delay signal obtained by delaying the clock signal; a second delay-locked loop circuit that generates a second delay signal with reference to the first delay signal; and an output circuit that outputs the delayed pulse signal according to the first delay signal and the second delay signal. The second delay-locked loop circuit may have: a second charge pump that outputs a current according to the clock signal and the delayed pulse signal; and a second delay circuit that outputs the second delay signal obtained by delaying the clock signal according to a current output by the second charge pump.

An optical pulse generator arranged to generate an initial sequence of optical pulses having an initial inter-pulse period; and an optical pulse burst formation apparatus including: an interleaving stage to receive an initial sequence of optical pulses having an initial inter-pulse period, including: an optical splitter to power split received optical pulses, thereby generating a first and second replica sequences of optical pulses; a first optical arm to receive the first replica sequence, having a first optical path length; and a second optical arm to receive the second replica sequence, having a second optical path length, different to the first optical path length by a path length difference; and an optical combiner arranged to combine the first replica sequence of pulses and the second replica sequence of delayed pulses to form an output sequence of optical pulse bursts.

This invention discloses a multi-delay mode delay pulse generation circuit, including a signal input unit, a signal processing unit, a pulse generation unit, and a pulse output unit. In the signal input unit, a logic processing circuit receives a level combination signal and a control pulse signal, and multiple signal output circuits are configured according to their combination. Each signal output circuit is connected to a delay selection circuit. In each delay selection circuit, a delay control signal is used to control the state of the delay selection switch, so that the signal delay processing circuit processes the signal output from the signal output circuit into a pulse signal DLY with a corresponding delay, which is then sent to the pulse generation unit. The pulse generation unit generates a detonation pulse based on the pulse signals DLY output from the multiple delay selection circuits. The pulse output unit outputs the detonation pulse to the detonation driving device. This invention enables the selection and setting of the delay of the driving pulse to provide pulse signals with different delays as needed, achieving precise control of the load switching time.

The present disclosure relates to a pipeline clock driving circuit, a computing chip, a computing power board and a computing device. A pipeline clock driving circuit is disclosed for providing a pulse clock signal for a pipeline, comprising: a plurality of stages of clock driving circuits, each stage for providing a pulse clock signal for a corresponding operation stage of the pipeline; a clock source coupled to an input of a first stage of the clock driving circuits, each stage of the clock driving circuits comprising: a flip-flop coupled to an input of the stage of the clock driving circuits; a delay module comprising a first delay submodule for delaying a pulse signal output by the flip-flop and feeding back the delayed pulse signal to the flip-flop as a feedback pulse signal; and a combinational logic module for performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal for providing to the corresponding operation stage, wherein the delay module further comprises a second delay submodule for delaying the pulse signal and outputting the delayed pulse signal to a next stage of the clock driving circuits.

A dynamic torsion-tension / compression synchronous combined loading device and loading method, through a delay pulse generator, a torsional wave and a tensile / compressive wave are simultaneously arrived at a sample, and finally a torsion, a tensile / compressive composite dynamic loading is realized. In the application, energy is stored through a rotating torque loading mechanism, and the size of the energy is obtained in real time through a strain flower pasted on a torsional incident rod. After the energy storage is completed, the clamping bolt of the rotating clamping mechanism is clamped to make the broken bolt be broken under tension, so that the energy stored in the energy storage section of the torsional incident rod is transmitted to the sample in the form of a stress wave, the strain flower located on the torsional incident rod can record the waveform of the torsional wave, and the sample is dynamically torsionally loaded when the torsional wave reaches the sample. Through accurate control of the delay time, the torsional wave and the tensile wave can be simultaneously arrived at the sample, and the dynamic tensile-torsion composite loading of the sample is realized. A data collector simultaneously records the stress wave pulse signals on the torsional incident rod and the tensile incident rod.

The invention relates to the technical field of fault detection, in particular to a discharge fault positioning system, a discharge fault positioning method, discharge fault positioning equipment and a medium, and the discharge fault positioning system comprises a laser, a first acoustic optical modulator, a second acoustic optical modulator, an optical amplifier, a balanced photoelectric detector and an acquisition card. One part of the first pulse sequence is delayed to obtain a delayed pulse sequence, the remaining first pulse sequence is modulated to obtain a second pulse sequence, the two parts of pulse sequences are amplified and then injected into the sensing optical fiber to obtain a target signal, and the sensing optical fiber is arranged on the outer surface of the GIL pipeline to be detected and converts the target signal into a voltage signal; and carrying out discharge fault positioning according to the voltage signal. Therefore, the problems that the GIL discharge fault positioning technology is high in cost and low in reliability, and long-distance GIL discharge fault positioning is difficult to achieve are solved, and the GIL discharge fault positioning method can cover the length of several kilometers and is easy to install, accurate in positioning and high in reliability.

A control signal generation circuit 5 according to one embodiment comprises: an insulated gate driver that is configured to output a control pulse signal corresponding to a common input pulse signal to first and second switching elements; a delay signal generation unit that is configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit that is configured to generate first and second control pulse signals by performing different logic synthesis on two signal sets among a plurality of signal sets that are defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.

The present disclosure relates to a minimum pulse width violation repair circuit and a minimum pulse width violation repair method. The circuit comprises a pulse delay module that delays the generation time of a pulse input signal transition edge that causes a minimum pulse width violation to obtain a delayed pulse signal; and a widening module that obtains a widened pulse signal that meets pulse design rules according to the pulse input signal and the delayed pulse signal. The technical solution of the present disclosure can eliminate the pulse width violation of the pulse signal that causes the minimum pulse width violation. The circuit of the present disclosure has a simple structure, is easy to implement, and has a good effect of improving the minimum pulse width violation. The data model of the circuit of the present disclosure can be stored in advance and called during the repair of the minimum pulse width violation. A plurality of circuits of the present disclosure can be connected in series to further enhance the repair effect of the minimum pulse width violation and finally completely repair the minimum pulse width violation.

The application provides an imaging interpolation calibration method and system based on a delay pulse number, a medium and equipment, and mainly solves the imaging frame loss problem caused by interrupted transmission during the interpolation calibration of a spaceborne SAR imaging. The implementation steps of the application are as follows: (1) reading a delay pulse number N and an interpolation calibration cycle number M; (2) constructing an interpolation calibration small cycle based on the delay pulse number and constructing an interpolation calibration large cycle based on the interpolation calibration cycle number; and (3) generating a calibration signal. The application can solve the imaging pulse interruption problem caused by the imaging interpolation calibration to a certain extent, and effectively guarantee the ground observation performance of the SAR system.

This invention discloses a pulse density modulation full-bridge converter capable of eliminating inter-frequency harmonics, belonging to the field of power electronic control technology. The pulse density modulator provided by this invention includes an adder for adding a pulse density command signal and a feedback signal to obtain a signal to be quantized, x. A quantizer quantizes the signal to be quantized, x, to obtain a pulse signal, a. A register delays pulse signal a by half a switching cycle to generate a pulse signal, b. Pulse signals a and b are input into an XOR gate and then subtracted from the signal to be quantized, x, to obtain a quantization error, e. The quantization error, e, is then filtered by a digital filter to obtain a feedback signal. Pulse signals a and b control the switching state of the full-bridge converter. This invention can be applied to various resonant converters, controlling the converter's output voltage or power through pulse density modulation; it can eliminate inter-frequency harmonics based on the resonant network, avoiding oscillation and ensuring stable converter operation.

To enable measurement of optical excitation dynamics only by adding a light source unit to an existing atomic force microscope (AFM).SOLUTION: A measuring system comprises: a cantilever; an AFM controller 43 that outputs a change amount signal that is voltage or current according to a change in the resonance frequency or amplitude of the cantilever; and a light source unit. The light source unit includes: a pump light generation section 22 that outputs pump light in response to a reference pulse P1 that is input thereto; a probe light generation section 23 that outputs probe light in response to a delay pulse P2 that is input thereto; and a trigger generator and delay time controller that inputs the reference pulse P1 and the delay pulse P2 to the pump light generation section 22 and the probe light generation section 23 and repeatedly inputs signals while switching a delay time td in multiple ways, and outputs a reference signal to a lock-in amplifier 25 in switching the delay time td.SELECTED DRAWING: Figure 1

To provide a delayed pulse generating circuit that is capable of keeping delay constant regardless of the cycle (frequency) of a clock signal.SOLUTION: A delayed pulse generating circuit 10 to which a clock signal CKREF is input and from which a delay pulse signal is output, includes: a delay circuit 300 to which a clock signal and a delayed pulse signal are input, and which generates a delayed signal by delaying the clock signal based on a first control signal, which changes to one logic when the clock signal has changed to a first logic and changes to the other logic when the delay pulse signal has changed to the first logic, and a second control signal, which changes to one logic when the delayed pulse signal has changed to the first logic and changes to the other logic when the delayed pulse signal has changed to a second logic; and a driver 500 which outputs a delayed pulse signal OUT according to the delay signal.SELECTED DRAWING: Figure 1

The present application relates to the technical field of fault detection, and particularly relates to a discharge fault positioning system, a discharge fault positioning method, equipment and a medium, wherein the discharge fault positioning system comprises a laser, a first / second acousto-optic modulator, an optical amplifier, a balanced photodetector and a collection card; the laser is split after being modulated into a first pulse sequence; a part of the first pulse sequence is delayed to obtain a delayed pulse sequence; the remaining first pulse sequence is modulated to obtain a second pulse sequence; the two pulse sequences are amplified and then injected into a sensing optical fiber to obtain a target signal; the sensing optical fiber is arranged on the outer surface of a GIL pipeline to be detected, and the target signal is converted into a voltage signal; and the discharge fault is positioned according to the voltage signal. Thus, the problem that the GIL discharge fault positioning technology has high cost, low reliability and is difficult to realize long-distance GIL discharge fault positioning is solved; the present application can cover a length of several kilometers, is easy to install, has accurate positioning and high reliability.

This application proposes a signal delay control method and system based on a carry4 delay chain. The method includes: configuring a target delay time and dividing the target delay time into a coarse delay and a fine delay; using a clock counter based on the FPGA system clock to count and output the coarse delay, obtaining a coarse delay pulse signal; inputting the coarse delay pulse signal into a delay chain combination composed of multiple cascaded carry4 units within the FPGA, and using the delay chain combination to output the fine delay, obtaining multiple initial delay trigger signals; and eliminating delay jitter errors by voting calibration of the multiple initial delay trigger signals to obtain a final delay trigger signal to control the signal delay. This application employs a two-level architecture of clock counter to implement the coarse delay and carry4 chain to implement the fine delay, which can break through the limitation of the FPGA system clock cycle in terms of delay step accuracy, achieving fine delay control much smaller than the clock cycle, and solving the problem of insufficient accuracy in traditional delay methods.

This invention relates to a control method for well stratification, belonging to the field of oilfield production tools technology. The method controls the opening and closing of switches according to a pre-set timed stratification status schedule. During stratification, if the current stratum is identified before the scheduled time for the next stratum, a stratification adjustment pulse signal is emitted at the wellhead by changing the wellhead pressure. Upon detecting the adjustment pulse signal, the open switch closes, and the switch corresponding to the next stratum in the schedule opens. If the current stratum is not identified by the scheduled time for the next stratum, a delayed pulse signal is emitted at the wellhead. Upon detecting the delayed pulse signal, all switches do not perform any switching actions. This solution addresses the problem in existing technologies that cannot adjust the single-layer water-finding cycle in real time according to the production status of each oil layer.

The application discloses a delay circuit of pulse sequence, integrated circuit, interactive system, method and equipment, and relates to the field of signal processing.The delay circuit comprises an edge detection module, a cycle counter and a FIFO cache module.The edge detection module is used for receiving an initial pulse sequence, generating an enable signal according to rising edges and falling edges of pulse signals in the initial pulse sequence, and inputting a first value to the FIFO cache module based on the enable signal.The cycle counter is used for cyclically outputting a count value.The FIFO cache module is used for receiving the first value from a data write port and inputting the first value to a value comparison module after the first value moves to a data read port.The value comparison module is used for comparing the first value with a real-time count value of the cycle counter and generating a trigger signal when the two values are equal.The pulse generation module generates a pulse signal according to the trigger signal and obtains a delayed pulse sequence.Therefore, the delay circuit can complete overall delay of the pulse sequence.

To provide a conversion circuit that can reduce the layout area occupied by a latch circuit.SOLUTION: An A / D conversion circuit 1 converts an analog input signal Vin into numerical data using a pulse delay circuit 2, which is made up of multiple delay units DU connected in series, each of which inverts and delays a pulse signal to output it. Master latch circuits 21m, ..., and 24m hold the states of the delayed pulse group outputs P1, P2, P3, ..., and Pn output from the pulse delay circuit 2 using different clocks CK1, ..., and CK4. The slave latch circuits 21s, ..., and 24s hold the outputs of the master latch circuits 21m, ..., and 24m using a clock CK1.SELECTED DRAWING: Figure 1

This invention provides a method for handling gate pulse train contention timing. The method, developed based on an FPGA, includes the following steps: S1: Delaying the pulse modulation signal, and using the rising and falling edges of the delayed pulse modulation signal to trigger the generation of a leading-edge trigger pulse train and a turning-off leading-edge pulse train, respectively; S2: Widening the pulse modulation signal, and using the rising and falling edges of the widened pulse modulation signal to trigger the generation of a turning-off trailing-edge pulse train and a trailing-edge trigger pulse train, respectively; S3: Using the leading-edge trigger pulse and the turning-off trailing-edge pulse train to generate the rising edge of the secondary-side pulse modulation signal; using the trailing-edge trigger pulse train and the turning-off leading-edge pulse train to generate the falling edge of the secondary-side pulse modulation signal. This method effectively avoids the problem of gate drive waveform distortion caused by contention between leading and trailing-edge pulse trains under low repetition rate and wide pulse conditions.