61 results about "Delayed pulse" patented technology

The power stage of the switching converter includes a high-side switch and a low-side switch that are operated by respective drive signals, respectively. The current sensing block generates a sensing current signal that undergoes blanking processing for a first time duration at the beginning of a longer phase of the high-side phase and the low-side phase. The sense current signal is de-blanked at the end of the first duration. The current sensing block generates a first pulse synchronized with the starting point of the longer phase, and the pulse width of the first pulse is equal to the first duration. The gate driver receives the first pulse and generates a delay pulse synchronized with the start point of the longer phase, the pulse width of the delay pulse being equal to the sum of the first duration and the second duration, the gate driver generating a drive signal (for the switch driven in the longer phase), the drive signal has a first logic level for a duration of at least a pulse width of the delayed pulse.

A method performed by a node of a quantum key distribution (QKD) network includes receiving, from a hub of the QKD network, a user-node pulse train of optical-pulse pairs, each of the optical-pulse pairs comprising a first pulse and a second pulse having an optical phase shift relative to the first pulse. The method further includes splitting the user-node pulse train into first and second pulse trains, calibrating an asymmetric Mach-Zehnder interferometer with the first pulse train, blocking the second pulse of each of the optical-pulse pairs of the second pulse train to generate a filtered pulse train, splitting the filtered pulse train into a timing pulse train and a pre-qubit pulse train, delaying the pre-qubit pulse train into a delayed pulse train, and encoding the delayed pulse train into a photonic-qubit pulse train and transmitting the photonic-qubit pulse train to the hub.

The invention belongs to the technical field of laser pulse modulation, and particularly relates to an ultrafast laser multi-pulse sequence preparation device and method. According to the invention, ultrafast pulse laser is divided into a transmission light path and a reflection light path through a beam splitter, a spatial light modulator is utilized to perform programming control on a target pulse in the transmission light path, and amplitude and pulse width parameters can be controlled while multiple pulse strings are generated; and the light path of the reflection light path is controlled through the high-precision one-dimensional displacement table, so that the time delay of a reflection light path pulse relative to a transmission light path pulse is controlled. And after the reflected light path and the transmission path subjected to pulse shaping are combined again, a periodic pulse string sequence with controllable time delay, pulse number, pulse width parameter and pulse intensity is realized. The problem that high-precision multi-pulse dynamic programming cannot be achieved through a traditional adjusting mode is solved, and the problems that in the prior art, the number of excitation pulses and pulse width parameters cannot be controlled at the same time, and an ordered periodic pulse sequence cannot be generated are solved.

A power stage of a switching converter contains a high-side switch and a low-side switch respectively operated by corresponding drive signals. A current-sense block generates a sensed-current signal which is blanked for a first duration upon start of a longer phase of a high-side phase and a low-side phase. The sensed-current signal is un-blanked upon end of the first duration. The current-sense block generates a first pulse starting synchronous with the start of the longer phase and with pulse-width equaling the first duration. A gate driver receives the first pulse and generates a delayed pulse starting synchronous with the start of the longer phase and with pulse-width equaling a sum of the first duration and a second duration. The gate driver generates drive signal (for the switch being driven with the longer phase) with a first logic level for a duration of at least the pulse-width of the delayed pulse.

The invention discloses a single-photon streak tube laser radar based on a delay difference. The single-photon streak tube laser radar comprises a delay pulse generator, a laser, a delay difference generation module, a beam shaping system and a receiving system. Wherein the delay difference generation module comprises an optical delay path and a time delay path, and can dynamically adjust the delay difference to adapt to near-field high-precision and far-field wide-range detection requirements; the light beam shaping system shapes the laser into a one-dimensional fan-shaped light beam, so that the divergence direction of the one-dimensional fan-shaped light beam is aligned with the time deflection dimension of the streak tube detector, and the energy utilization rate and the streak image quality are improved; the receiving system rejects noise and solves a target distance by using a cross-correlation noise reduction and weighted fusion algorithm through multi-stripe redundancy processing, so that the single-photon detection efficiency and the anti-interference capability are remarkably improved. According to the invention, the detection capability of the system on a long-distance weak reflection target, the reliability in a complex environment and the three-dimensional imaging precision are effectively improved.

The invention discloses a multi-channel high-precision time sequence pulse transmitting system, and the system comprises a control panel which comprises a command receiving control unit and a time sequence generation unit; the command receiving control unit is configured to receive a control command and analyze the control command into pulse basic information; the time sequence generation unit is configured to receive the pulse basic information, generate a coarse delay pulse signal according to the pulse basic information, and generate a driving signal; the daughter board comprises a pulse precise delay unit and an optical port output unit; the pulse fine delay unit is configured to receive the driving signal, perform fine delay adjustment on the coarse delay pulse signal and generate a time pulse sequence; the optical port output unit is configured to receive the time pulse sequence and convert the time pulse sequence into an optical signal. The delay precision of the system can be effectively improved.

The invention discloses a motor control digital circuit and a driving system, and the circuit comprises a first delay time sequence module which transmits a secondary delay pulse to an acceleration and deceleration synchronization module based on a synchronization signal and delay time; the acceleration and deceleration synchronization module obtains path input after receiving the secondary delay pulse, and selects acceleration and deceleration path write-in and acceleration and deceleration position write-in sent to the acceleration and deceleration module; the stepping direction selection module receives the stepping and direction signals of the acceleration and deceleration module and the stepping and direction signals of the distance compensation module, and outputs stepping control and direction control of the motor according to the stepping direction selection signals; and the absolute position module outputs an absolute position based on stepping control and direction control of the motor. A synchronous control function and an absolute position function are added into an existing acceleration and deceleration function, so that a user can freely switch among three modes of acceleration and deceleration, synchronous acceleration and deceleration and distance compensation, an original complex algorithm is realized through a digital circuit, and the working efficiency and the integration degree are improved.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The invention discloses a diamond NV color center-based quantum teaching machine, which comprises a circuit part and an optical path part, and is characterized in that the circuit part comprises a computer, a microprocessor, a digital delay pulse generator, a single photon detector, a microwave source, a radio frequency source, a switch and a power amplifier; the light path part comprises a laser, an acousto-optic modulator, a diaphragm, an optical fiber collimator, a dichroscope, an objective lens, a long-pass filter, a pinhole lens combination and an optical fiber flange; the computer is communicated with the microprocessor and the digital delay pulse generator, and the microprocessor is communicated with the microwave source and the radio frequency source so as to control microwave and radio frequency output; microwave and radio frequency outputs are switched on and off through a switch, and the switch is connected with the digital delay pulse generator, the microwave source and the radio frequency source. According to the invention, a circuit part and an optical path part are combined, a basic ODMR experiment, an advanced Labian oscillation experiment, T1, T2 and T2 * experiments and a higher-level dynamic decoupling experiment are completed, and the cost of the device is far lower than that of a quantum teaching machine sold in the market at present.

The invention discloses a nuclear pulse signal trapezoidal forming method suitable for an FPGA, and the method comprises the steps: carrying out the high-speed digital sampling of an exponential decay original signal outputted by a detector, and obtaining a discrete digital detector signal vn; calculating the discrete digital detector signal vn by using a differential algorithm to obtain a differentiated pulse signal pn; delaying the pulse signal pn by using a digital delay line to form three delayed pulse signals, and performing synthesis operation on the pulse signal pn and the delayed pulse signals to obtain a synthesized pulse signal sequence sn; and performing integral operation on the synthesized pulse sequence signal to obtain a trapezoidal forming pulse yn. The nuclear pulse signal trapezoid forming method is simple in calculation and suitable for being implemented in the FPGA, few FPGA logic resources are used, and the calculation speed is high.

Waveform characteristics of pulses in a pulse train configured to cause pulsed field tissue ablation may be varied in a manner that improves electromagnetic compatibility while retaining treatment efficacy. Such waveform characteristics may include pulse-to-pulse initiation intervals, inter-pulse delays, pulse on-times, pulse widths, inter-phase delays in the case of biphasic pulses, or a combination thereof. Such waveform characteristics may be varied in a random manner. Variations of waveform characteristics may be bounded by minimum, maximum, or both minimum and maximum differences between various pulses or pulse groups, or between various pulse trains or pulse train groups, for example, to help ensure sufficient stability of treatment signal waveforms while allowing sufficient variability, for example, to improve electromagnetic compatibility.

The invention discloses a novel picosecond-level digital delay pulse generator hardware design, relates to the technical field of signal measurement, and is applied to delay and generation of digital pulses. Comprising an external trigger interface circuit which is used for converting an external signal into a level signal which can be identified by SerDes of an FPGA; the FPGA master control module is used for receiving and sending pulses; the whole hardware design integration is high, the delay accuracy reaches 10ps when the pulse delay is set to be 1us, the jitter RMS value is 10.7 ps, the minimum delay time is not larger than 30ns, and the bandwidth for processing pulse signals can reach 29GHz.

To provide a pulse width measuring circuit with which a measurement time is shortened.SOLUTION: A first programmable delay circuit 130 and a second programmable delay circuit 140 respectively delay a first pulse S1 and a second pulse S2 corresponding to an input pulse SIN and generate a first delay pulse Sd1 and a second delay pulse Sd2. A latch circuit 150 latches the first delay pulse Sd1 in response to an edge of the second delay pulse Sd2. A controller 160 continuously sweeps a delay amount τ2 of the second programmable delay circuit 140 in first processing, and detects a first delay mount τP when the output Q of the latch circuit 150 changes. In second processing, the delay amount τ2 of the second programmable delay circuit 140 is changed by a binary search and a second delay amount τn is detected when the output Q of the latch circuit 150 changes. The difference between the first delay amount τP and the second delay amount τn is made a pulse width Tp of the input pulse SIN.SELECTED DRAWING: Figure 1

The invention relates to the technical field of spatial fault tolerance, in particular to a reliability design method for an intelligent computing system of a multi-dimensional COTS device. The method comprises the following steps of: respectively arranging a corresponding fault detection and recovery module in the intelligent computing module and each external interface module, and arranging a long-delay system-level watchdog respectively connected with the intelligent computing module and the external interface module; the long-time-delay system-level watchdog comprises a latch arbitration circuit and multiple paths of long-time-delay pulse generators, and the latch arbitration circuit is used for receiving clear signals sent by the intelligent calculation module and the N external interface modules and clearing timing of each path of long-time-delay pulse generator after latching and arbitration; and if the timing exceeds the first set time delay, outputting a first reset signal, and resetting and restarting the corresponding intelligent computing module or the external interface module. According to the scheme, two-stage reliability design is adopted, and compared with backup design, occupation of space and computing resources can be reduced.

The invention provides an experimental simulation system of an equivalent wind shear wind field. According to the system, pulse light signals emitted by a wind measurement laser radar are simulated through different delay optical fibers to reach atmospheric stratification at different positions, then delayed pulse light is emitted to different positions of the side face of a rotating disc rotating at a constant speed, and echo signals obtain Doppler frequency shifts of different sizes due to different radial speeds; based on this, the change of wind speed in wind shear is simulated. A required equivalent wind shear wind field can be customized by adjusting the length of the delay optical fiber, the diameter of the turntable and the incident position of light on the side surface of the turntable. The system is simple in structure and low in cost, and can provide an equivalent wind shear wind field with accurate and controllable wind speed and abundant changes.

A signal generation circuit according to one embodiment comprises: a delay signal generation unit configured so as to generate at least one delay pulse signal using an input pulse signal common to a first switching element and a second switching element; and a logic synthesis unit configured so as to generate a first control pulse signal and a second control pulse signal for the first switching element and the second switching element by performing different logic synthesis on two signal sets of a plurality of signal sets specified by the at least one delay pulse signal and the input pulse signal. The first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

The present invention relates to the field of spatial fault tolerance technology, and in particular to a reliability design method for a multi-dimensional COTS device intelligent computing system. The method includes: setting a corresponding fault detection and recovery module inside the intelligent computing module and each external interface module, and setting a long-delay system-level watchdog connected to the intelligent computing module and the external interface module respectively; the long-delay system-level watchdog includes a latching arbitration circuit and a multi-channel long-delay pulse generator, the latching arbitration circuit is used to receive the clear signal sent by the intelligent computing module and N external interface modules, and clear the timing of each long-delay pulse generator after latching and arbitration. If the timing exceeds the first set delay, a first reset signal is output to reset and restart the corresponding intelligent computing module or external interface module. This solution adopts a two-level reliability design, which can save space and computing resources compared to the backup design.

The invention discloses a delay circuit of a pulse sequence, an integrated circuit, an interaction system, a method and equipment, and relates to the field of signal processing. The delay circuit comprises an edge detection module used for receiving an initial pulse sequence, generating an enable signal according to a rising edge and a falling edge of a pulse signal in the initial pulse sequence, and inputting a first numerical value to an FIFO cache module based on the enable signal; the cycle counter is used for cyclically outputting a count value; the FIFO cache module is used for receiving the first numerical value from the data writing port and inputting the first numerical value to the numerical value comparison module after the first numerical value is moved to the data reading port; the numerical value comparison module is used for comparing the first numerical value with a real-time counting value of the cycle counter, and generating a trigger signal when the two values are equal; and the pulse generation module is used for generating a pulse signal according to the trigger signal to obtain a delayed pulse sequence. As a result, the delay circuit can complete the overall delay of the pulse sequence.

The embodiment of the present invention provides a method, system, device and medium for improving the initialization speed of BRAM in FPGA, using an additional bit CE_INV signal with a delayed pulse to perform an XOR logic operation with a first chip select enable signal with a wide pulse to obtain a second chip select enable signal with a narrow pulse, and the second chip select enable signal with a narrow pulse is used to automatically turn off the BRAM chip select signal during the initialization process in the BRAM, without the need to send an additional operation of turning off the BRAM chip select enable signal before the next write operation after each BRAM write operation is completed. The width of the narrow pulse is the time required to write data to a CFG bit in the configuration memory, which is much shorter than the cycle required to rewrite the chip select enable signal to 0 to ensure that the BRAM will not act before the next write operation, thus saving the initialization time of the BRAM and meeting the application requirements that require fast response.

The application discloses a signal sampling method, device and equipment of digital PET, and a storage medium. The signal sampling method of the application comprises the following steps: performing delay processing on pulse signals input to multiple channels, and obtaining multiple delay pulse signals; switching the multiple channels based on the multiple delay pulse signals, and obtaining comparison signals; and performing time-to-digital conversion processing on the comparison signals to extract time information. According to the scheme of the embodiment of the application, the multiplexing of time-to-digital converters among multiple channels can be realized in the FPGA, information loss is not caused, the resource usage of the FPGA is reduced, and the time measurement precision and system integration are improved.

The present inventive concept provides a capacitance sensor array chip with programmable fusion pixels comprising: a programmable module for generating a choosing signal according to a first clock signal; a delay pulse module for generating a third clock signal according to a second clock signal and a sensing pulse signal; and multiple electrode array modules comprising a charging unit for generating a charging signal according to the sensing pulse signal; M×N electrode pixel units forming an array, wherein the electrode arrays chooses a certain pattern of the electrode units according to the choosing signal in orders and the certain pattern of the electrode units in the electrode array generates a sampling signal according to the charging signal; and a sampling unit for generating a sensing output signal according to the sampling signal and the third clock signal.

The invention relates to an inter-pulse double-path delay accurate modulation interference method and device based on SAR-GMTI, belongs to the technical field of radar signal processing interference, and solves the problem that in the prior art, false targets with high-degree-of-freedom position distribution cannot be generated in an interference weakening area. The method comprises the following specific steps: a ground jammer receives a signal transmitted by an aerial radar to obtain a received signal; the ground jammer performs interference enhancement region complementary modulation on the received signal to obtain a first interference signal; wherein the first interference signal is formed by superposing a path of echo signal in a direct forwarding form and a path of echo signal forwarded by delaying n pulses; doppler modulation is carried out on the first interference signal to compensate position lag of delay pulse forwarding, and a second interference signal is obtained; and two-dimensional frequency modulation is carried out on the second interference signal, and an obtained final interference signal is transmitted back to the aerial radar, so that the multichannel SAR-GMTI deception interference with high degree of freedom not being canceled is realized.

The invention discloses a calibration method for impulse radar transmitted pulse jitter, and the method comprises the steps: capturing a transmitted pulse string sample of an impulse radar, generating a reference pulse waveform, and constructing a delay pulse sample set through random numbers; according to the reference pulse waveform and the delay pulse sample set, obtaining a measurement result by using a delay measurement mode based on multiple rules; according to the delay pulse sample set and the measurement result, constructing a delay measurement data set, carrying out fusion mapping relation training learning, and generating a fusion mapping relation function; a direct wave of the impulse radar is actually measured, and a measurement result is obtained through a delay measurement mode based on multiple rules; and according to the measurement result, obtaining a fusion value of the measurement result by using a fusion mapping relation function, and using the fusion value to delay the correction parameter.

The invention provides an all-digital delay-locked loop circuit and a calibration method, and relates to the technical field of integrated circuits. The all-digital delay phase-locked loop circuit comprises a frequency divider, a phase discriminator, a calibration logic circuit and a numerical control delay line, the input end of the frequency divider receives a reference clock signal, and the first output end of the frequency divider is connected with the input end of the numerical control delay line to provide a reference pulse signal; a second output end of the frequency divider is connected with a first input end of the phase discriminator and provides a phase discrimination sampling pulse signal; the second input end of the phase discriminator is connected with the output end of the numerical control delay line, and receives a delay pulse signal after the reference pulse signal is delayed by the numerical control delay line; the output end of the phase discriminator is connected with the input end of the calibration logic circuit to provide a phase discrimination result; the output end of the calibration logic circuit is connected with the control end of the numerical control delay line, and the delay step length of the numerical control delay line is calibrated according to the phase discrimination result so as to calibrate the delay of the delay pulse signal. The phase discrimination error can be reduced, and the calibration precision can be improved.

The invention discloses a testing device and a testing method for a powder fuel combustion transient spectrum, and relates to the technical field of powder fuel spectrum testing. The testing device comprises a shock tube system, a multi-channel oscilloscope, a spectrometer, an I CCD detector, a pressure sensor and a multi-channel digital delay pulse generator; an optical signal generated by powder fuel high-temperature self-ignition is transmitted to an I CCD detector, the time distribution of the measured optical signal and the time distribution of the I CCD detector meet a one-to-one corresponding optical system, and transient spectral information of powder fuel high-temperature self-ignition luminescence at different time is obtained. The device can realize nanosecond-level time resolution, is suitable for a rapidly changing combustion process, can obtain high-quality transient spectrum data by combining a high-resolution spectrometer and an I CCD detector, realizes measurement of a high-resolution transient spectrum of high-temperature self-ignition combustion of the powder fuel, and can be widely applied to transient spectrum measurement of the powder fuel.

The present invention is applicable to the field of analog-to-digital conversion and provides a high-speed two-step time-domain analog-to-digital converter, comprising: a common-mode voltage conversion unit for converting a differential voltage signal into first and second time pulse signals; a conversion and selection unit for sequentially delaying and encoding the first and second time pulse signals to obtain a first code, and selecting and outputting a first signal and a second signal from the first and second time pulse signals and the multiple delayed pulse signals obtained by the delay processing; a one-step multi-bit successive approximation analog-to-digital conversion unit for continuously quantizing and encoding the first and second signals, outputting a second code, and extending or shortening the transmission time of the first and / or second signals based on the second code; and a quantization coding unit for obtaining a target quantization code using the first and second codes. The solution provided by the present invention can effectively shorten quantization time, improve quantization efficiency, and improve quantization accuracy.

A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.

The application provides a time coding compressed sensing imaging method and device based on FPGA and electronic equipment, the method is applied to the technical field of photoelectric detection and computational imaging, and the method comprises the steps of: calibrating an FPGA delay unit based on a reference clock, constructing a delay lookup table and writing a time coding sequence of random coding and a push-scan mode. In response to a synchronization signal, coarse and fine delay tap values are analyzed, a reference pulse is generated and is synchronized to the reference clock, a delay pulse is generated through fine delay, three alignment timing control signals are generated, and the excitation gate and exposure signals are cooperatively controlled. Discrete integral observation values are collected in an exposure window, a continuous observation operator is constructed in combination with the delay lookup table, a target function is constructed based on physical priori, and the target function is iteratively solved to obtain a high signal-to-noise ratio, a transient response curve and physical parameters. The method can solve the problems of slow sampling speed and lack of software flexibility due to dependence on modulation devices in traditional hyperspectral imaging technology.

A method is provided for radar ranging using an IR-UWB radar transceiver. The range is determined by measuring a time required by a transmitted pulse to be reflected by an object and returned to the transceiver. The method includes transmitting a ranging signal having a predetermined sequence of positive and negative pulses using a transmitter of the transceiver. A receiver of the transceiver receives a signal having a reflected portion and a feedthrough portion. In the method, the receiver cancels the feedthrough portion using a delayed pulse polarity signal such that when the delayed pulse polarity signal is multiplied and accumulated with the received signal, the feedthrough portion is canceled, and the reflected portion is amplified. In another embodiment, a transceiver is provided that cancels the feedthrough portion while amplifying the reflected portion. Cancelling the feedthrough portion allows short-range operation by removing a blind range of the transceiver.

Provided is a pulse generation circuit that receives a clock signal and outputs a delayed pulse signal, including: a first delay-locked loop circuit that receives the clock signal and generates a first delay signal obtained by delaying the clock signal; a second delay-locked loop circuit that generates a second delay signal with reference to the first delay signal; and an output circuit that outputs the delayed pulse signal according to the first delay signal and the second delay signal. The second delay-locked loop circuit may have: a second charge pump that outputs a current according to the clock signal and the delayed pulse signal; and a second delay circuit that outputs the second delay signal obtained by delaying the clock signal according to a current output by the second charge pump.