Reconfigurable circuit to emulate system critical paths

Abstract

A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Description

BACKGROUND[0001]a. Field of the Invention[0002]The present invention generally relates to microprocessors, and more particularly to maintaining the performance of such microprocessors using control circuitry.[0003]b. Background of Invention[0004]Microprocessor devices should operate reliably across a variety of environmental conditions. One occurrence associated with microprocessor environments is voltage droop, whereby as a result of, for example, changes in current load, the supply voltage momentarily drops. Voltage droop may in turn affect the maximum operating frequency (fmax) of the microprocessor compared to the actual frequency at which the microprocessor is being driven. For example, the microprocessor may be operating at a nominal clock frequency of 4.5 GHz, while the maximum operating frequency (fmax) of the microprocessor may be characterized as being 4.7 GHz. Thus, a guardband of 200 MHz (i.e., 4.7 GHz−4.5 GHz=0.2 MHz) exists.[0005]According to one scenario, a voltage dr...

AI Technical Summary

Benefits of technology

The patent describes a circuit and method for monitoring and controlling a clock signal in a microprocessor device. The circuit includes a voltage divider network, a selector device, and a delay element. The delay element receives the scaled supply and ground voltages and applies a delay to each pulse of the clock signal, resulting in a delayed pulse signal. A frequency correction signal is then generated based on the variation in the supply voltage of the microprocessor, and this signal is applied to the clock source to maintain a frequency guardband for the clock signal. The technical effect is the ability to maintain a stable clock signal even during voltage variations, ensuring optimal performance of the microprocessor device.

Problems solved by technology

Therefore, as a result of driving the microprocessor at a nominal frequency (i.e., 4.5 GHz) that is beyond the momentarily reduced fmax (i.e., 4.3 GHz) value, the microprocessor operation may fail.

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