11 results about "Microprocessor design" patented technology

The invention discloses a sequential single-emission five-stage assembly line micro-processing system and application, and relates to the technical field of microprocessor design and embedded systems. The sequential single-transmission five-stage assembly line micro-processing system mainly comprises an instruction fetching module, a decoding module, an execution module, a two-stage assembly line memory access module, a write-back module, a data forwarding module, an interruption and exception processing module and a bus network. By implementing the sequential single-emission five-stage assembly line micro-processing system provided by the invention, the execution efficiency, the resource utilization rate and the real-time performance of an embedded system can be improved.

The invention discloses a 32-bit processor based on an RISC-V instruction set architecture, and belongs to the field of computer system structures and microprocessor design. According to the technical scheme adopted by the invention, the 32-bit processor based on the RISC-V instruction set architecture comprises an instruction set extension module, two new instructions of'aggresgate 'and'disaggresgate' are introduced, an R-type coding format is adopted, and the 32-bit processor is used for realizing grouping and splitting operation of data bits; the data path unit comprises a general register group, an arithmetic logic unit ALU and a special adder and is used for executing various data operations and processing; the control unit is used for generating a control signal according to an instruction decoding result and controlling operation of the data path unit and the memory; according to the method, by adding the special instruction and optimizing the data flow control mechanism, the complex bit operation is completed in a single period, the cache pressure is reduced, and the method has the advantages of improving the bit operation efficiency, reducing the instruction cache pressure and reducing the dynamic power consumption.

A Coriolis flow meter includes a sensor system generating a first sensor signal and a second sensor signal. A measuring or operating circuit includes a microprocessor designed to operate an excitation system. An all-pass filter having a filter coefficient and which is designed to receive the first sensor signal and to generate a filtered first sensor signal is provided. The measuring or operating circuit receives the filtered first sensor signal and the second sensor signal, and has a control circuit designed to control the filter coefficient, based on the filtered first sensor signal and the second sensor signal, or based on a variable derived from the filtered first sensor signal and the second sensor signal, such that a control criterion is satisfied, and a first measurement value representing the process variable from the filter coefficient is generated.

There is described a computing device (800) for value prediction in concurrent instruction execution (406), the computing device (800) for: obtaining a load value (511) of an executed instruction (101); inputting at least a portion (601) of the load value (511) into a training table (503); in accordance with the load value (605) having a training table confidence level (602) above a training table confidence threshold, the load value (511) is input into a value table (504) comprising one or more load values (605) for the corresponding one or more instructions for use as predicted values (408) in the concurrent instruction execution (406). In this manner, the load value (511) can be used as a predicted value (408) only when the confidence level is at a sufficiently high level.

The application discloses a hardware-multiplexing-based floating-point addition and rounding off tail bit processing device and method, relates to the technical field of microprocessor design, and comprises: a scale shift multiplexing circuit, which is used for performing an exponent alignment operation on a first floating-point operand and a second floating-point operand, performing tail number right shift processing on the smaller floating-point operand in the aligned first floating-point operand and the aligned second floating-point operand, and extracting a target tail bit discarded in the tail number right shift processing process; a sign exponent splicing circuit, which is used for obtaining a target sign bit and a target exponent output by a main operation unit, splicing the target sign bit, the target exponent and a target tail bit, and generating an intermediate floating-point number; and a normalization multiplexing circuit, which is used for taking the intermediate floating-point number as a third floating-point operand, constructing a virtual operand as a fourth floating-point operand, performing a floating-point addition operation on the third floating-point operand and the fourth floating-point operand, and outputting a normalized floating-point number. High-precision intermediate results in iterative calculation are obtained.

This invention discloses an operator-based microprocessor architecture design method and system. The invention includes: for a target instruction set architecture, determining the computational functions contained in the target instruction set it supports, and abstracting these computational functions as operators; for each operator in the operator set, establishing execution component libraries for the instructions of the target instruction set's computational functions mapped to those operators; and updating the execution pipeline template based on the execution component library to complete the design of the execution pipeline in the target instruction set architecture. This invention effectively reduces the coupling between the instruction set and the hardware architecture corresponding to the pipeline execution stage, enabling rapid completion of the execution pipeline design in the target instruction set architecture. It provides a lightweight and scalable implementation method for microprocessor design supporting multiple instruction sets, alleviating the area overhead problem caused by incremental design of multiple instruction sets, and reducing the design cycle of microprocessor architecture upgrades.

The application provides a systolic array hardware implementation method and device supporting multiple different precision operations, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: establishing an association table associated with the stage of a neural network and an operation configuration; S2: obtaining the stage of the neural network, and obtaining the operation configuration corresponding to the stage from the association table; S3: if the operation configuration is a mixed precision floating point operation, then a 16*16bit+32bit fixed point / floating point operation model is established based on a systolic array, and the mixed precision floating point operation is performed based on the 16*16bit+32bit fixed point / floating point operation model; if the operation configuration is a fixed point shaping operation, then an 8*8bit+16bit fixed point operation model is established based on a systolic array, and the fixed point shaping operation is performed based on the 8*8bit+16bit fixed point operation model. The application fully excavates the space for reducing precision, improves processing throughput, improves the operation performance of the systolic array, and reduces unnecessary hardware overhead.

The application provides an instruction construction method and device supporting processing function extension, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: obtaining a target source operand from a processor; S2: storing a target function descriptor in the target source operand; and S3: controlling an accelerator to analyze the target function descriptor in the target source operand to obtain a target instruction function. The application stores the target function descriptor in the target source operand, realizes the description of the instruction function, and identifies the instruction function by analyzing the input function descriptor by means of the accelerator, so that the function of the instruction can be further extended without extending the length of the instruction.

The application provides an accumulator double buffering method and device supporting work area and result area switching, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: taking one buffer in an idle state as a work area and taking another buffer in an unloading state as a result area when it is not determined that the two buffers are areas, and performing S2 when it is determined that the two buffers are areas; S2: controlling the work area to perform accumulation operation and store accumulation results and controlling the result area to unload data; S3: switching the work area to the result area when the accumulation results of the work area are stored, and switching the result area to the work area when the data of the result area is unloaded and cleared. The accumulation results of the application can be directly accumulated with the current buffer and written without waiting for the completion of the buffer data unloading, so that the delay of the accumulation result write-back can be hidden, and the performance of the systolic array is improved.

The application provides an accumulator hardware implementation method and device supporting continuous writing of accumulation results, and belongs to the technical field of high-performance microprocessor design. The method comprises the following steps: S1: determining the starting entry of the current accumulation result writing in the accumulator based on the enable bit corresponding to the current accumulation result; S2: sequentially writing the current accumulation result into the accumulator from the starting entry; S3: obtaining the ending entry of the current accumulation result writing, and obtaining the latching entry of the current accumulation result based on the ending entry; and S4: latching the latching entry of the current accumulation result. In programming, the programmer can realize the continuous writing function of the accumulation result based on the enable bit, so it is not necessary to manually calculate the accumulator buffer address of the current writing, and therefore the programming complexity and the possibility of errors in calculating the address can be reduced, and the programming efficiency is improved.

A safety circuit for a low heat capacity hair styling appliance is described. Safety circuitry may rely on intentionally designed weak links or temperature sensors, as well as electronic circuitry that may remove power from heater electrodes, as well as dual microprocessor designs.