61 results about "Microprocessor design" patented technology

A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.

Power, routability and electromigration have become crucial issues in modern microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.

To resolve problems of communication between a mobile telephone provided with a smart-card reader and the circuits of a smart-card reader, it is planned to provide this mobile telephone with a fourth microprocessor designed to manage the communications of the mobile telephone with the smart card only. This fourth microprocessor then becomes, in competition with a SIM security circuit of the mobile telephone, a master of the microprocessor of the mobile telephone. To resolve the problem of competition resulting from the existence of these two master circuits, it is planned that one of the two will be called upon to execute a command and that it will execute this command if it falls within the commands that are executable by it. If this command is not executable by this first microprocessor, then it is transmitted to the microprocessor of the second master circuit so that this second master circuit executes it. By acting in this way, it is shown that it is very easy to update mobile telephones, even old models. To this end, it is enough to place especially the fourth microprocessor in a battery pack and interchange the battery pack with the original battery pack.

Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.

The invention relates to the field of information security and microprocessor design, and provides an optimized automatic bilinear pairing encryption method and device based on a point blinding process aiming at increasing the computing efficiency of algorithms from the perspective of hardware implementation, further saving computing resources, fundamentally reducing the encryption and decryption time and space consumption, simultaneously using reasonable anti-attack protection measures, effectively enhancing the security of bilinear pairing encryption, and providing a possibility for replacing a current mainstream encryption system by using the bilinear pairing encryption method. The technical scheme adopted by the invention is that the optimized automatic bilinear pairing encryption method based on the point blinding process comprises two steps namely encryption and decryption, and also comprises a step that a certificate authority (CA) gives a public key Kp=sPCA and a private key dA=sIDA in advance by using the feature that a random parameter s belongs to [1, p-1] and p is a prime field which is represented by a formula, wherein PCA is a public parameter, and IDA is identity information of a user; and it is assumed that a user B encrypts a message which is represented by a formula to a user A, a formula is a bilinear pairing, and both P and Q are input formal parameters. The optimized automatic bilinear pairing encryption method and device based on the point blinding process provided by the invention are mainly applied to information security occasions.

The invention relates to the field of automatic control in industrial production, particularly an automatic control system for Kyropoulos-process sapphire crystal growth. The invention is characterized in that the automatic control system mainly comprises a microprocessor, a touch screen, an audible and visual alarm circuit, a control cabinet, an upper computer, a vacuum meter, a heating power source, a rotary variable-frequency motor, an elevating variable-frequency motor, a weighing sensor and an elevating stepping motor, wherein the microprocessor is the core unit of the whole automatic control system, implements communication and control with the control cabinet, upper computer, vacuum meter, heating power source, rotary variable-frequency motor and elevating variable-frequency motor through an RS-485 bus, implements communication with the touch screen and weighing sensor through an RS-232 bus, and controls the operation of the elevating stepping motor and audible and visual alarm circuit through an I / O port. The multi-physical-quantity detection and control system in the Kyropoulos-process sapphire crystal growth process is designed on the basis of the embedded microprocessor, implements automatic control on the whole crystal growth process, lowers the dependence on the artificial intervention and technology capability of operating personnel in the crystal growth process, reduces the labor amount of the operating personnel, and enhances the standardability and crystal quality of the crystal growth operation process.

Methods and apparatus for improving system performance using redundant arithmetic are disclosed. In one embodiment, one or more dependency chains are formed. A dependency chain may comprise of two or more instructions. A first instruction may generate a result in a redundant form. A second instruction may accept the result from the first instruction as a first input operand. The instructions in the dependency chain may execute separately from instructions not in the dependency chain.

The invention discloses an elliptic curve cipher processor, and relates to the field of information technology security and micro-processor design. The processor is of a transport triggered architecture (TTA) structure, and the hybrid flow mechanism of the elliptic curve cipher processor comprises a transmission flow and a functional unit flow. The elliptic curve cipher processor comprises a command memory, a fetch unit, a decoding unit, a register file, a bus internetwork, a Socket and a functional unit, wherein the fetch unit fetches a command in the command memory; the command is decoded by the decoding unit; the decoded command is subjected to an error correction code (ECC) operation by selecting a corresponding functional unit through the bus internetwork; operation data required by the functional unit is acquired through the register file or the functional unit; and the functional unit is interconnected with the Socket through the bus internetwork. By utilizing the elliptic curve cipher processor, the operation speedup ratio is improved, the engineering change cycle is shortened, a software and hardware collaborative design is realized, and the problem of going against secondary development is solved.