System and method for issuing instruction, processor and design method thereof

A technology of instruction emission and processor, which is applied in the computer field, can solve the problems of inability to judge data correlation, judge troublesome instructions, etc., and achieve the effect of improving processor performance, reducing complexity, and ensuring correctness

Active Publication Date: 2010-05-12
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when designing the structure of the microprocessor and adopting the pipeline method of dynamically dispatching instructions, there are still many problems to be considered, because there are still many data dependencies that cannot be judged in the instruction emission stage, or the judgment of more troublesome instructions

Method used

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  • System and method for issuing instruction, processor and design method thereof
  • System and method for issuing instruction, processor and design method thereof
  • System and method for issuing instruction, processor and design method thereof

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Experimental program
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Embodiment 1

[0039] The present invention proposes a launch strategy combining dynamic scheduling and static scheduling. Different processor structures can divide instructions into different types according to their respective requirements. The instructions whose correlation is not easy to judge or cannot be judged are classified into one category. Instructions of this type can only be scheduled statically, and are issued completely in accordance with the sequence of instructions in the source program, but instructions of this type do not affect the issuance of other instructions that allow dynamic scheduling.

[0040] see Image 6 , the present invention discloses an instruction emission system, which includes an instruction classification module 10 and an instruction emission module 20 .

[0041] 【Command classification module】

[0042] When the instructions are written into the operation queue, the inter-instruction correlation is judged, and the inter-instruction interdependence informa...

Embodiment 2

[0064] The difference between this embodiment and Embodiment 1 is that in this embodiment, the instruction classification module judges whether the correlation of each instruction in the operation queue is easy to judge through a judgment logic circuit (or whether it can be obtained through the logic judgment circuit) ; If it is easy to determine (or can be determined), the instruction is classified as a dynamic scheduling instruction; otherwise, the instruction is classified as a static scheduling instruction. It can be seen that the static scheduling instruction refers to the instruction whose correlation is not easy to judge, that is to say, when the instruction is written into the operation queue, it is judged that there is no correlation with other instructions, but in fact there is correlation.

[0065] Specifically, the judgment logic circuit can judge whether the correlation of each instruction in the operation queue is easily (or can) be judged by the judgment logic ci...

Embodiment 3

[0068] In this embodiment, the instruction sending system includes an instruction classification module and an instruction sending module. The instruction classification module is used to classify the instructions whose correlation has been judged in the operation queue; classify the instructions whose correlation is difficult to judge in the operation queue into statically scheduled and sequentially executed instructions; classify the instructions whose correlation is easy to judge in the operation queue into Instructions for dynamic scheduling and out-of-order execution; the instruction emission module is used to emit static scheduling instructions and dynamic scheduling instructions with operands prepared from the operation queue according to the static scheduling and dynamic scheduling methods respectively.

[0069] In the instruction emission method corresponding to the above-mentioned instruction emission system, the instructions whose correlation is difficult to judge in...

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Abstract

The invention discloses a system and a method for issuing an instruction. The system comprises an instruction classifying module and an instruction issuing module, wherein the instruction classifying module classifies instructions in an operation queue; the instructions which can only be statically scheduled and sequentially executed in the operation queue are classified as static scheduling class instructions, and the instructions which can be dynamically scheduled and executed out of order in the operation queue are classified as dynamic scheduling class instructions; the instruction issuing module issues the static scheduling class instructions and the dynamic scheduling class instructions of which operands are prepared in the operation queue according to a static scheduling method and a dynamic scheduling method respectively. The system and the method indicate the instructions of which data dependency is not easy to judge, and statically schedule the instructions by aiming at the instructions. The execution method can ensure the correctness of program execution, and greatly reduces the complexity of microprocessor design. For the instructions of which the data dependency is easy to judge, the system and the method make full use of a flow line to improve performance of a processor by continuously adopting the method for dynamically scheduling the instructions.

Description

technical field [0001] The present invention belongs to the field of computer technology, and relates to an instruction emission system, in particular to an instruction emission system and method combining dynamic scheduling and static scheduling; in addition, the present invention also relates to a processor including the above-mentioned instruction emission system and the processor design method. Background technique [0002] Modern microprocessors usually use pipeline technology to increase the processing speed of the microprocessor. Pipeline technology divides the process of instruction execution into several stages, and implements parallel execution of instructions by executing different instructions in different stages, thereby improving the performance of the processor. [0003] Such as figure 1 As shown, the execution of the entire instruction can be divided into several stages according to the specific structure of the processor, and the pipeline is usually divide...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 李祖松郝守青汪文祥徐翠萍
Owner LOONGSON TECH CORP
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