803 results about "Operand" patented technology

The invention discloses an instruction execution acceleration method based on a GPGPU and a GPGPU architecture, and relates to the field of high-performance computation.The method comprises the steps that a thread execution task output by a host compiler is received, and the thread execution task is scheduled according to the current idle state of a computing unit; capturing instruction data output by the host compiler, and executing concurrent instruction decoding according to the corresponding instruction type to obtain a machine code corresponding to the instruction data; obtaining an operand corresponding to the instruction data, and generating a to-be-transmitted instruction based on the machine code corresponding to the instruction data and the operand after secondary verification; according to the calculation complexity, determining an optimal calculation unit, and sending the to-be-launched instruction to the optimal calculation unit; and receiving an execution result of the to-be-transmitted instruction, and returning the execution result to the terminal. The thread execution task is dynamically scheduled according to the idle state of the computing unit, so that computing resources can be fully utilized, and the operation efficiency is improved.

The invention discloses mixed precision multiply-add operation hardware, which comprises an input processing unit used for obtaining standard symbols, standard indexes and standard mantissas according to a pre-configured input format and unpacked input multiply-add operation factors, and obtaining input and output special value detection results; the floating point multiplier-adder is used for calculating an operation result after the operand multiplies the scaling factor and the offset is accumulated according to the symbol, the exponent and the mantissa of each multiplication-addition operation factor; and the output processing unit is used for obtaining a target format result according to a pre-configured output format, a rounding type and a normalization and rounding operation result, packaging the target format result according to a detection result and outputting the target format result, and by multiplexing a data path of the floating-point multiplier-adder, the chip area is saved, format conversion is integrated, a data stream is simplified, and the data processing efficiency is improved. The requirements for automatic reconstruction of the multiply-add operation unit according to input and output formats and quantization and inverse quantization of floating points and integers are met, and the reuse rate of computing resources is increased.

The invention belongs to the field of high-performance computing, and relates to an integer parallel computing method and device based on distributed storage and computer equipment, and the method comprises the steps of collecting real-time resource indexes, dynamically identifying fault nodes, triggering task migration, and performing data verification and hard disk fault detection. The weight value of each node is calculated, the nodes are arranged according to the descending order of the weight values, and the nodes with high load capacity are selected to distribute tasks; dynamically distributing a data generation task to a computing node, executing parallel computing, and performing distributed storage on a result; obtaining an operand, converting the operand into a first-order tensor form of a basic operand, serializing tensor data, and sending the serialized tensor data to a parallel computing layer; distributing a search task to a computing node, retrieving storage data in parallel, reading effective data from a storage layer, and combining search results into a partial sum; and summarizing and then outputting. The system has dynamic resource management and fault-tolerant capabilities, and can realize efficient task allocation and load balancing.

The invention relates to the technical field of microprocessor structures, and discloses a protocol calculation method, an engine, computer equipment, a storage medium and a program product.The protocol calculation engine comprises an instruction receiving module used for receiving a protocol instruction sent by a core; the instruction splitting module is used for splitting the protocol instruction into a read request and a write request; the read request processing module is used for reading an operand corresponding to the read request from the draft book storage module; and the write request processing module is used for executing protocol calculation on the operand according to the protocol instruction to obtain a calculation result, and writing the calculation result into a draft book for storage. The protocol calculation engine specially used for protocol calculation is designed, and the protocol calculation instruction is executed asynchronously, so that compared with a traditional VPU form, the occupied chip area is small, the calculation efficiency is high, judgment is completed through answer words, and programming is convenient.

The invention provides a collaborative computing method, system and device based on SIMD and SIMT, and belongs to the technical field of computer processing. The method is applied to a Warp composed of a plurality of SPs, and the Warp comprises an SIMT front end and an SIMD rear end. Each SP corresponds to a vector register combined by a plurality of short registers; generating instruction fetching indication information under the condition that a thread bundle scheduler at the front end of the SIMT determines that a first thread bundle corresponding to the calculation task is in an activated state; obtaining a first cache instruction corresponding to the first thread bundle through an instruction fetching unit, and sending the first cache instruction to a decoding unit at the front end of the SIMT for analysis; obtaining one or more corresponding required operands through an operand collection unit at the rear end of the SIMD; and distributing the required operands to the corresponding calculation management units through the SIMD rear end to execute the corresponding calculation tasks, and writing the calculation results corresponding to the calculation tasks back to the storage unit through the write-back unit.

The invention discloses a reconfigurable systolic array tensor IP core based on an FPGA. The architecture comprises a core controller, a shift distributor, a data processing array and a four-stage data cache. The tensor core can adapt to general tensor multiplication and addition operations in Prefill and Decode stages of the generative neural network at the same time through reconfigurable design. The core controller receives the tensor multiplication instruction and the configuration information and decouples the tensor multiplication instruction and the configuration information according to a data stream to generate a plurality of block tensor multiplication instructions. The shift distributor decodes a block tensor multiplication instruction, decoded mode information controls data communication between a first-level cache and a second-level cache (Distrided RAM and Bram), a control signal of a data processing array is generated, and the control signal enters the array together with data to flow. And the data processing array is connected with different secondary BRAM caches according to the received configuration information and is used for processing data in a bubble-free pulsating flow manner. The four-stage data cache realizes the multi-stage pinpong operation of the loading of the operation data of the tensor operation core, and realizes the multi-stage pipeline design of the data from the off-chip HBM to the on-chip URAM, from the URAM to the BRAM and from the BRAM to the operation unit. Aiming at a single-user edge end generation type network reasoning task, a core controller generates a data processing unit mode configuration signal in a fine-grained (tensor element level) manner, and the data processing unit mode configuration signal is transmitted by a shift distributor and flows in parallel with operation data, so that the mode configuration efficiency and the hardware resource utilization rate are greatly improved, the problem of high fan-out caused by broadcast control is reduced, and the user experience is improved. A control flow is designed by means of the structural characteristics of the systolic array, and a complex control algorithm is realized with low resource occupation.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention provides an instruction execution method, a processor, electronic equipment and a storage medium, the method is applied to the processor, the processor comprises a first execution unit, a second execution unit and a pipeline register, and a first execution instruction of an atomic instruction group is obtained through the first execution unit; writing a first execution result of the first execution instruction into the pipeline register in response to the first execution instruction; a second execution instruction of the atomic instruction group is obtained through the second execution unit, and the first execution result is read from the pipeline register as the source operand of the second execution instruction in response to the second execution instruction, so that the instruction execution method, the processor, the electronic equipment and the storage medium can reduce the access frequency of the general register and improve the access efficiency of the general register. Processor power consumption and register port conflicts can be reduced.

The invention provides a multiply-accumulate operation method and device for extremely low precision training, and the method comprises the steps: obtaining an operated part and to-be-operated data, and the to-be-operated data comprises one or more of floating point, fixed point and logarithm data formats; if the high-precision floating-point number exists in the data to be calculated, decomposing the high-precision floating-point number into the sum of two low-precision floating-point numbers; floating-point, fixed-point and logarithm data formats in the data to be calculated are decoded to be uniform formats of symbols, indexes and mantissas, and input data in the uniform formats are generated; performing multi-term dot product on the input data with the unified format to realize combined calculation of data formats with different precision; and adding the combined calculation result and the calculated part sum by adopting an advanced random rounding method. The method can support the combined calculation among various formats, reduces the bit width of the accumulator on the premise of maintaining the precision requirement by using an advanced random rounding method, and reduces the operation cost and improves the training efficiency under extremely low precision compared with the existing operation hardware.

The invention provides a data storage position dynamic optimization method, device and equipment and a storage medium, and the method comprises the steps: connecting expansion card equipment with a GPU through a PCIe interface on the GPU, and carrying out BDF structure scanning and space mapping to obtain storage space configuration information; preprocessing a shared keyword code segment of the GPU kernel function code and inserting an expansion card identifier, and configuring data transmission parameters to obtain initial configuration of a CUDA shared storage mechanism; the method comprises the following steps of: partitioning a running capacity region and a high-speed cache region of a storage space of expansion card equipment, and performing thread synchronization and parallel calculation on to-be-operated data of a GPU (Graphics Processing Unit) through SLC (Single Level Cell) data block partitioning to obtain running state information of the storage space; and dynamically migrating the distribution of the to-be-operated data between the operation capacity region and the cache region according to the operation state information. By dynamically optimizing the data storage position, the utilization rate of storage resources is improved, the data access delay is reduced, the GPU computing process is accelerated, and the overall system performance is improved.

The invention discloses an inter-thread operand collection strategy and an application system, and relates to the technical field of cross-thread data sharing of a GPGPU (General Purpose Graphics Processing Unit). In order to solve the problems of read-write delay and cache occupation caused by synchronous operation of the GPGPU in a data sharing scene, the scheme adopted by the invention comprises a decoding unit, a transmitting unit and a write-back unit, and the three units cooperate with one another to form a complete cross-thread data read-write path. Wherein the decoding unit is responsible for decoding a self-defined instruction and remapping a thread index; the transmitting unit undertakes the tasks of instruction caching, data synchronization control and cross-thread data reading; and the write-back unit is responsible for writing an instruction execution result back to the storage space and updating the state of a related register. According to the method, the parallel performance of the GPGPU in a multi-thread parallel computing scene can be improved.

Methods and systems relating to computational hardware are disclosed herein. One disclosed method for executing a multiplication computation using a computational hardware block includes storing a first operand and a second operand for the multiplication computation. The first operand includes a first set of bit strings. The second operand includes a second set of bit strings. The method also includes multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational hardware block. Each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings. A cardinality of the set of temporal phases is determined by a fidelity control value. The fidelity control value adaptively sets a fidelity of execution of the multiplication computation.

The invention discloses a security protection method based on an SM9 signature algorithm, operation time is determined according to the value of a random number, the operation time is random, in addition, point multiplication operation time is also random, and timing attacks can be resisted; according to the method, secret key masking operation is carried out on a private key of a user, meanwhile, randomization operation is carried out on operands of point multiplication in point multiplication operation, the private key is not leaked in the process of adopting an NAF point multiplication operation algorithm and a signature algorithm, and meanwhile, full-process masking is carried out in the middle process, so that power consumption, electromagnetism and secret key information have no correlation; energy power consumption and electromagnetic attack can be resisted; whether related parameter variables are tampered or whether errors are injected or not can be detected by comparing hash operation before algorithm starting and point multiplication operation; in addition, after signature is completed, verification operation is carried out on the signature value once, whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and fault attacks can be resisted.

The invention provides an atomic instruction execution method and device, relates to the technical field of computers, and is used for improving the expandability of atomic instructions. The method comprises the steps that an atomic instruction is obtained, the atomic instruction comprises first instruction information, and the first instruction information is used for indicating at least one of an address register, a source register and a destination register; wherein the address register is used for storing an address to be operated, and the source register is used for storing an operand; respectively acquiring the address to be operated and the operand from the address register and the source register according to first instruction information; and executing an atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and storing an obtained execution result in the destination register.

Embodiments of the invention provide a compiling method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of converting a branch instruction in a target function into a control flow pseudo instruction related to an architecture of a compiler; performing a first instruction processing operation on any control flow pseudo instruction, and performing a second instruction processing operation on a vector instruction of which the operand type corresponding to the operand is a first preset type; and under the condition that the operand type corresponding to the operand of the control flow pseudo instruction or the vector instruction is a second preset type, determining a target physical predicate register and replacing the virtual predicate register corresponding to the control flow pseudo instruction or the vector instruction with the target physical predicate register. In this way, the number of the generated instructions is reduced, and the running efficiency of the program is improved to a certain extent. The target physical predicate registers are respectively distributed for different control flows, so that the overall execution efficiency of the program is improved, and the parallel execution capability and throughput of the program are improved.

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

The invention discloses a data format conversion method and device, data format conversion equipment and a medium. The method is executed by a data format conversion device and comprises the steps of obtaining an input operand and a format conversion standard; according to the input operand and the format conversion standard, any one of the following items is executed: when the input operand is in a first floating point data format, the input operand is converted into an output operand according to a rounding mode, a second floating point data format and each standard output data format supported by the data format conversion equipment; when the input operand is in the first integer data format, the input operand is converted into an output operand according to the second integer data format and each output data format supported by the data format conversion device. By the adoption of the technical scheme, in the data format conversion process, it can be avoided that the intermediate data format is referenced, the data format conversion logic is simplified, and the problem that in the prior art, the bit width of the intermediate data format is large is solved.

The invention provides a universal Transform acceleration method and system based on floating point instruction set extension, and the method comprises the steps: constructing a multiplier which comprises a plurality of stages of adders and a 4-Booth coding algorithm which are connected in sequence, and coding data; the coded data is operated through a plurality of stages of adders in sequence to obtain the output of a multiplier; the construction of the floating-point number register comprises the following specific steps: adding a floating-point number register group, generating the floating-point number register group, enabling input result register indexes to correspond to respective register numbers by writing port logic of the floating-point number register group, generating a writing enable signal, writing data into the register by an enabled general register, and writing the data into the floating-point number register group. The read port is realized by using a multi-path parallel selector, and a selection signal of the multi-path parallel selector is an index of a read operand register; and the RISC-V processor accelerates the operation of the Transform neural network based on the constructed multiplier and the floating-point number register.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

There is provided an apparatus, a system, a chip containing product, a method and a medium, the apparatus comprises decoder circuitry responsive to a floating point accumulate instruction identifying pairs of floating point operands and an accumulation source, and processing circuitry comprising a plurality of arithmetic combination units to perform an arithmetic operation to combine the pairs of operands, and summation circuitry to perform an arithmetically precise summation operation to calculate an intermediate result by summing results generated by the arithmetic combination units. The intermediate result is independent of an order in which the arithmetic results are summed. The processing circuitry comprises accumulation circuitry to accumulate the intermediate result into the accumulation source and rounding circuitry to perform a rounding operation after accumulating, and is configured to propagate additional precision information relating to the arithmetic results, the intermediate result, and / or the prior accumulation value to the rounding circuitry.

The invention discloses an approximate floating point multiplier, a chip and computing equipment, an approximate mantissa multiplier of the approximate floating point multiplier comprises an AND logic unit and a compressor unit, and the AND logic unit is used for performing AND operation on two input operands bit by bit to generate a partial product array with the size of 11 rows and 21 columns; the compressor unit is used for compressing the 11th column to the 21st column by column to obtain a final approximate mantissa, the compressor unit comprises two novel approximate 4-2 compressors ignoring carry design, and the error rate of the approximate 4-2 compressors is within an acceptable range by utilizing mutual compensation inside the compressors. The invention aims to excavate and use the characteristics of floating point multiplication to further improve the energy efficiency of floating point multiplication, realize the optimization of the approximate floating point multiplier in the overhead aspects of precision, power consumption, area and the like, and solve the problems of relatively complex circuit and low compression efficiency of the traditional approximate 4-2 compressor.

Multiply and accumulate (MAC) operations typically involve extremely large amounts of data and large numbers of operations. As such, they are extremely computationally intensive, involving large numbers of data transfers and consuming large amounts of time and power. To address these problems, the following presents methods of realizing a MAC engine in a 3D NAND flash die. The engine takes as input two vectors and outputs their dot product. The dot product of two vectors is the building block of matrix multiplication. The 3D NAND MAC engine presented here can be used to implement modern machine learning algorithms, in particular Neural Networks. The two vector operands are not programed into the NAND memory cells, therefore the endurance of the device is not compromised.

The invention relates to an instruction identification method and device, equipment, a readable storage medium and a program product. The method comprises the steps of obtaining a target natural language text and a target instruction library set; identifying a target index word of the target natural language text, and if the target index word is a preset index word, determining at least one candidate instruction from a target instruction library set according to the target index word; determining a conversion operand for converting the target natural language text into each candidate instruction, and determining the similarity between the target natural language text and the corresponding candidate instruction according to each conversion operand; and determining a target instruction of which the similarity is within a preset threshold range from the at least one candidate instruction according to the similarity. By adopting the method, the accuracy of instruction identification can be improved.

The SRT operational circuit comprises an input module, a floating point conversion module, a calculation module and an output module, the input module is configured to output an initial operand, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; if the calculation module is configured to perform division operation or root extraction operation by adopting the first operand based on the SRT algorithm, the output module is configured to perform mantissa rounding on a division result or a root extraction result after the calculation of the calculation module is completed and output a floating point result, so that the operation accuracy of an integer in the circuit is improved, and the universality of the circuit is improved.

A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

The invention provides a vector instruction processing method, electronic equipment, a readable medium and a program product. The vector instruction processing method comprises the steps of obtaining a vector length of a vector instruction; when the vector length of the vector instruction is the first value and the effective indication of the second source operand is the first value, cancelling the transmission of the vector instruction, and setting the effective indication of the second source operand as a second value; a first value of the second source operation valid indication indicates that the old value of the destination register is not required as a valid indication of the second source operand, and a second value of the second source operation valid indication indicates that the old value of the destination register is required as a valid indication of the second source operand; under the condition that the destination register is ready, retransmitting the vector instruction; a first source operand and a second source operand are obtained based on the vector instruction, and the vector instruction is executed based on the first source operand and the second source operand, the second source operand being an old value of the destination register.

Systems and methods related to vector mask buffers in a vector instruction execution pipeline are disclosed herein. The vector instruction execution pipeline may include several lanes. Each lane may include a vector register file, a vector mask buffer, and a functional processing unit. The vector register file may store operand data and the vector mask buffer may store a vector mask associated with the operand data. In a lane, the operand data may be read from the register file into a functional processing unit, and the vector mask may be read from the vector mask buffer to the functional processing unit. The functional processing unit may process the operand data based on the vector mask. The lane-specific vector mask buffers improve the efficiency of the vector instruction execution pipeline by storing the vector masks proximate to where the vector masks will be used.

A computer implementation method for obtaining a lower triangular matrix for a matrix multiplication result value, the method comprising: a process of allocating elements of each of a first operand matrix pair and a second operand matrix pair input into a memory to calculation units of an accelerator; and a process of the calculation units of the accelerator performing a matrix multiplication calculation on the elements of the first operand matrix pair and the second operand matrix pair, wherein the process of allocating the elements thereof to the calculation units of the accelerator comprises: allocating elements of the first operand matrix pair to first calculation units corresponding to elements of the lower triangular matrix for the matrix multiplication result value of the first operand matrix pair; and allocating elements of the second operand matrix pair to second calculation units corresponding to elements of the lower triangular matrix for the matrix multiplication result value of the second operand matrix pair.

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

The invention relates to an artificial intelligence chip, a method for parallel vector and scalar execution assembly lines, a computing device, a medium and a program product. The artificial intelligence chip comprises an execution unit, the execution unit is configured with a vector execution assembly line and a scalar execution assembly line, and the scalar execution assembly line at least comprises a scalar instruction decoding unit which is configured to at least obtain an operand type, address information and scalar operation control information of a scalar instruction; a scalar instruction operand acquisition unit configured to acquire an operand source of a scalar instruction; and a scalar instruction operation unit configured to execute scalar calculation at least based on an operand type, an operand source and scalar operation control information of the scalar instruction, and write a calculation result to the scalar register group included in the execution unit. According to the method, the utilization rate and the actual computing power of hardware resources of the execution unit of the artificial intelligence chip can be remarkably improved.