1093 results about "Operand" patented technology

The invention discloses an instruction execution acceleration method based on a GPGPU and a GPGPU architecture, and relates to the field of high-performance computation.The method comprises the steps that a thread execution task output by a host compiler is received, and the thread execution task is scheduled according to the current idle state of a computing unit; capturing instruction data output by the host compiler, and executing concurrent instruction decoding according to the corresponding instruction type to obtain a machine code corresponding to the instruction data; obtaining an operand corresponding to the instruction data, and generating a to-be-transmitted instruction based on the machine code corresponding to the instruction data and the operand after secondary verification; according to the calculation complexity, determining an optimal calculation unit, and sending the to-be-launched instruction to the optimal calculation unit; and receiving an execution result of the to-be-transmitted instruction, and returning the execution result to the terminal. The thread execution task is dynamically scheduled according to the idle state of the computing unit, so that computing resources can be fully utilized, and the operation efficiency is improved.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: calling a preset instruction if a current instruction is recognized as an indirect jump instruction; the instruction code of the preset instruction comprises a first operand and a second operand; the first operand points to the first register, and the second operand points to the second register; the target PC value is stored in the first register; the second register is used for storing a calculation result of the preset instruction; the preset instruction executes preset calculation logic to calculate a target index value corresponding to the target PC value in the hash table, and the target index value is written into a second register; the target index value is read from the second register, whether the target PC value hits the hash table or not is inquired through the target index value, and the next instruction is executed based on the inquiry result. According to the embodiment of the invention, the instruction translation number of the high-frequency instruction can be reduced, and the execution efficiency of the binary translator is improved.

The invention discloses mixed precision multiply-add operation hardware, which comprises an input processing unit used for obtaining standard symbols, standard indexes and standard mantissas according to a pre-configured input format and unpacked input multiply-add operation factors, and obtaining input and output special value detection results; the floating point multiplier-adder is used for calculating an operation result after the operand multiplies the scaling factor and the offset is accumulated according to the symbol, the exponent and the mantissa of each multiplication-addition operation factor; and the output processing unit is used for obtaining a target format result according to a pre-configured output format, a rounding type and a normalization and rounding operation result, packaging the target format result according to a detection result and outputting the target format result, and by multiplexing a data path of the floating-point multiplier-adder, the chip area is saved, format conversion is integrated, a data stream is simplified, and the data processing efficiency is improved. The requirements for automatic reconstruction of the multiply-add operation unit according to input and output formats and quantization and inverse quantization of floating points and integers are met, and the reuse rate of computing resources is increased.

Systems and methods for generating fixed function shared accelerators (FFSAs) implement and / or comprise operations of receiving source code, the source code indicating a plurality of workloads to be performed by an electronic circuit; generating a plurality of abstract syntax trees (ASTs) based on the source code, wherein respective ones of the plurality of ASTs include a plurality of nodes corresponding to function instructions; generating a plurality of fingerprinting vectors corresponding to the plurality of ASTs, wherein respective ones of the plurality of fingerprinting vectors encode at least one of a number of nodes, a number of edges, a density, a computation intensity, an operands percentage, a control, or a data dependency; and providing the plurality of fingerprinting vectors to a machine learning (ML) model, wherein the ML model is configured to predict similarities between different ones of the plurality of workloads and to output at least one candidate FFSA.

In one embodiment, an apparatus comprises a cache to store a plurality of instructions and data associated with a trusted execution environment; instruction processing circuitry to execute the plurality of instructions and process the data, the plurality of instructions including one or more instructions with memory operands, wherein responsive to an interrupt or an exception, the instruction processing circuitry is to pause processing the plurality of instructions and execute a handler; and decode circuitry to partially decode a next instruction of the plurality of instructions to be processed following execution of the handler to determine if the next instruction indicates a memory access and, if so, to calculate at least one corresponding memory address, wherein the partial decode is performed in accordance with one or more constant time programming restrictions.

The invention belongs to the field of high-performance computing, and relates to an integer parallel computing method and device based on distributed storage and computer equipment, and the method comprises the steps of collecting real-time resource indexes, dynamically identifying fault nodes, triggering task migration, and performing data verification and hard disk fault detection. The weight value of each node is calculated, the nodes are arranged according to the descending order of the weight values, and the nodes with high load capacity are selected to distribute tasks; dynamically distributing a data generation task to a computing node, executing parallel computing, and performing distributed storage on a result; obtaining an operand, converting the operand into a first-order tensor form of a basic operand, serializing tensor data, and sending the serialized tensor data to a parallel computing layer; distributing a search task to a computing node, retrieving storage data in parallel, reading effective data from a storage layer, and combining search results into a partial sum; and summarizing and then outputting. The system has dynamic resource management and fault-tolerant capabilities, and can realize efficient task allocation and load balancing.

Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.

The invention discloses a model processing method, a chip assembly and equipment. The method comprises the following steps: an in-memory computing element performs first operation processing on input data to obtain first processing data; wherein the first operation processing comprises fixed weight calculation of an operand; the near memory computing element performs second operation processing on the first processing data to obtain second processing data; wherein the second operation processing at least comprises attention calculation of operand change. Thus, heterogeneous deployment of model parameters of the model can be realized based on cooperation of the in-memory computing element and the near-memory computing element, the in-memory computing element can realize weight calculation of fixed operands, and the near-memory computing element can realize attention calculation of operand changes. The characteristics of high computing power efficiency and low power consumption of the in-memory computing element can be utilized to the greatest extent, the erasing operation on the in-memory computing element can be reduced by means of the near-memory computing element, and the application performance of a model deployed on the equipment side can be effectively improved.

The invention relates to the technical field of compiling, in particular to a byte code file optimization method and device, a byte code file execution method and device and an intelligent card. The method comprises the following steps: acquiring a byte code file to be optimized; bytecode instructions in the bytecode file are traversed in sequence, target bytecode instructions are obtained based on instruction operation codes of the target bytecode instructions, and target operand information carried in the target bytecode instructions is obtained according to instruction types of the target bytecode instructions, determining an operand storage area corresponding to the instruction type; determining an index of each piece of target operand information in the corresponding operand storage area to obtain each corresponding target index value; and according to each target index value and a preset index value length, repackaging the corresponding target bytecode instruction to obtain an optimized bytecode file. Therefore, the problem that an executable bytecode file of an existing intelligent card application occupies a large space can be effectively solved.

The invention relates to the technical field of microprocessor structures, and discloses a protocol calculation method, an engine, computer equipment, a storage medium and a program product.The protocol calculation engine comprises an instruction receiving module used for receiving a protocol instruction sent by a core; the instruction splitting module is used for splitting the protocol instruction into a read request and a write request; the read request processing module is used for reading an operand corresponding to the read request from the draft book storage module; and the write request processing module is used for executing protocol calculation on the operand according to the protocol instruction to obtain a calculation result, and writing the calculation result into a draft book for storage. The protocol calculation engine specially used for protocol calculation is designed, and the protocol calculation instruction is executed asynchronously, so that compared with a traditional VPU form, the occupied chip area is small, the calculation efficiency is high, judgment is completed through answer words, and programming is convenient.

An apparatus for facilitating support of 8-bit floating point format operands in a computing architecture is disclosed. In one embodiment, the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, where the decoded instruction is a matrix instruction that operates on an 8-bit floating point operand to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for an 8-bit floating point operand according to an 8-bit floating point data format indicated by the decoded instruction; and a pulsation dot product circuit to execute the decoded instruction using pulsation layers, each pulsation layer comprising one or more sets of interconnected multipliers, shifters and adders, each set of multipliers, shifters and adders to generate a dot product of 8-bit floating point operands.

The invention provides a collaborative computing method, system and device based on SIMD and SIMT, and belongs to the technical field of computer processing. The method is applied to a Warp composed of a plurality of SPs, and the Warp comprises an SIMT front end and an SIMD rear end. Each SP corresponds to a vector register combined by a plurality of short registers; generating instruction fetching indication information under the condition that a thread bundle scheduler at the front end of the SIMT determines that a first thread bundle corresponding to the calculation task is in an activated state; obtaining a first cache instruction corresponding to the first thread bundle through an instruction fetching unit, and sending the first cache instruction to a decoding unit at the front end of the SIMT for analysis; obtaining one or more corresponding required operands through an operand collection unit at the rear end of the SIMD; and distributing the required operands to the corresponding calculation management units through the SIMD rear end to execute the corresponding calculation tasks, and writing the calculation results corresponding to the calculation tasks back to the storage unit through the write-back unit.

The invention discloses a reconfigurable systolic array tensor IP core based on an FPGA. The architecture comprises a core controller, a shift distributor, a data processing array and a four-stage data cache. The tensor core can adapt to general tensor multiplication and addition operations in Prefill and Decode stages of the generative neural network at the same time through reconfigurable design. The core controller receives the tensor multiplication instruction and the configuration information and decouples the tensor multiplication instruction and the configuration information according to a data stream to generate a plurality of block tensor multiplication instructions. The shift distributor decodes a block tensor multiplication instruction, decoded mode information controls data communication between a first-level cache and a second-level cache (Distrided RAM and Bram), a control signal of a data processing array is generated, and the control signal enters the array together with data to flow. And the data processing array is connected with different secondary BRAM caches according to the received configuration information and is used for processing data in a bubble-free pulsating flow manner. The four-stage data cache realizes the multi-stage pinpong operation of the loading of the operation data of the tensor operation core, and realizes the multi-stage pipeline design of the data from the off-chip HBM to the on-chip URAM, from the URAM to the BRAM and from the BRAM to the operation unit. Aiming at a single-user edge end generation type network reasoning task, a core controller generates a data processing unit mode configuration signal in a fine-grained (tensor element level) manner, and the data processing unit mode configuration signal is transmitted by a shift distributor and flows in parallel with operation data, so that the mode configuration efficiency and the hardware resource utilization rate are greatly improved, the problem of high fan-out caused by broadcast control is reduced, and the user experience is improved. A control flow is designed by means of the structural characteristics of the systolic array, and a complex control algorithm is realized with low resource occupation.

The embodiment of the invention discloses a taint analysis method and device, computer equipment and a storage medium, and belongs to the technical field of information security. In the application, the coprocessor of the computer equipment comprises a plurality of registers, and the plurality of registers not only can be used for storing stain information corresponding to a plurality of general registers in a main processor of the computer equipment, but also can be used for storing stain information corresponding to a program memory space of a target program currently executed by the main processor. Therefore, when the coprocessor performs taint propagation on the first instruction, the taint information of the operand of the first instruction can be accessed by accessing the plurality of registers, and compared with the mode of accessing the taint information by accessing a memory, the operation is simpler, the speed is faster, and the performance overhead is smaller.

In some examples, a method of performing matrix multiplication using mixed precision decomposition of operands includes converting a first matrix including a plurality of elements having a first precision to a second matrix, where the second matrix includes a plurality of elements having a second precision, the second precision being lower than the first precision; generating a first output matrix comprising a product of the second matrix and a third matrix, where the third matrix comprises a plurality of elements having the second precision, the elements of the first output matrix being stored at the first precision or converted to the first precision; calculating a residual value matrix using the first matrix and the second matrix, where the residual value matrix comprises elements representing respective differences between elements of the first matrix and elements of the second matrix; the elements of the residual matrix are scaled using a first scaling factor to generate a first scaled matrix.

A disclosed approximate tensor processing unit (APTPU) includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU's systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. Performance of the disclosed APTPU across various configurations and various workloads shows that the disclosed APTPU's systolic array achieves delay, area, and power reductions, while realizing comparable accuracy to previous designs.

The invention discloses a floating point addition implementation method and device for mixed precision operation and electronic equipment. The method comprises the steps of performing mild preprocessing on two low-precision operands of floating point addition operation; if the improved near-path condition is met, leading zero prediction and mantissa addition operation are carried out on the two operands in parallel, a near-path operation result is obtained, and the number of leading zeros comprises the number of leading zeros subjected to floating-point number addition mantissa high-order offset and the number of non-normalized leading zeros; if the improved near-path condition is not met, performing far-path order shifting and mantissa addition operation on the two operands to obtain a far-path operation result; and selecting one as an operation result to carry out mantissa rounding and normalized shifting to obtain a high-precision floating point addition operation result. Through the above mode, according to the embodiment of the invention, normalized calculation with improved precision and existing near-path calculation can be combined into one, floating point additive operation resource reuse and delay elimination are realized, and the execution efficiency is improved.

The invention provides a parallel optimization method and system for a GPGPU (General Purpose Graphics Processing Unit) instruction execution stage, and the method comprises the steps: splitting an input instruction into a plurality of sub-instructions which can be independently scheduled based on an instruction type, operand dependency analysis and a hardware resource real-time state, and generating a dependency table to record the input and output association of the sub-instructions; acquiring real-time load data of the calculation unit, the storage unit and the communication unit, and distributing the sub-instructions to the calculation unit, the storage unit or the communication unit by adopting a priority dynamic adjustment algorithm and combining instruction key path analysis; according to the dependency relationship of the sub-instructions and the availability of hardware resources, the execution sequence of the sub-instructions is adjusted to maximize the degree of parallelism; and analyzing the dependency relationship among the sub-instructions in real time to maximize the degree of parallelism to dynamically adjust a parallel execution strategy so as to realize serial execution of dependent instructions and parallel execution of non-dependent instructions. According to the method, the complexity of instruction compiling is reduced, the efficiency of instruction compiling is improved, and meanwhile extra consumed time is reduced.

The invention provides an instruction execution method, a processor, electronic equipment and a storage medium, the method is applied to the processor, the processor comprises a first execution unit, a second execution unit and a pipeline register, and a first execution instruction of an atomic instruction group is obtained through the first execution unit; writing a first execution result of the first execution instruction into the pipeline register in response to the first execution instruction; a second execution instruction of the atomic instruction group is obtained through the second execution unit, and the first execution result is read from the pipeline register as the source operand of the second execution instruction in response to the second execution instruction, so that the instruction execution method, the processor, the electronic equipment and the storage medium can reduce the access frequency of the general register and improve the access efficiency of the general register. Processor power consumption and register port conflicts can be reduced.

The invention provides a multiply-accumulate operation method and device for extremely low precision training, and the method comprises the steps: obtaining an operated part and to-be-operated data, and the to-be-operated data comprises one or more of floating point, fixed point and logarithm data formats; if the high-precision floating-point number exists in the data to be calculated, decomposing the high-precision floating-point number into the sum of two low-precision floating-point numbers; floating-point, fixed-point and logarithm data formats in the data to be calculated are decoded to be uniform formats of symbols, indexes and mantissas, and input data in the uniform formats are generated; performing multi-term dot product on the input data with the unified format to realize combined calculation of data formats with different precision; and adding the combined calculation result and the calculated part sum by adopting an advanced random rounding method. The method can support the combined calculation among various formats, reduces the bit width of the accumulator on the premise of maintaining the precision requirement by using an advanced random rounding method, and reduces the operation cost and improves the training efficiency under extremely low precision compared with the existing operation hardware.

The invention provides a data storage position dynamic optimization method, device and equipment and a storage medium, and the method comprises the steps: connecting expansion card equipment with a GPU through a PCIe interface on the GPU, and carrying out BDF structure scanning and space mapping to obtain storage space configuration information; preprocessing a shared keyword code segment of the GPU kernel function code and inserting an expansion card identifier, and configuring data transmission parameters to obtain initial configuration of a CUDA shared storage mechanism; the method comprises the following steps of: partitioning a running capacity region and a high-speed cache region of a storage space of expansion card equipment, and performing thread synchronization and parallel calculation on to-be-operated data of a GPU (Graphics Processing Unit) through SLC (Single Level Cell) data block partitioning to obtain running state information of the storage space; and dynamically migrating the distribution of the to-be-operated data between the operation capacity region and the cache region according to the operation state information. By dynamically optimizing the data storage position, the utilization rate of storage resources is improved, the data access delay is reduced, the GPU computing process is accelerated, and the overall system performance is improved.

The invention discloses an inter-thread operand collection strategy and an application system, and relates to the technical field of cross-thread data sharing of a GPGPU (General Purpose Graphics Processing Unit). In order to solve the problems of read-write delay and cache occupation caused by synchronous operation of the GPGPU in a data sharing scene, the scheme adopted by the invention comprises a decoding unit, a transmitting unit and a write-back unit, and the three units cooperate with one another to form a complete cross-thread data read-write path. Wherein the decoding unit is responsible for decoding a self-defined instruction and remapping a thread index; the transmitting unit undertakes the tasks of instruction caching, data synchronization control and cross-thread data reading; and the write-back unit is responsible for writing an instruction execution result back to the storage space and updating the state of a related register. According to the method, the parallel performance of the GPGPU in a multi-thread parallel computing scene can be improved.

Methods and systems relating to computational hardware are disclosed herein. One disclosed method for executing a multiplication computation using a computational hardware block includes storing a first operand and a second operand for the multiplication computation. The first operand includes a first set of bit strings. The second operand includes a second set of bit strings. The method also includes multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational hardware block. Each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings. A cardinality of the set of temporal phases is determined by a fidelity control value. The fidelity control value adaptively sets a fidelity of execution of the multiplication computation.

The invention discloses a security protection method based on an SM9 signature algorithm, operation time is determined according to the value of a random number, the operation time is random, in addition, point multiplication operation time is also random, and timing attacks can be resisted; according to the method, secret key masking operation is carried out on a private key of a user, meanwhile, randomization operation is carried out on operands of point multiplication in point multiplication operation, the private key is not leaked in the process of adopting an NAF point multiplication operation algorithm and a signature algorithm, and meanwhile, full-process masking is carried out in the middle process, so that power consumption, electromagnetism and secret key information have no correlation; energy power consumption and electromagnetic attack can be resisted; whether related parameter variables are tampered or whether errors are injected or not can be detected by comparing hash operation before algorithm starting and point multiplication operation; in addition, after signature is completed, verification operation is carried out on the signature value once, whether all parameter variables and intermediate variables are tampered or whether errors are injected in the whole-process operation can be detected, and fault attacks can be resisted.

The invention provides an atomic instruction execution method and device, relates to the technical field of computers, and is used for improving the expandability of atomic instructions. The method comprises the steps that an atomic instruction is obtained, the atomic instruction comprises first instruction information, and the first instruction information is used for indicating at least one of an address register, a source register and a destination register; wherein the address register is used for storing an address to be operated, and the source register is used for storing an operand; respectively acquiring the address to be operated and the operand from the address register and the source register according to first instruction information; and executing an atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and storing an obtained execution result in the destination register.

Embodiments of the invention provide a compiling method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of converting a branch instruction in a target function into a control flow pseudo instruction related to an architecture of a compiler; performing a first instruction processing operation on any control flow pseudo instruction, and performing a second instruction processing operation on a vector instruction of which the operand type corresponding to the operand is a first preset type; and under the condition that the operand type corresponding to the operand of the control flow pseudo instruction or the vector instruction is a second preset type, determining a target physical predicate register and replacing the virtual predicate register corresponding to the control flow pseudo instruction or the vector instruction with the target physical predicate register. In this way, the number of the generated instructions is reduced, and the running efficiency of the program is improved to a certain extent. The target physical predicate registers are respectively distributed for different control flows, so that the overall execution efficiency of the program is improved, and the parallel execution capability and throughput of the program are improved.

The embodiment of the invention provides a processor random verification program generation method and device, equipment and a storage medium, and the method comprises the steps: generating a target processing instruction for a target instruction which may generate an unpredictable execution result during loop execution in a loop instruction sequence; inserting the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used for processing an operand in a source register of the target instruction before the target instruction is executed in each cycle execution process, so that the target instruction generates a predictable execution result in the cycle process. Thus, the execution result of the target instruction in the loop instruction sequence can be predicted, it is not needed to avoid the instruction with the execution result unpredictable in the instruction sequence, the instruction types in the loop instruction sequence are enriched, the verification efficiency of the microprocessor is improved, and the verification efficiency of the microprocessor is improved. And the quality of the random verification program and the convergence speed of the function verification coverage rate are improved.

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

The invention discloses a data format conversion method and device, data format conversion equipment and a medium. The method is executed by a data format conversion device and comprises the steps of obtaining an input operand and a format conversion standard; according to the input operand and the format conversion standard, any one of the following items is executed: when the input operand is in a first floating point data format, the input operand is converted into an output operand according to a rounding mode, a second floating point data format and each standard output data format supported by the data format conversion equipment; when the input operand is in the first integer data format, the input operand is converted into an output operand according to the second integer data format and each output data format supported by the data format conversion device. By the adoption of the technical scheme, in the data format conversion process, it can be avoided that the intermediate data format is referenced, the data format conversion logic is simplified, and the problem that in the prior art, the bit width of the intermediate data format is large is solved.

The invention provides a universal Transform acceleration method and system based on floating point instruction set extension, and the method comprises the steps: constructing a multiplier which comprises a plurality of stages of adders and a 4-Booth coding algorithm which are connected in sequence, and coding data; the coded data is operated through a plurality of stages of adders in sequence to obtain the output of a multiplier; the construction of the floating-point number register comprises the following specific steps: adding a floating-point number register group, generating the floating-point number register group, enabling input result register indexes to correspond to respective register numbers by writing port logic of the floating-point number register group, generating a writing enable signal, writing data into the register by an enabled general register, and writing the data into the floating-point number register group. The read port is realized by using a multi-path parallel selector, and a selection signal of the multi-path parallel selector is an index of a read operand register; and the RISC-V processor accelerates the operation of the Transform neural network based on the constructed multiplier and the floating-point number register.