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12 results about "Boolean expression" patented technology

In computer science, a Boolean expression is used expression in a programming language that produces a Boolean value when evaluated, that is one of true or false. A Boolean expression may be composed of a combination of the Boolean constants true or false, Boolean-typed variables, Boolean-valued operators, and Boolean-valued functions.

Systems and methods for optimizing compound rule execution for big data

Systems and methods for uses and / or improvements to executing complex multi-step rule execution against big data. Prompts may be parsed to extract rule sets formed of Boolean expressions. These rules can be executed individually against datasets and the results of the rules can be cached. The cached results can be used upon generation of a compound rule, thereby enabling a simplified execution of custom rules. The techniques further resolve issues involving evaluations of various expression subgroupings and logical operators, while also improving performance by eliminating duplicate rule execution and circular dependencies.
Owner:CAPITAL ONE SERVICES LLC

Photonic logic gate

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.
Owner:刘国栋

Multiple index scans

Techniques are disclosed relating to implementing multiple index scans. A computer system may store a database table comprising fields and indexes corresponding to those fields. The computer system may receive a request to access records based on a Boolean expression that affects a selection of records from the database table and that comprises clauses, at least two of which are joined by an AND operation. The computer system may access the requested records. The accessing may include, for a given one of the at least two clauses, performing an index scan on an index that corresponds to the given clause to identify records that satisfy that clause. The computer system may update a hash table based on the identified records and then identify the requested records based on the hash table. The Boolean expression may include clauses joined by an OR operation that are processed using multiple index scans.
Owner:SALESFORCE INC

A filtering condition rewriting method, device, equipment, medium and product

The application provides a filtering condition rewriting method, device, equipment, medium and product, comprising: obtaining a filtering condition; when the filtering condition meets an optimization condition, splitting the filtering condition into a condition unit; when the condition unit is a Boolean expression containing a column name and a constant, determining a current partition table in which a target column corresponding to the column name is located and a current partition column of the current partition table, determining an optimization mark of the condition unit by comparing the current partition column with the target column; if the optimization mark of the condition unit is first mark information and a partition base table of the current partition table of the condition unit is a range partition table, obtaining the constant and a comparison operator in the condition unit, selecting a current lower-level partition table from lower-level partition tables of the partition base table, and determining optimization indication information of the condition unit according to the constant, the comparison operator and partition information of the current lower-level partition table; and rewriting based on the optimization indication information to obtain a rewritten filtering condition. The method improves the query efficiency of the filtering condition.
Owner:SHANGHAI DAMENG DATABASE

Interlocking Boolean logic graphical display method and system

The invention discloses an interlocking Boolean logic graphical display method and system. The method comprises the steps that an interlocking Boolean logic source code file is read on a graphical user interface of a computer; analyzing the interlocking Boolean logic source code file, splitting each Boolean expression in the interlocking Boolean logic source code file to obtain the split Boolean expressions, and displaying each split Boolean expression on the graphical user interface; according to each split Boolean expression, generating an expression graph corresponding to the Boolean expression on the graphical user interface; each expression graph is stored in a vector diagram mode, the problem of software logic visualization pain points is solved, and the interlocking Boolean logic relation can be visually displayed; through the design of display elements, the understanding difficulty of signal personnel is reduced.
Owner:CASCO SIGNAL LTD

Correlation analysis expression index analysis method, device and electronic equipment

The application provides a correlation analysis expression index analysis method and device and electronic equipment. The method comprises the following steps: obtaining a correlation analysis expression to be analyzed; determining that the correlation analysis expression to be analyzed is a key Boolean expression and an indexable expression at the same time, and determining that the correlation analysis expression to be analyzed has an index, wherein the key Boolean expression is a Boolean expression capable of determining the value of the correlation analysis expression, each indexable expression comprises two identical single-table field expression, the flow table corresponding to each single-table field expression is mutually exclusive, and the fields in each single-table field expression belong to the same flow table. The performance of the correlation analysis can be improved based on the index analysis on the correlation analysis expression corresponding to the data flow, and the search efficiency of the data flow can be improved, thereby improving the efficiency of the network security analysis.
Owner:QI-ANXIN LEGENDSEC INFORMATION TECH (BEIJING) INC +1

Programmable sequence-driven hardware trigger for multiple FPGA system

Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware (“Debug FPGA”) that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.
Owner:CADENCE DESIGN SYST INC

A shared bicycle station site selection method based on density and in-out degree balance clustering

The application discloses a shared bicycle station site selection method based on density and in-out degree balance clustering, introduces an in-out balance coefficient, and performs clustering on a shared bicycle station candidate area through a composite clustering algorithm of the density and the balance coefficient; a GPS data set of the bicycle is taken as a sample point data set, the sample point data set is clustered by improving and combining the characteristics of a Clique grid clustering algorithm, a plurality of shared station candidate addresses are acquired, each shared station candidate address is optimized, and the best shared station address is determined by combining POI matching of the area. A Boolean expression is used to define complex attribute conditions in a formalized manner, and then a clustering result of the shared bicycle station under the complex attribute conditions is given based on the density and a threshold value. The application has high efficiency and accuracy, can perform data mining on massive user travel OD data, analyze hot spot gathering areas of bicycle user orders, provide good early data preparation for the bicycle station, and has the characteristics of lightness and flexibility.
Owner:BEIJING UNIV OF TECH

Data search method, apparatus, device, and medium

This application provides a data search method, apparatus, device, and medium. The method includes: selecting multiple target historical filtering conditions from a historical query dataset based on vector data of attribute data that satisfy various historical filtering conditions and the memory budget limit corresponding to the attribute vector dataset, with the goal of minimizing query cost; constructing sub-indexes corresponding to each target historical filtering condition based on the vector data of attribute data that satisfy each target historical filtering condition, and constructing a full index based on the multiple vector data; constructing an index dependency graph based on the sub-indexes and the full index; and, in response to a query request, selecting target vector data that semantically matches the query vector data and satisfies the query filtering conditions according to the query vector data and query filtering conditions carried in the query request, based on the index dependency graph. This allows for query filtering conditions based on arbitrary Boolean expressions, and features low index construction overhead, high efficiency, and controllable memory consumption.
Owner:北京数智引航科技有限公司

System and method for symbolic logic-based evaluation and composite descriptor generation

PCT designated stageWO2026062627A1Biological modelsKnowledge representationHeat mapLogic network
A computer-implemented method and system for symbolic logic-based evaluation are disclosed. Input data (e.g., responses, sensor feeds, or financial indicators) are normalized into symbolic parameters (pᵢ) through processor-executed routines. A clause engine evaluates Boolean expressions and records outcomes in a clause-truth registry. Weighted aggregation generates a composite descriptor (θ), with redundancy reduced through Karnaugh-map or equivalent logical simplification. Visualization modules—including θ gauges, flow diagrams, heatmaps, and logic networks—produce human- and machine-readable outputs that can interface with compliance APIs. Technical effects include reduced computational complexity, lower latency through incremental recomputation, and compliance-grade traceability. The invention is domain-agnostic, with applicability to education, healthcare (limited to monitoring and decision-support functions), finance, industrial IoT, cybersecurity, and enterprise analytics. Healthcare embodiments explicitly exclude diagnosis or treatment. All operations are processor-executed, producing compliance-linked outputs that extend beyond abstract algorithms, mental acts, or mere presentation of information.
Owner:GANESAN VASANTHARAJAN

Method and device for generating off-line data of railway trackside train control equipment

The invention discloses a method and a device for generating off-line data of railway trackside train control equipment. The method comprises the steps of obtaining railway related files corresponding to a target railway line, wherein the railway related files comprise a Boolean expression file, a Boolean variable table, an engineering data file, an interface file and a configuration file; generating a Boolean interface file corresponding to the target railway line according to the Boolean variable table and the interface file; generating an application data file corresponding to the target railway line according to the engineering data file, the interface file and the configuration file; inputting the Boolean expression file and the Boolean interface file into a preset Boolean tool, and generating a Boolean application file corresponding to the target railway line; determining application data corresponding to each trackside train control device according to the application data file; determining a plurality of Boolean variable data corresponding to each trackside train control device according to the Boolean application file; and generating off-line data of the target railway line according to the application data corresponding to each trackside train control device and the plurality of Boolean variable data.
Owner:CASCO SIGNAL (BEIJING) CO LTD

Methods of forming logic circuits with reduced transistor counts and computer-readable-medium for performing the same

A non-transitory computer-readable medium that includes computer-executable instructions for carrying out a method (of expanding a set of standard cells which comprise a library) including: identifying ad hoc groups of elementary standard cells which are recurrent (in a population of one or more layout diagrams) and each of which, as a whole, having a first number of transistors and a second number of logic gates; and selecting one of the ad hoc groups to provide a selected logical function which is representable as a Boolean expression; generating one or more macro standard cells each of which, as a whole, having a third number of components (representing transistors or logic gates in a context of the first or second numbers) which is smaller than the first number or the second number; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD