24 results about "Boolean expression" patented technology

Systems and methods for uses and / or improvements to executing complex multi-step rule execution against big data. Prompts may be parsed to extract rule sets formed of Boolean expressions. These rules can be executed individually against datasets and the results of the rules can be cached. The cached results can be used upon generation of a compound rule, thereby enabling a simplified execution of custom rules. The techniques further resolve issues involving evaluations of various expression subgroupings and logical operators, while also improving performance by eliminating duplicate rule execution and circular dependencies.

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.

The application discloses a conversion method and system from RSML ‑e model to Luster synchronous data flow language. ‑e The method converts RSML ‑e model into Luster, which involves type conversion, Boolean expression conversion, and-or table conversion, variable conversion, macro conversion and function conversion. Type conversion handles undefined values by creating enumerations and structs. Boolean expression conversion includes truth judgment, logical negation, previous state reference and equality judgment. and-or table conversion constructs sub-expressions by columns and connects them with logical or. Variable conversion is converted into Luster nodes, and ordinary variables and input variables are processed with initial values and conditions respectively. Macro and function conversion are converted into nodes with input and return values, and the contained logic is converted into Boolean expressions. The overall process realizes the mapping of RSML ‑e logic to Luster data flow, so that the safety properties of the system can be verified using model checking tools, improving system security.

The invention provides a filtering condition rewriting method and device, equipment, a medium and a product. The filtering condition rewriting method comprises the following steps: obtaining a filtering condition; when the filtering condition meets the optimization condition, the filtering condition is divided into condition units; when the condition unit is a Boolean expression containing a column name and a constant, determining a current partition table where a target column corresponding to the column name is located and a current partition column of the current partition table, and determining an optimization mark of the condition unit by comparing the current partition column with the target column; if the optimization mark of the condition unit is the first mark information and the partition base table of the current partition table of the condition unit is the range partition table, acquiring a constant and a comparison operator in the condition unit, selecting a current lower-level partition table from lower-level partition tables of the partition base table, and according to the constant, selecting the current lower-level partition table from the range partition table; comparing the operator with partition information of the current lower-level partition table, and determining optimization indication information of the condition unit; and rewriting based on the optimization indication information to obtain a rewritten filtering condition. According to the method, the query efficiency of the filtering condition is improved.

Techniques are disclosed relating to implementing multiple index scans. A computer system may store a database table comprising fields and indexes corresponding to those fields. The computer system may receive a request to access records based on a Boolean expression that affects a selection of records from the database table and that comprises clauses, at least two of which are joined by an AND operation. The computer system may access the requested records. The accessing may include, for a given one of the at least two clauses, performing an index scan on an index that corresponds to the given clause to identify records that satisfy that clause. The computer system may update a hash table based on the identified records and then identify the requested records based on the hash table. The Boolean expression may include clauses joined by an OR operation that are processed using multiple index scans.

The application provides a filtering condition rewriting method, device, equipment, medium and product, comprising: obtaining a filtering condition; when the filtering condition meets an optimization condition, splitting the filtering condition into a condition unit; when the condition unit is a Boolean expression containing a column name and a constant, determining a current partition table in which a target column corresponding to the column name is located and a current partition column of the current partition table, determining an optimization mark of the condition unit by comparing the current partition column with the target column; if the optimization mark of the condition unit is first mark information and a partition base table of the current partition table of the condition unit is a range partition table, obtaining the constant and a comparison operator in the condition unit, selecting a current lower-level partition table from lower-level partition tables of the partition base table, and determining optimization indication information of the condition unit according to the constant, the comparison operator and partition information of the current lower-level partition table; and rewriting based on the optimization indication information to obtain a rewritten filtering condition. The method improves the query efficiency of the filtering condition.

The invention discloses an interlocking Boolean logic graphical display method and system. The method comprises the steps that an interlocking Boolean logic source code file is read on a graphical user interface of a computer; analyzing the interlocking Boolean logic source code file, splitting each Boolean expression in the interlocking Boolean logic source code file to obtain the split Boolean expressions, and displaying each split Boolean expression on the graphical user interface; according to each split Boolean expression, generating an expression graph corresponding to the Boolean expression on the graphical user interface; each expression graph is stored in a vector diagram mode, the problem of software logic visualization pain points is solved, and the interlocking Boolean logic relation can be visually displayed; through the design of display elements, the understanding difficulty of signal personnel is reduced.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for neural network-assisted circuit design for integrated circuits. One of the methods include obtaining a description of an integrated circuit (IC); selecting one or more Boolean expressions specified in the description; and processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions.

The application belongs to the field of spectrum allocation, and particularly relates to a spectrum allocation method and system based on a hybrid quantum and classical algorithm. According to a constructed Boolean expression, an analysis tree is parsed, then according to a ratio of positive variables and negative variables in the analysis tree, a high-quality search space is selected from a search space, then in the high-quality search space, non-uniform superposition is first performed, then the target allocation scheme is flipped, the flipped scheme set is iterated through a constructed average inversion operator, the amplitude of the target scheme is increased, and an amplitude-increased scheme set is obtained; the amplitude-increased scheme set is measured, and an allocation result is obtained. Compared with a traditional spectrum allocation mode, the search space is reduced to a high-quality search space, the search range is reduced, redundant calculation and unnecessary resource consumption are avoided, secondly, a change from a traditional uniform superposition state to centralized search is realized, and the practical application ability of quantum search in a complex combination optimization problem is significantly improved.

A computer-implemented system and method for dynamic requirement determination using multiple independent hierarchy data structures. Entity records store identifiers of associated nodes in at least two hierarchies. Requirement rules define Boolean expressions, including AND, OR, and NOT operators, that reference node identifiers across multiple hierarchies. The system evaluates the Boolean expressions against an entity record's node identifiers to determine applicable requirements, generates a compliance status, and automatically re-evaluates at least a subset of the requirement rules to update applicability responsive to change events including changes in entity-node associations, hierarchy structure, or rule definitions. Requirement rules assigned to parent nodes are automatically inherited by descendant nodes, and the hierarchy data structures support recursive expansion without requiring modification to existing requirement rules. In some implementations, a control hierarchy stores condition-state values derived from external inputs such as equipment failures, environmental hazards, or regulatory changes, and triggers event-driven updates to requirement applicability in real time. A reporting engine may generate cross-dimensional compliance matrices by independently filtering entity records and requirement objects using node-based criteria across the hierarchies.

The application provides a correlation analysis expression index analysis method and device and electronic equipment. The method comprises the following steps: obtaining a correlation analysis expression to be analyzed; determining that the correlation analysis expression to be analyzed is a key Boolean expression and an indexable expression at the same time, and determining that the correlation analysis expression to be analyzed has an index, wherein the key Boolean expression is a Boolean expression capable of determining the value of the correlation analysis expression, each indexable expression comprises two identical single-table field expression, the flow table corresponding to each single-table field expression is mutually exclusive, and the fields in each single-table field expression belong to the same flow table. The performance of the correlation analysis can be improved based on the index analysis on the correlation analysis expression corresponding to the data flow, and the search efficiency of the data flow can be improved, thereby improving the efficiency of the network security analysis.

The invention discloses a logic gate netlist generation oriented large language model hardware description language conversion method, electronic equipment and a computer readable storage medium, and relates to the technical field of digital circuits and generative AI and large language models.The method comprises the steps that an LLM is trained to analyze and rewrite an input original HDL; converting the state machine description into a standardized state machine description with a uniform format; analyzing the description of the standardized state machine through logic Boolean, and generating a Boolean expression of the sum of products corresponding to each bit of a state register, an internal register and an output signal in the circuit as an intermediate expression; and generating the logic gate netlist based on an SOP Boolean expression and a predefined logic gate unit library. The problem that a traditional EDA tool is prone to falling into local optimum due to the fact that the traditional EDA tool depends on a curing heuristic algorithm is solved.

The application discloses a memory safety runtime detection acceleration method combined with static pointer analysis and a medium, and the method comprises the following steps: preprocessing and analyzing the source code of a program to be detected by using a compiler, collecting metadata of array variables, performing intra-procedure alias analysis and inter-procedure alias analysis, inserting a code segment for transferring metadata across procedures, rewriting array subscript expressions in the code, inserting a code segment for out-of-bound detection, inserting runtime detection code, compiling and linking the source code after the plugging by using the compiler and the linker, and generating an executable file; and running the executable file and outputting the result of the memory safety runtime detection. The application uses lightweight Boolean expression calculation instead of heavy runtime detection, can effectively reduce the time overhead of the runtime detection tool without changing the existing code, introducing false negatives and false positives, and guaranteeing the timing of error reporting and memory errors, and has practical application value.

Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware (“Debug FPGA”) that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.

The invention provides a fault diagnosis method and system for an integrated circuit, and relates to the technical field of circuit diagnosis, and the method comprises the steps: calculating ideal output values corresponding to all pre-generated test vectors based on a Boolean expression of a directed acyclic graph of a to-be-diagnosed circuit, and carrying out the fault detection through combining with a preset actual measurement output set; when a fault is detected, traversing all signal lines in the directed acyclic graph to generate a candidate fault set; performing priority ranking on the candidate fault set based on the Boolean difference sensitivity and the test coverage rate, and performing hierarchical simulation matching on the candidate fault set according to a ranking result; and performing multi-fault combination optimization verification on a fault matching result obtained after layered simulation matching through Boolean differential analysis, and outputting a fault diagnosis result after optimization verification, so that the efficiency and accuracy of fault diagnosis are improved, the misjudgment and missed judgment rates are reduced, and the product research and development cost and time are reduced.

The application discloses a shared bicycle station site selection method based on density and in-out degree balance clustering, introduces an in-out balance coefficient, and performs clustering on a shared bicycle station candidate area through a composite clustering algorithm of the density and the balance coefficient; a GPS data set of the bicycle is taken as a sample point data set, the sample point data set is clustered by improving and combining the characteristics of a Clique grid clustering algorithm, a plurality of shared station candidate addresses are acquired, each shared station candidate address is optimized, and the best shared station address is determined by combining POI matching of the area. A Boolean expression is used to define complex attribute conditions in a formalized manner, and then a clustering result of the shared bicycle station under the complex attribute conditions is given based on the density and a threshold value. The application has high efficiency and accuracy, can perform data mining on massive user travel OD data, analyze hot spot gathering areas of bicycle user orders, provide good early data preparation for the bicycle station, and has the characteristics of lightness and flexibility.

Methods, systems, and apparatus, including computer-readable media, for circuit design using a Boolean satisfiability solver. In some implementations, a system accesses circuit data describing circuit behavior or logic for a circuit to be designed. The system generates one or more Boolean expressions with variables that each represent a different design characteristic for the circuit. The system defines a Boolean satisfiability problem for the class of circuits having a predetermined circuit size, where the Boolean satisfiability problem has criteria that include (i) the generated one or more Boolean expressions and (ii) an assertion that the circuit is faulted. The system uses a Boolean satisfiability solver to process the Boolean satisfiability problem, and after determining that the Boolean satisfiability problem is unsatisfiable, the system uses the Boolean satisfiability solver to solve a series of updated versions of the Boolean satisfiability problem, and the system generates circuit design parameters for the circuit.

This application provides a data search method, apparatus, device, and medium. The method includes: selecting multiple target historical filtering conditions from a historical query dataset based on vector data of attribute data that satisfy various historical filtering conditions and the memory budget limit corresponding to the attribute vector dataset, with the goal of minimizing query cost; constructing sub-indexes corresponding to each target historical filtering condition based on the vector data of attribute data that satisfy each target historical filtering condition, and constructing a full index based on the multiple vector data; constructing an index dependency graph based on the sub-indexes and the full index; and, in response to a query request, selecting target vector data that semantically matches the query vector data and satisfies the query filtering conditions according to the query vector data and query filtering conditions carried in the query request, based on the index dependency graph. This allows for query filtering conditions based on arbitrary Boolean expressions, and features low index construction overhead, high efficiency, and controllable memory consumption.

A code analysis method includes: converting an expression indicated by a source code to Boolean expression, the expression including n conditions; generating binary expression tree including a plurality of nodes based on the Boolean expression; initializing a flip limit and the number of flips of each node by analyzing whether each node is a leaf node or a parent node; generating a first test case by initialization Boolean values of each of the plurality of parent nodes each of which a name is an operator among the plurality of nodes and two child nodes of the plurality of parent nodes to one of a plurality of valid cases; and generating n test cases by performing a flip on all node having flip feasibility on a path from a root node to a leaf node based on the first test case, and storing the first test and the n test cases.

This specification discloses a data query method and apparatus. The method includes: obtaining an SQL statement whose select part consists only of Boolean expressions, and determining a subquery statement targeting a single sensitive attribute based on several sensitive attributes located in a real data table. Then, each subquery statement is treated as a target statement and the following processing is performed: obtaining a target virtual table, whose corresponding target field value set is sampled from the target sensitive attribute fields in the real data table; determining multiple subsets of target field values ​​whose union is the target field value set based on the result matrix obtained by executing the target statement on the target virtual table; determining the target count of the target sensitive attribute field on each field value in each subset of target field values. Next, based on the multiple subsets of target field values ​​and the target count, determining a quantitative data leakage indicator value corresponding to the target statement to determine whether to provide the user with the query results of the SQL statement on the real data table.

The invention discloses an energy storage management script generation method and device, equipment and a storage medium. The method comprises the following steps: acquiring spoken language management information for spoken language of the energy storage system; semantic analysis processing is conducted on the spoken language management information, semantic structure information is extracted, and the semantic structure information at least comprises management condition information and management execution information; performing Boolean expression conversion on the management condition information to obtain condition expression information of a standard Boolean expression, and performing instruction conversion on the management execution information to obtain execution instruction information in a JSON-DSL (JavaScript Object Notation-Digital Subscriber Line) instruction form; and generating an energy storage management script based on a script generator according to the condition expression information and the execution instruction information, so that the programming height of an energy storage control strategy can be reduced, the operation and maintenance efficiency and the response speed are remarkably improved, and a key technical support is provided for safe, efficient and intelligent operation and maintenance of an energy storage system.

A computer-implemented method and system for symbolic logic-based evaluation are disclosed. Input data (e.g., responses, sensor feeds, or financial indicators) are normalized into symbolic parameters (pᵢ) through processor-executed routines. A clause engine evaluates Boolean expressions and records outcomes in a clause-truth registry. Weighted aggregation generates a composite descriptor (θ), with redundancy reduced through Karnaugh-map or equivalent logical simplification. Visualization modules—including θ gauges, flow diagrams, heatmaps, and logic networks—produce human- and machine-readable outputs that can interface with compliance APIs. Technical effects include reduced computational complexity, lower latency through incremental recomputation, and compliance-grade traceability. The invention is domain-agnostic, with applicability to education, healthcare (limited to monitoring and decision-support functions), finance, industrial IoT, cybersecurity, and enterprise analytics. Healthcare embodiments explicitly exclude diagnosis or treatment. All operations are processor-executed, producing compliance-linked outputs that extend beyond abstract algorithms, mental acts, or mere presentation of information.

The invention discloses a method and a device for generating off-line data of railway trackside train control equipment. The method comprises the steps of obtaining railway related files corresponding to a target railway line, wherein the railway related files comprise a Boolean expression file, a Boolean variable table, an engineering data file, an interface file and a configuration file; generating a Boolean interface file corresponding to the target railway line according to the Boolean variable table and the interface file; generating an application data file corresponding to the target railway line according to the engineering data file, the interface file and the configuration file; inputting the Boolean expression file and the Boolean interface file into a preset Boolean tool, and generating a Boolean application file corresponding to the target railway line; determining application data corresponding to each trackside train control device according to the application data file; determining a plurality of Boolean variable data corresponding to each trackside train control device according to the Boolean application file; and generating off-line data of the target railway line according to the application data corresponding to each trackside train control device and the plurality of Boolean variable data.

A non-transitory computer-readable medium that includes computer-executable instructions for carrying out a method (of expanding a set of standard cells which comprise a library) including: identifying ad hoc groups of elementary standard cells which are recurrent (in a population of one or more layout diagrams) and each of which, as a whole, having a first number of transistors and a second number of logic gates; and selecting one of the ad hoc groups to provide a selected logical function which is representable as a Boolean expression; generating one or more macro standard cells each of which, as a whole, having a third number of components (representing transistors or logic gates in a context of the first or second numbers) which is smaller than the first number or the second number; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells.