41 results about "Boolean expression" patented technology

The invention belongs to the field of spectrum allocation, and particularly relates to a spectrum allocation method and system based on mixed quantum and a classical algorithm, according to a constructed Boolean expression, an analytic tree is analyzed, then a high-quality search space is selected from a search space according to the ratio of a positive variable to a negative variable in the analytic tree, and in the high-quality search space, the high-quality search space is selected from a search space. Non-uniform superposition is firstly carried out, then a target distribution scheme is overturned, then iteration is continuously carried out on an overturning scheme set through a constructed average inversion operator, the amplitude of the target scheme is increased, and an amplitude increasing scheme set is obtained; and measuring the amplitude increasing scheme set to obtain a distribution result. Compared with a traditional spectrum allocation mode, the method has the advantages that the search space is reduced to a high-quality search space, the search range is reduced, redundant calculation and unnecessary resource consumption are avoided, the transformation from a traditional uniform superposition state to centralized search is realized, and the search efficiency is improved. And the practical application capability of quantum search in a complex combination optimization problem is remarkably improved.

Software vulnerabilities affecting devices can be determined using a vulnerability identifier uniquely identifying a vulnerability and version check information for use in determining software versions affected by the vulnerability. The version check information comprises one or more version rules providing a definition of how a software version number is tokenized and one or more Boolean expressions on those tokens to identify impacted versions of software according to the one or more version rules. In checking software for a vulnerability, the software version is determined and checked using the Boolean expression according to the version definition.

The invention discloses an Alliance tool chain logic synthesis method based on multiple logic domains. The method comprises the following steps that an intermediate representation structure of a target circuit is obtained; mapping a Boolean expression in the intermediate representation structure into an XMG network equivalent to the logic function of the target circuit; logic optimization with the optimization logic hierarchy as the target is executed on the XMG network obtained through mapping; converting the XMG network after logic hierarchy optimization into an AIG network; logic optimization with optimization of the number of nodes as a target is executed on the AIG network obtained through conversion, and the optimized AIG network is output as an aig file; and reading the aig file, analyzing the aig file, outputting the analyzed aig file as a VHDL file, inputting the VHDL file to the Alliance tool chain, and generating a gate-level netlist corresponding to the optimized target circuit. According to the method, the logic optimization efficiency and expandability can be greatly improved, the performance bottleneck of an existing Alliance tool chain is effectively solved, and the large-scale circuit design processing capacity of the Alliance tool chain is remarkably improved.

Systems and methods for uses and / or improvements to executing complex multi-step rule execution against big data. Prompts may be parsed to extract rule sets formed of Boolean expressions. These rules can be executed individually against datasets and the results of the rules can be cached. The cached results can be used upon generation of a compound rule, thereby enabling a simplified execution of custom rules. The techniques further resolve issues involving evaluations of various expression subgroupings and logical operators, while also improving performance by eliminating duplicate rule execution and circular dependencies.

The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.

Techniques are disclosed relating to implementing multiple index scans. A computer system may store a database table comprising fields and indexes corresponding to those fields. The computer system may receive a request to access records based on a Boolean expression that affects a selection of records from the database table and that comprises clauses, at least two of which are joined by an AND operation. The computer system may access the requested records. The accessing may include, for a given one of the at least two clauses, performing an index scan on an index that corresponds to the given clause to identify records that satisfy that clause. The computer system may update a hash table based on the identified records and then identify the requested records based on the hash table. The Boolean expression may include clauses joined by an OR operation that are processed using multiple index scans.

A non-transitory, computer-readable medium includes instructions, that, when executed, cause processing circuitry to receive, from an electronic device, a request regarding a custom segment defined by a first Boolean expression of a plurality of segments having elements corresponding to, or representative of, one or more electronic devices and / or one or more users of the one or more electronic devices. The instructions, when executed, also cause the processing circuitry to generate a different, second Boolean expression based on the first Boolean expression and the plurality of segments. Additionally, the instructions, when executed, cause the processing circuitry to determine a number of distinct elements of the custom segment at least partially utilizing the second Boolean expression and a plurality of data structures corresponding to the plurality of segments. Furthermore, the instructions, when executed, cause the processing circuitry to send an indication of the number of distinct elements to the electronic device.

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.

The invention discloses a static pointer analysis-combined detection acceleration method and medium during memory safe operation, and the method comprises the steps: carrying out the preprocessing and analysis of a source code of a to-be-detected program through a compiler, collecting the metadata of an array variable, carrying out the intra-process alias analysis and the inter-process alias analysis, and obtaining a to-be-detected program; inserting code snippets used for transmitting metadata in a cross-process manner, rewriting array subscript expressions in codes, inserting code snippets used for border crossing detection, inserting runtime detection codes, compiling and linking instrumented source codes by using a compiler and a linker, and generating an executable file; and running the executable file, and outputting a detection result during safe running of the memory. According to the method, lightweight Boolean expression calculation is used for replacing heavy-weight runtime detection, the time overhead of a runtime detection tool can be effectively reduced on the premise that existing codes are not changed, missing report and false report are not introduced, and the time sequence of report errors and memory errors is guaranteed, and the method has practical application value.

Techniques are disclosed relating to implementing multiple index scans. A computer system may store a database table comprising fields and indexes corresponding to those fields. The computer system may receive a request to access records based on a Boolean expression that affects a selection of records from the database table and that comprises clauses, at least two of which are joined by an AND operation. The computer system may access the requested records. The accessing may include, for a given one of the at least two clauses, performing an index scan on an index that corresponds to the given clause to identify records that satisfy that clause. The computer system may update a hash table based on the identified records and then identify the requested records based on the hash table. The Boolean expression may include clauses joined by an OR operation that are processed using multiple index scans.

The invention relates to the technical field of computers, and discloses a method for generating a minimum test case set of a genetic algorithm based on combinatorial optimization. Comprising the following steps: S1, extracting a logic dependency relationship in software, constructing a causal diagram, mapping a conditional branch and variable relationship into a Boolean expression, simplifying the causal diagram, merging invalid paths, reducing input, and converting the Boolean expression into a simplified ordered binary decision diagram; s2, according to the simplified ordered binary decision diagram obtained in the step 1, a combination number is obtained, and the combination number is the number of every two combinations of parameters in the simplified ordered binary decision diagram; and S3, optimizing and simplifying the ordered binary decision diagram by adopting an improved genetic algorithm to obtain an optimal minimum test case set. According to the method, the causal diagram is simplified, the binary decision diagram is simplified into a simplified ordered binary decision diagram, input path branches are reduced, the problem of path explosion is effectively solved, and the cost of test work is reduced.

The invention discloses a method and a system for converting an RSML-e model into a Luter synchronous data stream language. The method is used for converting the RSML-e model into a Luter related type, a Boolean expression, an and-or table, a variable, a macro and a function. Type conversion processes undefined values by creating enumeration and structures. The Boolean expression conversion comprises truth value judgment, logical negation, pre-state reference and equivalence judgment. And constructing sub-expressions according to columns in the and-or table conversion, and using logic or connection. The variables are converted into a Luster node, and the ordinary variables and the input variables are used for processing initial values and conditions respectively. The macro and function are converted into nodes with input and return values, and the contained logic is converted into a Boolean expression. In the whole process, the mapping from the RSML-e logic to the Luter data stream is realized, so that the security attribute of the system can be verified by using a model detection tool, and the security of the system is improved.

The application discloses a conversion method and system from RSML ‑e model to Luster synchronous data flow language. ‑e The method converts RSML ‑e model into Luster, which involves type conversion, Boolean expression conversion, and-or table conversion, variable conversion, macro conversion and function conversion. Type conversion handles undefined values by creating enumerations and structs. Boolean expression conversion includes truth judgment, logical negation, previous state reference and equality judgment. and-or table conversion constructs sub-expressions by columns and connects them with logical or. Variable conversion is converted into Luster nodes, and ordinary variables and input variables are processed with initial values and conditions respectively. Macro and function conversion are converted into nodes with input and return values, and the contained logic is converted into Boolean expressions. The overall process realizes the mapping of RSML ‑e logic to Luster data flow, so that the safety properties of the system can be verified using model checking tools, improving system security.

Embodiments are for auto generation of a debug trace in pre-silicon verification. A configuration file is created that includes fail information of a fail related to at least one failed interface of a design. A Boolean expression is generated to represent interface signals of the at least one failed interface, the configuration file comprising the interface signals of the least one failed interface. Responsive to determining that the Boolean expression meets a condition for complexity of the Boolean expression, code is automatically generated related to the fail based on the configuration file in preparation for a simulation of the failed interface in the design. A simulation of the design is run based at least in part on the code to generate a debug trace for the fail of the at least one failed interface.

The invention provides a filtering condition rewriting method and device, equipment, a medium and a product. The filtering condition rewriting method comprises the following steps: obtaining a filtering condition; when the filtering condition meets the optimization condition, the filtering condition is divided into condition units; when the condition unit is a Boolean expression containing a column name and a constant, determining a current partition table where a target column corresponding to the column name is located and a current partition column of the current partition table, and determining an optimization mark of the condition unit by comparing the current partition column with the target column; if the optimization mark of the condition unit is the first mark information and the partition base table of the current partition table of the condition unit is the range partition table, acquiring a constant and a comparison operator in the condition unit, selecting a current lower-level partition table from lower-level partition tables of the partition base table, and according to the constant, selecting the current lower-level partition table from the range partition table; comparing the operator with partition information of the current lower-level partition table, and determining optimization indication information of the condition unit; and rewriting based on the optimization indication information to obtain a rewritten filtering condition. According to the method, the query efficiency of the filtering condition is improved.

Techniques are disclosed relating to implementing multiple index scans. A computer system may store a database table comprising fields and indexes corresponding to those fields. The computer system may receive a request to access records based on a Boolean expression that affects a selection of records from the database table and that comprises clauses, at least two of which are joined by an AND operation. The computer system may access the requested records. The accessing may include, for a given one of the at least two clauses, performing an index scan on an index that corresponds to the given clause to identify records that satisfy that clause. The computer system may update a hash table based on the identified records and then identify the requested records based on the hash table. The Boolean expression may include clauses joined by an OR operation that are processed using multiple index scans.

The application provides a filtering condition rewriting method, device, equipment, medium and product, comprising: obtaining a filtering condition; when the filtering condition meets an optimization condition, splitting the filtering condition into a condition unit; when the condition unit is a Boolean expression containing a column name and a constant, determining a current partition table in which a target column corresponding to the column name is located and a current partition column of the current partition table, determining an optimization mark of the condition unit by comparing the current partition column with the target column; if the optimization mark of the condition unit is first mark information and a partition base table of the current partition table of the condition unit is a range partition table, obtaining the constant and a comparison operator in the condition unit, selecting a current lower-level partition table from lower-level partition tables of the partition base table, and determining optimization indication information of the condition unit according to the constant, the comparison operator and partition information of the current lower-level partition table; and rewriting based on the optimization indication information to obtain a rewritten filtering condition. The method improves the query efficiency of the filtering condition.

The present invention discloses a method for generating interlocking formal safety data based on the divide-and-conquer method, which classifies and stores the variables on the left side of the Boolean expression, and uses the divide-and-conquer method to search for and find in the variables on the right side of the Boolean expression, so as to generate input variables. This method can greatly reduce the time for variable search and query, and improve the search efficiency.

The invention discloses an interlocking Boolean logic graphical display method and system. The method comprises the steps that an interlocking Boolean logic source code file is read on a graphical user interface of a computer; analyzing the interlocking Boolean logic source code file, splitting each Boolean expression in the interlocking Boolean logic source code file to obtain the split Boolean expressions, and displaying each split Boolean expression on the graphical user interface; according to each split Boolean expression, generating an expression graph corresponding to the Boolean expression on the graphical user interface; each expression graph is stored in a vector diagram mode, the problem of software logic visualization pain points is solved, and the interlocking Boolean logic relation can be visually displayed; through the design of display elements, the understanding difficulty of signal personnel is reduced.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for neural network-assisted circuit design for integrated circuits. One of the methods include obtaining a description of an integrated circuit (IC); selecting one or more Boolean expressions specified in the description; and processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions.

The present invention discloses a logic synthesis method for an Alliance tool chain based on multiple logical domains, comprising the following steps: obtaining an intermediate representation structure of a target circuit; mapping a Boolean expression in the intermediate representation structure to an XMG network equivalent to the logical function of the target circuit; performing logic optimization aiming at optimizing the logic hierarchy on the mapped XMG network; converting the XMG network with optimized logic hierarchy into an AIG network; performing logic optimization aiming at optimizing the number of nodes on the converted AIG network, and outputting the optimized AIG network as an aig file; reading the aig file, parsing and outputting it as a VHDL file, and inputting the VHDL file to the Alliance tool chain to generate a gate-level netlist corresponding to the optimized target circuit. This method can greatly improve the efficiency and scalability of logic optimization, effectively solve the performance bottleneck of the existing Alliance tool chain, and significantly enhance the ability of the Alliance tool chain to process large-scale circuit designs.

The application belongs to the field of spectrum allocation, and particularly relates to a spectrum allocation method and system based on a hybrid quantum and classical algorithm. According to a constructed Boolean expression, an analysis tree is parsed, then according to a ratio of positive variables and negative variables in the analysis tree, a high-quality search space is selected from a search space, then in the high-quality search space, non-uniform superposition is first performed, then the target allocation scheme is flipped, the flipped scheme set is iterated through a constructed average inversion operator, the amplitude of the target scheme is increased, and an amplitude-increased scheme set is obtained; the amplitude-increased scheme set is measured, and an allocation result is obtained. Compared with a traditional spectrum allocation mode, the search space is reduced to a high-quality search space, the search range is reduced, redundant calculation and unnecessary resource consumption are avoided, secondly, a change from a traditional uniform superposition state to centralized search is realized, and the practical application ability of quantum search in a complex combination optimization problem is significantly improved.

A computer-implemented system and method for dynamic requirement determination using multiple independent hierarchy data structures. Entity records store identifiers of associated nodes in at least two hierarchies. Requirement rules define Boolean expressions, including AND, OR, and NOT operators, that reference node identifiers across multiple hierarchies. The system evaluates the Boolean expressions against an entity record's node identifiers to determine applicable requirements, generates a compliance status, and automatically re-evaluates at least a subset of the requirement rules to update applicability responsive to change events including changes in entity-node associations, hierarchy structure, or rule definitions. Requirement rules assigned to parent nodes are automatically inherited by descendant nodes, and the hierarchy data structures support recursive expansion without requiring modification to existing requirement rules. In some implementations, a control hierarchy stores condition-state values derived from external inputs such as equipment failures, environmental hazards, or regulatory changes, and triggers event-driven updates to requirement applicability in real time. A reporting engine may generate cross-dimensional compliance matrices by independently filtering entity records and requirement objects using node-based criteria across the hierarchies.

The application provides a correlation analysis expression index analysis method and device and electronic equipment. The method comprises the following steps: obtaining a correlation analysis expression to be analyzed; determining that the correlation analysis expression to be analyzed is a key Boolean expression and an indexable expression at the same time, and determining that the correlation analysis expression to be analyzed has an index, wherein the key Boolean expression is a Boolean expression capable of determining the value of the correlation analysis expression, each indexable expression comprises two identical single-table field expression, the flow table corresponding to each single-table field expression is mutually exclusive, and the fields in each single-table field expression belong to the same flow table. The performance of the correlation analysis can be improved based on the index analysis on the correlation analysis expression corresponding to the data flow, and the search efficiency of the data flow can be improved, thereby improving the efficiency of the network security analysis.

The invention discloses a logic gate netlist generation oriented large language model hardware description language conversion method, electronic equipment and a computer readable storage medium, and relates to the technical field of digital circuits and generative AI and large language models.The method comprises the steps that an LLM is trained to analyze and rewrite an input original HDL; converting the state machine description into a standardized state machine description with a uniform format; analyzing the description of the standardized state machine through logic Boolean, and generating a Boolean expression of the sum of products corresponding to each bit of a state register, an internal register and an output signal in the circuit as an intermediate expression; and generating the logic gate netlist based on an SOP Boolean expression and a predefined logic gate unit library. The problem that a traditional EDA tool is prone to falling into local optimum due to the fact that the traditional EDA tool depends on a curing heuristic algorithm is solved.

The application discloses a memory safety runtime detection acceleration method combined with static pointer analysis and a medium, and the method comprises the following steps: preprocessing and analyzing the source code of a program to be detected by using a compiler, collecting metadata of array variables, performing intra-procedure alias analysis and inter-procedure alias analysis, inserting a code segment for transferring metadata across procedures, rewriting array subscript expressions in the code, inserting a code segment for out-of-bound detection, inserting runtime detection code, compiling and linking the source code after the plugging by using the compiler and the linker, and generating an executable file; and running the executable file and outputting the result of the memory safety runtime detection. The application uses lightweight Boolean expression calculation instead of heavy runtime detection, can effectively reduce the time overhead of the runtime detection tool without changing the existing code, introducing false negatives and false positives, and guaranteeing the timing of error reporting and memory errors, and has practical application value.

Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware (“Debug FPGA”) that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.

The invention provides a fault diagnosis method and system for an integrated circuit, and relates to the technical field of circuit diagnosis, and the method comprises the steps: calculating ideal output values corresponding to all pre-generated test vectors based on a Boolean expression of a directed acyclic graph of a to-be-diagnosed circuit, and carrying out the fault detection through combining with a preset actual measurement output set; when a fault is detected, traversing all signal lines in the directed acyclic graph to generate a candidate fault set; performing priority ranking on the candidate fault set based on the Boolean difference sensitivity and the test coverage rate, and performing hierarchical simulation matching on the candidate fault set according to a ranking result; and performing multi-fault combination optimization verification on a fault matching result obtained after layered simulation matching through Boolean differential analysis, and outputting a fault diagnosis result after optimization verification, so that the efficiency and accuracy of fault diagnosis are improved, the misjudgment and missed judgment rates are reduced, and the product research and development cost and time are reduced.

The application discloses a shared bicycle station site selection method based on density and in-out degree balance clustering, introduces an in-out balance coefficient, and performs clustering on a shared bicycle station candidate area through a composite clustering algorithm of the density and the balance coefficient; a GPS data set of the bicycle is taken as a sample point data set, the sample point data set is clustered by improving and combining the characteristics of a Clique grid clustering algorithm, a plurality of shared station candidate addresses are acquired, each shared station candidate address is optimized, and the best shared station address is determined by combining POI matching of the area. A Boolean expression is used to define complex attribute conditions in a formalized manner, and then a clustering result of the shared bicycle station under the complex attribute conditions is given based on the density and a threshold value. The application has high efficiency and accuracy, can perform data mining on massive user travel OD data, analyze hot spot gathering areas of bicycle user orders, provide good early data preparation for the bicycle station, and has the characteristics of lightness and flexibility.

A non-transitory, computer-readable medium includes instructions, that, when executed, cause processing circuitry to receive, from an electronic device, a request regarding a custom segment defined by a first Boolean expression of a plurality of segments having elements corresponding to, or representative of, one or more electronic devices and / or one or more users of the one or more electronic devices. The instructions, when executed, also cause the processing circuitry to generate a different, second Boolean expression based on the first Boolean expression and the plurality of segments. Additionally, the instructions, when executed, cause the processing circuitry to determine a number of distinct elements of the custom segment at least partially utilizing the second Boolean expression and a plurality of data structures corresponding to the plurality of segments. Furthermore, the instructions, when executed, cause the processing circuitry to send an indication of the number of distinct elements to the electronic device.