Machine instruction for enhanced control of multiple virtual processor systems

a virtual processor and machine instruction technology, applied in the field of electronic systems, can solve the problems of reducing the overall processor efficiency, wasting otherwise usable cycles of the physical processor, and limiting the thread switching process in these experimental mvp systems, so as to facilitate the improvement of the processor efficiency and clean and efficient

Inactive Publication Date: 2005-05-19
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is about a method for improving the efficiency of MVP systems by using a special machine instruction called YIELD. This instruction allows a user to trigger a thread change, which means the thread surrenders control of the physical processor to an idle thread. This results in faster processing because the idle thread is executed instead of the stalled thread. The YIELD instruction is a clean and efficient way to remove a stalled thread from contention for the physical processor and allow an idle thread to take exclusive control.

Problems solved by technology

The technical problem addressed in this patent is how to efficiently remove a stalled virtual processor from contention for the physical processor in a multiple virtual processor system, and allow other idle virtual processors to take exclusive control of the physical processor until a condition on the removed virtual processor is satisfied.

Method used

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  • Machine instruction for enhanced control of multiple virtual processor systems
  • Machine instruction for enhanced control of multiple virtual processor systems
  • Machine instruction for enhanced control of multiple virtual processor systems

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Embodiment Construction

[0017] The concepts of multi-threading and multiple virtual processing are known in the processor art, and generally refer to processor architectures that utilize a single physical processor to serially execute two or more “virtual processors”. The term “virtual processor” refers to a discrete thread and physical processor operating state information associated with the thread. The term “thread” is well known in the processor art, and generally refers to a set of related machine (program) instructions (i.e., a computer or software program) that is executed by the physical processor. The operating state information associated with each virtual processor includes, for example, status flags and register states of the physical processor at a particular point in the thread execution. For example, an MVP system may include two virtual processors (i.e., two threads and two associated sets of operating state information). When a first virtual processor is executed, its associated operating ...

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Abstract

A multiple virtual processor (MVP) system using a special “YIELD” machine instruction inserted into a thread (virtual processor) at a selected point to trigger an immediate thread change (i.e., transfer of physical processor control to another thread). When the physical processor processes a YIELD instruction, the task thread surrenders control of the physical processor, and an otherwise idle thread is selected by a thread scheduling mechanism of the MVP system for loading into the physical processor. In one embodiment, the YIELD instruction includes an input operand that identifies the hardware signal on which the issuing thread intends to wait, and a result operand indicating the reason for reactivation.

Description

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Claims

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Application Information

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Owner INFINEON TECH AG
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