403 results about "Machine instruction" patented technology

A system for providing secondary data storage and recovery services for one or more networked host nodes includes a server application for facilitating data backup and recovery services; a first data storage medium accessible to the server application; a second data storage medium accessible to the server application; at least one client application for mapping write locations allocated by the first data storage medium to write locations represented in a logical view of the first data storage medium; and at least one machine instruction enabling direct read capability of the first data storage medium by the server application for purposes of subsequent time-based storage of the read data into the secondary data storage medium.

Watermarks and related machine-readable coding techniques are used to embed data within the information content on object surfaces. These techniques may be used as a substitute for (or in combination with) standard machine-readable coding methods such as bar codes, magnetic stripes, etc. As such, the coding techniques extend to many applications, such as linking objects with network resources, retail point of sale applications, object tracking and counting, production control, object sorting, etc. Object message data, including information about the object, machine instructions, or an index, may be hidden in the surface media of the object. An object messaging system includes an embedder and reader. The embedder converts an object message to an object reference, and encodes this reference in a watermarked signal applied to the object. The reader detects the presence of a watermark and decodes the watermark signal to extract the object reference.

Detecting executable machine instructions in a data is accomplished by accessing a plurality of values representing data contained within a memory of a computer system and performing pre-processing on the plurality of values to produce a candidate data subset. The pre-processing may include determining whether the plurality of values meets (a) a randomness condition, (b) a length condition, and/or (c) a string ratio condition. The candidate data subset is inspected for computer instructions, characteristics of the computer instructions are determined, and a predetermined action taken based on the characteristics of the computer instructions.

One embodiment of the present invention provides a system that provides precise exception semantics for a virtual machine. During operation, the system receives a program comprised of instructions that are specified in a machine instruction set architecture of the virtual machine, and translates these instructions into native instructions for the processor that the virtual machine is executing upon. While performing this translation, the system inserts one or more safepoints into the translated native instructions. The system then executes these native instructions on the processor. During execution, if the system detects that an exception was signaled by a native instruction, the system reverts the virtual machine to a previous safepoint to ensure that the virtual machine will precisely emulate the exception behavior of the virtual machine's instruction set architecture. The system uses a gated store buffer to ensure that any stores that occurred after the previous safepoint are discarded when reverting the virtual machine to the previous safepoint.

A multiple virtual processor (MVP) system using a special “YIELD” machine instruction inserted into a thread (virtual processor) at a selected point to trigger an immediate thread change (i.e., transfer of physical processor control to another thread). When the physical processor processes a YIELD instruction, the task thread surrenders control of the physical processor, and an otherwise idle thread is selected by a thread scheduling mechanism of the MVP system for loading into the physical processor. In one embodiment, the YIELD instruction includes an input operand that identifies the hardware signal on which the issuing thread intends to wait, and a result operand indicating the reason for reactivation.

A compiler apparatus that is capable of generating instruction sequences for causing a processor with parallel processing capability to operate with lower power consumption is a compiler apparatus that translates a source program into a machine language program for the processor including a plurality of execution units which can execute instructions in parallel and a plurality of instruction issue units which issue the instructions executed respectively by the plurality of execution units, and includes: a parser unit operable to parse the source program; an intermediate code conversion unit operable to convert the parsed source program into intermediate codes; an optimization unit operable to optimize the intermediate codes so as to reduce a hamming distance between instructions placed in positions corresponding to the same instruction issue unit in consecutive instruction cycles, without changing dependency between the instructions corresponding to the intermediate codes; and a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

A method for visual programming an automated transaction machine (12). The method includes the creation of terminal directors (225) that generally correspond to transactions performed by the automated transaction machine. The terminal directors are programmed by visually creating associations (238) between a plurality of ATM objects (230, 232) in a work space (224). Exemplary ATM objects include an authorization object (260), a back stage control object (262), a card reader object (264), a customer profile object (266), a depositor object (268), a dispenser object (270), keypad object (272), a logic object (274), a OCS object (276), a presenter object (278), a PIN entry object (280), a printer object (282), a sync object (284), and a transaction data object (286). A portion of the exemplary ATM objects are operative to interface with a device interface layer (728) for communicating with physical hardware devices (724, 726).

An IDE is provided by a web browser on a client machine, the IDE having a document editor that allows a user to generate source code. The source code is transmitted from the client machine to one or more servers via a network connection to be compiled into compiled native machine instructions. The compiled native machine instructions are received from the one or more servers by the client machine. The compiled native machine instructions are executed in a sandboxed environment on the client machine, such that system calls originating from the compiled native machine instructions that present a security risk are blocked using the sandboxed environment and system calls originating from the compiled native machine instructions that do not present a security risk are allowed in the sandboxed environment.

It is possible to identify pre- and post-conditions on a set of machine instructions by determining and analyzing possible value sets for variables and expressions. Stepping forward and backward through the set of instructions and tracking value sets at all points of reference allows for the value sets to be maximally restricted, which, in turn, gives an indication of allowed domains for different variables. These domains can be used to derive pre- and post-conditions for the set of instructions.

A virtual machine with a stack architecture includes: a stack 120 whose top level (TOS) and the second level from the top (SOS) are mapped to registers of a real machine 201; an instruction storing unit 102 for storing a virtual machine instruction sequence to be executed; next instruction information storing unit 101 for storing a plurality of sets of next instruction information that are each associated with a different virtual machine instruction in the virtual machine instruction sequence, the set of next instruction information for a given virtual machine instruction indicating a change in a number of sets of data stored in the stack 120 due to execution of a virtual machine instruction executed after the given virtual machine instruction; a decoding unit 103 for decoding a virtual machine instruction and an associated set of next instruction information after reading them from the instruction storing unit 102 and the next instruction information storing unit 101; and an executing unit 110 for executing the decoded virtual machine instruction and performing a stack handling in. the stack 120 in advance for a virtual machine instruction that is to be executed next based on the set of next instruction information.

A method finds an error in a computer program. A plurality of execution breakpoints are set in the computer program. A portion of the execution of the computer program is simulated as recorded in the trace data in the reverse order until one a plurality of conditions is met, wherein one of the plurality of conditions is an attempt to execute a machine instruction associated with one of the plurality of execution breakpoints.

The invention discloses a concurrent multiprocessor virtual machine system supporting CPU simultaneous execution, which comprises a virtual machine and an operating system running on the virtual machine. The virtual machine system can simulate not less than one virtual processor, which comprises a processor concurrent simulation module, a memory management module, an interrupt controlling simulation module and a peripheral simulation module; the machine instruction of the operating system is transferred to the processor simulation module through the memory management module of the virtual machine; the processor simulation module can simulate multiple virtual processors used for executing the operating system instruction translated by an instruction translation module and make the processors concurrently execute; the invention also provides a synchronous and access control algorithm in the concurrent execution process; and the peripheral simulation module and the processor simulation module are coordinated by the interrupt controlling simulation module. The invention has the advantages of suitability for simulating a concurrent execution environment of complete simulating hardware on an SMP server or a multi-core server.

A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.

An embodiment of the invention discloses a smart home control system and a control method, relates to the field of internet of things, and is to solve the problems that a user cannot control a plurality of different types of household appliances through a unified manner, and the operation process is complex. The concrete scheme is that the smart home control system comprises at least one household appliance and an intelligent controller connected with the household appliance through a short-distance communication module. The intelligent controller is used for obtaining control information comprising identification of the household appliance and a first control instruction, if capacity information indicates that the household appliance can execute a first working mode, and a first working parameter is within the range of working parameters corresponding to the first working mode and indicated by the capacity information, determining a first machine instruction corresponding to the first control instruction according to mapping relation, and sending the first machine instruction to the household appliance according to the identification of the household appliance; and the household appliance is used for receiving the first machine instruction sent by the intelligent controller, and executing the first machine instruction.

A client device detects one or more servers to which an application can be offloaded. The client device receives information from the servers regarding their graphics processing unit (GPU) compute resources. The client device selects one of the servers to offload the application based on such factors as the GPU compute resources, other performance metrics, power, and bandwidth/latency/quality of the communication channel between the server and the client device. The client device sends host code and a GPU computation kernel in intermediate language format to the server. The server compiles the host code and GPU kernel code into suitable machine instruction set architecture code for execution on CPU(s) and GPU(s) of the server. Once the application execution is complete, the server returns the results of the execution to the client device.

Machine instructions comprising a bootstrap code are buried within a critical component of an electronic game console where they cannot readily be accessed or modified. A preloader portion in a read only memory (ROM) is hashed by the bootstrap code and the result is compared to an expected hash value maintained in the bootstrap code. Further verification of the boot-up process is carried out by the preloader, which hashes the code in ROM to obtain a hash value for the code. The result is verified against a digital signature value that defines an expected value for this hash. Failure to obtain any expected result terminates the boot-up process. Since the bootstrap code confirms the preloader, and the preloader confirms the remainder of the code in ROM, this technique is useful for ensuring that the code used for booting up the device has not been modified or replaced.

An instruction generator comprising a storage device configured to store a machine instruction function incorporating both an operation definition defining a program description in a source program targeted for substitution to a SIMD instruction, and the SIMD instruction. A parallelism analyzer is configured to analyze the source program so as to detect operators applicable to parallel execution, and to generate parallelism information indicating the set of operators applicable to parallel execution. A SIMD instruction generator is configured to perform a matching determination between an instruction generating rule for the SIMD instruction and the parallelism information, and to read the machine instruction function out of the storage device in accordance with a result of the matching determination.

Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine instructions. Using machine instructions to round results according to the selected rounding mode has several advantages over software-implemented rounding techniques, such as faster execution and concise code. A variety of rounding modes can be specified. Depending in part on the specified rounding mode and on the sign of the value to be rounded, a rounding term is added to the value to be rounded. Adding this rounding term ensures that the desired result is obtained. The value thus obtained is then right-shifted.