21 results about "Instruction cycle" patented technology

The invention relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system oriented to a high-load scene. The method comprises the steps of collecting micro performance indexes such as the CPU instruction cycle number and the page table missing frequency, constructing a three-layer causal directed acyclic graph through Granger causal inspection, reducing a parameter search space based on bottleneck node reverse backtracking, generating an interpretable optimization decision with a causal path and contribution degree quantification, and carrying out optimization on the basis of the interpretable optimization decision. The problems that the performance bottleneck root cause cannot be accurately positioned and the optimization result lacks transparency in the prior art are solved. According to the method, bottleneck node reverse backtracking and parameter space pruning are performed based on the causal atlas, so that the problem of low optimization efficiency caused by incapability of accurately positioning a performance bottleneck root cause and blind exploration of a parameter space in the prior art is solved.

The application provides an RISC-V multi-core heterogeneous platform intelligent load balancing method and system, and relates to the technical field of resource allocation and scheduling. Micro-architecture performance data of each processing core in the RISC-V multi-core heterogeneous platform is acquired to construct a state vector; the micro-architecture performance data comprises instruction cycle number, cache miss rate at each level and memory pause proportion; the state vector is input into a pre-trained deep Q network model to generate optimal action instructions, so that the load balancing of thread resources and core capacity is realized; the optimal action instructions comprise thread migration, thread exchange and core frequency adjustment; the pre-training of the deep Q network model is performed on a parallel computing program running on the RISC-V platform; the environment is randomly disturbed before the program runs; the action is executed through a random strategy, and state, action and reward data are collected; an offline experience dataset is constructed to perform pre-training. Dynamic, cooperative and adaptive optimization of parallel computing of the RISC-V multi-core heterogeneous platform is realized.

This invention relates to the field of cloud service technology and provides an intelligent cloud service management method and system, comprising the following steps: collecting hardware performance counter data on each physical node, predicting the memory bandwidth contention intensity and last-level cache contention intensity of each application in the near future, and determining the interference fingerprint based on the number of instruction cycles per second; calculating the interference potential coefficient between each pair of applications, calculating the global co-location interference entropy of nodes, and classifying nodes into different levels based on the interference entropy; when a node is at a low or medium interference level, identifying aggressive applications, and dynamically adjusting the last-level cache quota, memory bandwidth limit, and CPU scheduling priority of aggressive applications; when a node is at a high interference level, determining candidate migration plans: selecting target nodes through a distributed node negotiation mechanism and executing application migration. This invention achieves the optimal balance between performance assurance and system overhead through a two-level strategy of local resource elastic adjustment and proactive migration.

The invention discloses a big data calculation analysis mining and operation storage system based on a smart machine room, relates to the technical field of big data analysis, and solves the technical problems of equipment state evaluation simplification, equipment grading and monitoring strategy extensibility and insufficient anomaly analysis depth. According to the method, invalid data is removed, the data format is unified, the storage and transmission cost is reduced, a high-quality data basis is provided for subsequent analysis, a dynamic reference is constructed based on historical normal data of equipment, the influence of task types on performance is distinguished in combination with comparison of a real-time instruction period and a historical period, and the limitation of single threshold judgment in the prior art is avoided; the accuracy of equipment state evaluation is improved, importance classification is performed on the equipment based on a multi-dimensional quantitative scoring system of business influence degree, fault cost and operation role, and a differentiated monitoring period is adopted, so that the problem of resource waste or insufficient core equipment monitoring caused by extensive monitoring strategies in the prior art is solved, and the accuracy of equipment state evaluation is improved. And the monitoring precision and the system overhead are balanced.

The invention relates to the technical field of resource management, in particular to a software resource dynamic management method and system. According to the method, a multi-dimensional physical performance evaluation system is established by fusing the frequency of the central processing unit, the bandwidth of the disk and the state of the network buffer, so that the integrating degree of a resource allocation decision and an actual load of underlying hardware is greatly improved; a fluctuation residual set is constructed by using response delay jitter, verification integrity and instruction period deviation, and an information entropy quantization algorithm is introduced, so that the disorder degree and the uncertainty risk of the operation behavior of the storage node are accurately captured; a dynamic security reference line is determined by referring to a cluster whole deviation degree mean value, so that an outlier sub-health server can be effectively identified, state identification overturning is executed, and a penalty factor and a deviation multiplying power reciprocal are combined to generate a weight adjustment factor to endow a storage cluster with a Byzantine fault self-repairing capability. And a software resource scheduling weight and decline polling assignment mechanism ensures that the high-reliability and high-performance node bears a core service request.

The application relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system for a high-load scene. The method comprises the following steps: collecting micro-performance indexes such as CPU instruction cycle numbers and page table missing times, constructing a three-layer causal directed acyclic graph through Granger causality test, reducing a parameter search space based on a bottleneck node reverse backtracking, and generating an interpretable optimization decision with a causal path and contribution quantification, so as to solve the problems that an existing technology cannot accurately locate a performance bottleneck root cause and an optimization result lacks transparency. The application performs bottleneck node reverse backtracking and parameter space pruning based on a causal graph, and solves the problems that the existing technology cannot accurately locate the performance bottleneck root cause and blind exploration of the parameter space leads to low optimization efficiency.

The invention relates to the technical field of decision support systems, in particular to a cloud intelligent decision support system and method supporting heterogeneous data sources, and the system comprises a heterogeneous logic alignment module, a pressure parameter derivation module, a self-adaptive simulation deduction module, a computing power value evaluation module and a decision confidence quantification module. According to the method, by means of numerical field combination calculation and topological structure comparison, an attribute constraint graph is constructed to judge logic isomorphism, the problem that heterogeneous source semantics are fuzzy is solved, gradient disturbance parameters are generated based on sliding window statistical superposition pressure coefficients, and extreme scenes are simulated in a definition domain boundary. A high-frequency log stream and a low-frequency aggregation table are dynamically switched according to index deviation, high-granularity data support is guaranteed during abnormal fluctuation, resource occupation is reduced in a stationary period, the storage efficiency ratio is calculated in combination with CPU instruction cycle consumption and access counting, high-calculation-cost data is prevented from being mistakenly deleted, the risk opening and efficiency ratio is evaluated, the reliability of a decision scheme is quantified, and the reliability of the decision scheme is improved. And an explanatory confidence basis is provided.

The invention discloses a heterogeneous multi-core system hybrid task allocation method and device, and the method comprises the steps: carrying out the instruction cycle according to the hierarchy of each task and the worst case of the task, and sorting the tasks, and obtaining the allocation priority of each task; selecting to-be-allocated tasks according to the allocation priority sequence, and allocating the selected task forcing part to a processor core which meets the task deadline and system energy consumption requirements of the tasks and has the highest task execution efficiency; according to the total energy consumption of the distributed task forcing parts and the total energy consumption budget of the system, sequentially carrying out energy consumption extension on the task forcing parts according to the task distribution priority; and selecting the tasks to be distributed according to the distribution priority sequence, and distributing the selectable parts of the selected tasks to the processor core which meets the task deadline of the tasks and has the highest task execution efficiency. According to the technical scheme, system resources are fully utilized to improve the service quality of the system, and collaborative optimization of hybrid task scheduling is achieved.

The application provides a clock synchronization method and device of a virtual machine, a storage medium and an electronic device, wherein the method comprises the following steps: determining a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip, wherein a clock period of a first clock source of the first virtual machine is a non-fixed instruction period, and a clock period of a second clock source of the second virtual machine is a fixed physical clock period; acquiring the first clock source of the first virtual machine; configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization on the first virtual machine and the second virtual machine by using the clock alignment duration. Through the embodiment, the technical problem of clock asynchronization between different virtual machines in the prior art is solved, the communication timing between different virtual machines is ensured to be consistent with the real hardware, and the inconsistency between the virtual and the real caused by the timing error is avoided.

The invention provides a clock synchronization method and device of virtual machines, a storage medium and an electronic device.The method comprises the steps that a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip are determined, the clock cycle of a first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock cycle of a second clock source of the second virtual machine is a non-fixed instruction cycle; the clock period of a second clock source of the second virtual machine is a fixed physical clock period; acquiring a first clock source of the first virtual machine; and configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization on the first virtual machine and the second virtual machine by adopting the clock alignment duration. Through the embodiment of the invention, the technical problem that clocks among different virtual machines in a heterogeneous chip in the prior art are asynchronous is solved, the communication time sequence among the different virtual machines is ensured to be consistent with real hardware, and virtual-real inconsistency caused by time sequence errors is avoided.

The application provides a lightweight deployment method and system of a large model on an edge computing device. In the application, the hardware instruction set architecture type and the number of parallel computing units of the target edge device are extracted to construct an acceleration capability portrait. Based on the instruction type, the large model weight is grouped and divided by a unified lookup table vectorization engine for precalculation, and a precalculation vector matching the target instruction set is generated. According to the number of parallel units and the instruction level parallelism capability, the precalculation vector is compiled to generate an adaptive parallel lookup table instruction block, the execution threads equal to the number of parallel units are allocated, and the data dependency conflict is eliminated. Finally, the instruction block is loaded into the shared memory area, the topology logic of the light guide switch matrix is configured based on the instruction type, and the data transmission path is dynamically switched within the hardware instruction cycle. The application realizes efficient deployment of the large model on the edge device and low-delay inference in the resource-constrained environment.

The present application relates to the technical field of flexible direct current transmission, and discloses a kind of control flow chart running time offline estimation method, the estimation method includes generating several embedded C codes to visual control flow chart, when generating, all function calls are unfolded in the form of inline function;Embedded C code is compiled into assembly code;Accumulate the code instruction cycle of each assembly instruction cycle to obtain code instruction cycle;Code instruction cycle is divided by the offline estimation result of the main frequency of processor calculated control flow chart running time.The present application can not depend on specific hardware platform and operating environment, can accurately estimate the running time of visual control flow chart offline, thereby intuitively positioning code running performance bottleneck, quickly predict code execution efficiency in development stage and guide subsequent optimization.

Latency-based instruction reservation clusters in a scheduler circuit in a processor are disclosed. The scheduler circuit includes a plurality of latency-based reservation circuits, each having an assigned producer instruction cycle latency. Producer instructions having the same cycle latency can be clustered in the same latency-based reservation circuit. Thus, the number of reservation entries is distributed among the plurality of latency-based reservation circuits to avoid or reduce the number of scheduler path connections and the increase in complexity in each reservation circuit to avoid or reduce the increase in scheduling latency. The number of scheduler path connections is reduced for a given number of reservation entries on a non-clustered selection circuit because the signals (e.g., wake-up signals, selection signals) used to schedule the instructions in each latency-based reservation circuit do not have to have the same clock cycle latency in order not to impact performance.

The invention discloses a communication conversion method for connecting a fieldbus master station and a servo press controller, and belongs to the field of electronic data processing.The method includes the steps that the servo press controller, an Ethernet controller (W5500), a master control processor (STM32F103CT6) and an industrial communication interface module (Anybus B40) are integrated, a hardware architecture with multi-protocol fusion is constructed, and Modbus TCP / PROFINET / TSN protocol conversion is supported; an intelligent dynamic scheduling algorithm is adopted, and comprises GraphSAGE + GATConv-based 32-dimensional topological feature coding, XGBoost weighted similarity calculation and a priority formula of PPO reinforcement learning optimization, so that rhogt is realized; switching the TFT prediction model at 10%; the communication reliability is guaranteed through TSN three-level flow scheduling and PRP double-link redundancy switching, and the confidence coefficient is predicted to be 1t; when 60%, a CRITICAL alarm frame is triggered, and a communication period is adaptively adjusted; in combination with digital twin fault injection and GAN data enhancement, an instruction period of 0.92 + / -0.07 ms, emergency response of 238 + / -15 microseconds and a prediction error rate of 6.8% are finally achieved, and the method is suitable for a high-precision industrial control scene.

Embodiments of the technology described herein include hardware of a processor configured to decrease the number of pipeline flushes caused by loop instructions by extracting data regarding the loop during the instruction fetch stage of the instruction cycle of the processor and / or updating the data as determined during the execution stage of the instruction cycle of the processor. In this regard, the control unit of the processor can direct the instruction fetch unit of the processor to fetch instructions of the loops based on the number of iterations of the loop as stored in a register associated with the instruction fetch stage of the processor. In this manner, certain computing devices employing embodiments of the technology described herein decrease the number of pipeline flushes, thereby increasing computational efficiency and hardware lifespan compared to using conventional technology.

This invention discloses a dynamic compensation method for pitch and perpendicularity errors in CNC machine tools, comprising the following steps: constructing and updating the comprehensive state vector of the machine tool in real time; extracting a set of time-varying geometric error parameters with clear physical meaning from the state vector in real time, the set of time-varying geometric error parameters including a transient pitch error table based on dynamic estimation of axis position, temperature and load force, and a dynamic perpendicularity angle change based on dynamic identification of structural temperature difference and off-center load moment; calculating the multi-axis synchronous correction command position required to offset the current error; generating a multi-axis linkage micro-compensation command vector that is strictly synchronized with the original command cycle by subtracting the correction command position from the original interpolation command; injecting the micro-compensation command vector into the command end of the CNC system position loop through command feedforward superposition, or acting on the system coordinate transformation layer by writing it into a high-speed dynamic coordinate offset.

The application provides a multi-Bank memory reorganization and parallel access method for BNN operation, and relates to the technical field of on-chip memory access control of neural network accelerator.The application determines a target bit set of a same inference instruction cycle based on a convolution window size, a channel serial number, a parallel operation bit width and an access step length, generates a Bank mapping value and stores the target bit distribution to a plurality of memory Banks; when there is a same Bank mapping value, writes the conflict target bit to a backup Bank position and establishes a backup Bank index; when reading, the target bit set is obtained in parallel, reorganized into a wide vector through a bit stream and transmitted to a BNN execution unit.The method can reduce the influence of Bank conflict of the same target bit set on the continuity of wide vector reorganization.

The application relates to an edge processing method and system for real-time sensing of power consumption of a water plant pump set. The method comprises: obtaining transient voltage and current waveforms of a water pump motor according to a synchronous acquisition trigger signal; extracting an active power mean value with a power frequency as a period, and constructing active power time sequence characteristic data; analyzing instruction period time sequence data, adaptively estimating the length of start-stop and speed regulation transition processes, and generating a steady-state operation identification sequence; removing non-steady-state periods and abnormal points based on the identification sequence to obtain a cleaned active power sequence; and finally performing cumulative operation on the cleaned power sequence in the time domain to directly obtain unit operation energy consumption data. The method can complete waveform compression, transition process removal and energy consumption accumulation on the edge side, does not need to upload massive high-frequency original data, reduces the load of a communication link, alleviates data transmission congestion in a multi-point monitoring scene, and guarantees the real-time performance and measurement accuracy of energy consumption sensing.

The application discloses a bit folding entropy encoding method and a processor based on single instruction processing. By adding special entropy encoding instructions and entropy decoding instructions in the instruction set architecture of the processor, the core operations such as state splitting, interval matching, shifting and combination of the BFE algorithm can be completed in a single instruction cycle. The single instruction atomicity eliminates the error cross-instruction propagation window in multi-instruction implementation, and pushes the inherent error self-cleaning capability of BFE to the extreme. The preferred implementation scheme can realize 0 BIT error of decoding output in combination with light verification. The instruction supports SIMD parallelism, and the execution unit is free of multiplication and branching. The application gives the instruction definition, assembly implementation and C language verification of Loongson and RISC-V, and can be widely applied in communication baseband chips, AI accelerators, solid state disk controllers and various system-level chips requiring efficient and highly reliable data compression.

The application belongs to the technical field of electrochemical energy storage and discloses a kind of energy storage unit battery cluster parallel equalization control system, comprising: data acquisition module, power optimization module, resistance adjustment module, control execution module and state monitoring module;Data acquisition module communicates with battery management system, for obtaining the power instruction of energy storage unit, the state of charge, health state, open-circuit voltage, equivalent internal resistance and operating limit value of each battery cluster;Power optimization module is connected with data acquisition module, for solving the power optimization model with the minimum SOC variance of battery cluster as the target based on the collected data.Construction is proposed in the application a kind of energy storage unit battery cluster parallel equalization control method based on program-controlled resistance.Series program-controlled resistance on battery cluster, adjust resistance value in each instruction cycle, realize the SOC equalization between battery cluster.

The invention provides an intelligent load balancing method and system for an RISC-V multi-core heterogeneous platform, and relates to the technical field of resource allocation scheduling. The method comprises the following steps: acquiring micro-architecture performance data of each processing core in an RISC-V multi-core heterogeneous platform, and constructing the micro-architecture performance data into a state vector; the micro-architecture performance data comprises an instruction cycle number, a cache miss rate of each level and a memory pause proportion; inputting the state vector into a pre-trained deep Q network model, generating an optimal action instruction, and realizing load balancing of thread resources and core capability; the optimal action instruction comprises thread migration, thread exchange and core frequency adjustment; the pre-training of the deep Q network model comprises the steps of running a parallel computing program on an RISC-V platform, randomly disturbing the environment before the program runs, executing actions through a random strategy, collecting state, action and reward data, and constructing an offline empirical data set for pre-training. And dynamic, collaborative and adaptive optimization of parallel computing of the RISC-V multi-core heterogeneous platform is realized.