55 results about "Instruction cycle" patented technology

The invention discloses an RISC-V vector optimization method, device and equipment based on thread scheduling, relates to the field of digital integrated circuit design, and is used for solving the problems of operation resource waste, relatively low operation efficiency and performance reduction caused by memory access performance limitation in the prior art. Comprising the following steps: acquiring an RISC-V vector instruction, extracting decoding information from the RISC-V vector instruction, and acquiring register configuration information in a vector state; determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and hardware configuration; executing a corresponding thread task according to the thread scheduling information; after execution is finished, if the thread task of the current instruction is executed, updating the state and delivering the current instruction; otherwise, updating the state and executing the next thread task until all the thread tasks are executed, writing back the data, completing instruction delivery and ending the instruction cycle. According to the method, the vector instruction execution performance under memory access performance limitation can be effectively improved, and the overall operation performance is improved.

The invention provides a lightweight deployment method and system of a large model on edge computing equipment. According to the method, the acceleration capability portrait is constructed by extracting the hardware instruction set architecture type of the target edge device and the number of parallel computing units. Based on the instruction type, the large model weight is grouped, divided and pre-calculated through a unified lookup table vectorization engine, and a pre-calculation vector matched with the target instruction set is generated; and according to the number of the parallel units and the instruction-level parallel capability, compiling the pre-calculation vector to generate an adaptive parallel table look-up instruction block, distributing execution threads with the same number as the parallel units, and eliminating data dependence conflicts. And finally, loading the instruction block to a shared memory area, configuring topological logic of the photoconductive switch matrix based on an instruction type, and dynamically switching a data transmission path in a hardware instruction period. According to the method, the efficient deployment of the large model in the edge equipment and the low-delay reasoning in the resource-constrained environment are realized.

The invention discloses an application deployment method, a cloud management platform, a computing device cluster and a storage medium, and relates to the technical field of cloud computing, the method comprises the following steps: the cloud management platform predicts to obtain the predicted maximum resource consumption of an application in a target time period, and predicts to obtain multiple groups of prediction information in one-to-one correspondence with multiple candidate nodes, a target deployment node of the application is then determined from a plurality of candidate nodes based on the predicted maximum resource usage, the plurality of sets of prediction information, and the resource allocation information. Wherein the target candidate node is any one of the plurality of candidate nodes, and the prediction information corresponding to the target candidate node comprises a predicted application running time length and / or a predicted average instruction cycle number when an application is deployed on the target candidate node in a target time period; the resource allocation information is used for indicating resource allocation conditions of a plurality of candidate nodes. According to the scheme, the resource utilization rate and the user experience can be considered.

The embodiment of the invention provides a distribution network monitoring and controlling edge computing chip system and method based on multi-core heterogeneity, and belongs to the technical field of edge computing chips. The distribution network monitoring and controlling edge computing chip system based on multi-core heterogeneity comprises a main system and a subsystem, the main system comprises a plurality of processors and a power algorithm acceleration module; the subsystems comprise an MCU (Microprogrammed Control Unit) real-time subsystem, an Ethernet subsystem and an embedded security subsystem; the embedded security subsystem comprises a hardware algorithm module and an embedded security module; the main system is used for operating software applications and algorithm programs in the power distribution network; the MCU real-time subsystem is used for processing on-line tasks of electricity saving and voltage monitoring; the Ethernet subsystem is used for communicating with an external chip; and the embedded security subsystem is used for integrating an encryption algorithm. According to the method, the problem that tensor calculation kernels and floating point operation involved in part of specific power algorithms consume a large number of instruction periods during operation can be solved, and the stability of a distribution network system is facilitated.

The invention discloses a regulation and control strategy, equipment, medium and system for a super-capacity coupling thermal power generating unit, belongs to the technical field of power grid dispatching, and aims to improve the response precision and efficiency of the unit to a frequency modulation instruction. According to the strategy, firstly, a received frequency modulation instruction is decomposed into a plurality of sub frequency modulation instructions with the same time length, so that the output adjustment process of a unit is managed more meticulously. Then, in each sub frequency modulation instruction period, a response error is calculated according to the current sub instruction, the actual output of the unit and the super-capacity output condition; based on the error, unit output of the next time period is adjusted and corrected in real time, so that it is ensured that unit output can closely follow the change of the frequency modulation instruction until the whole frequency modulation instruction is executed. The strategy effectively improves the flexibility and accuracy of the thermal power generating unit in the process of participating in the power grid frequency modulation by finely decomposing the frequency modulation instruction and dynamically adjusting the unit output.

The invention relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system oriented to a high-load scene. The method comprises the steps of collecting micro performance indexes such as the CPU instruction cycle number and the page table missing frequency, constructing a three-layer causal directed acyclic graph through Granger causal inspection, reducing a parameter search space based on bottleneck node reverse backtracking, generating an interpretable optimization decision with a causal path and contribution degree quantification, and carrying out optimization on the basis of the interpretable optimization decision. The problems that the performance bottleneck root cause cannot be accurately positioned and the optimization result lacks transparency in the prior art are solved. According to the method, bottleneck node reverse backtracking and parameter space pruning are performed based on the causal atlas, so that the problem of low optimization efficiency caused by incapability of accurately positioning a performance bottleneck root cause and blind exploration of a parameter space in the prior art is solved.

The invention provides a communication method of a self-anti-interference real-time bus. The communication method comprises the following steps that a main controller periodically sends a control instruction to a slave station through the real-time bus; the slave station executes corresponding operation after receiving the control instruction, and generates feedback data based on an execution result; wherein the control instruction and the feedback data exist in the form of a data packet; the slave station sends the feedback data back to the master controller through a real-time bus, the master controller adjusts the control instruction based on the feedback data, the control instruction is periodically sent to the slave station in a small data packet mode, data transmission with high transmission rate is achieved, meanwhile, the control instruction can be coded into a data packet, and the data packet is transmitted to the slave station through the data packet. The data packet of the control instruction is parallel in the bus, and the slave station can accurately identify the data packet, so that the bus has extremely strong anti-interference capability, and the use of the bus is ensured to enable the whole system to operate stably.

The invention discloses a surgical robot slave arm vibration suppression method and device, a medium and a product, and belongs to the technical field of medical equipment. The method comprises the steps that a position error combination generated by all position joints of a slave arm in a current reference period combination is determined, the position error combination comprises position errors corresponding to all reference periods, and the position errors are differences between instruction positions and actual positions of the position joints; updating the set filter combination according to the frequency spectrum data corresponding to the position error combination; using the updated set filter combination to sequentially filter the position instruction signals corresponding to the instruction periods in the current instruction period combination, and sequentially updating the position instruction signals corresponding to the instruction periods in the current instruction period combination; and for each position joint, controlling each position joint to move according to the sequentially updated position command signals. According to the technical scheme, vibration of the slave arm of the surgical robot can be restrained.

The invention relates to the technical field of artificial intelligence, in particular to an interaction instruction processing method and device, a vehicle and a storage medium. The interaction instruction processing method comprises the steps that when a cloud side instruction reasoning result and an end side instruction reasoning result are received within a preset instruction period, the cloud side instruction reasoning result and the end side instruction reasoning result are received; respectively identifying a first confidence value of the cloud side instruction reasoning result and a second confidence value of the end side instruction reasoning result, and when the first confidence value is greater than the second confidence value, controlling the vehicle to execute corresponding operation based on the cloud side instruction reasoning result corresponding to the first confidence value, otherwise, controlling the vehicle to execute corresponding operation. And controlling the vehicle to execute corresponding operation based on an end-side instruction reasoning result corresponding to the second confidence value. Therefore, the problems of high delay, serious network dependence and the like caused by pure dependence on cloud computing resources when a large model is adopted for text reasoning are solved, reasoning is carried out on text instruction information through cooperation of the cloud side and the end side, instruction reasoning results on the two sides are recognized through the end-cloud arbitration module, and an instruction with a high confidence value is executed.

The application provides an RISC-V multi-core heterogeneous platform intelligent load balancing method and system, and relates to the technical field of resource allocation and scheduling. Micro-architecture performance data of each processing core in the RISC-V multi-core heterogeneous platform is acquired to construct a state vector; the micro-architecture performance data comprises instruction cycle number, cache miss rate at each level and memory pause proportion; the state vector is input into a pre-trained deep Q network model to generate optimal action instructions, so that the load balancing of thread resources and core capacity is realized; the optimal action instructions comprise thread migration, thread exchange and core frequency adjustment; the pre-training of the deep Q network model is performed on a parallel computing program running on the RISC-V platform; the environment is randomly disturbed before the program runs; the action is executed through a random strategy, and state, action and reward data are collected; an offline experience dataset is constructed to perform pre-training. Dynamic, cooperative and adaptive optimization of parallel computing of the RISC-V multi-core heterogeneous platform is realized.

The present invention provides an instruction fetch control system for a dual-core lockstep processor supporting extended instructions, comprising an instruction fetch module, an instruction cache, a branch prediction module, a lockstep comparison module, and a dual-core lockstep processor. The present invention implements fine-grained control of the lockstep protection mode of different user codes through lockstep extended instructions. Lockstep extended instructions use a decoding path different from conventional instructions, directly entering the lockstep extended instruction decoding logic after instruction fetching, without relying on resource scheduling of the lockstep processor's subsequent stages or a specific instruction set. Branch prediction faults are treated as a type of branch prediction failure and processed in the instruction fetch module to ensure that branch prediction faults do not contaminate the dual-core lockstep processor's subsequent stages. For subsequent stage faults in the dual-core lockstep processor, the instruction fetch module can widen the pulse width of the subsequent stage fault signal to the difference value of the dual-core instruction cycles, and align the instruction streams in the check core and the execution core by inserting no-operations into the pipeline.

The present invention relates to the field of puncture control technology, and provides an automatic puncture control method and system, including providing a first spatial positioning device for monitoring respiratory and cardiac phases; collecting image data of the object to be punctured, and formulating a puncture path to guide subsequent punctures based on the image data; after obtaining a puncture execution instruction, executing a puncture instruction cycle at a fixed time interval until a puncture cancellation instruction is obtained or the current puncture depth is greater than or equal to the planned puncture depth, at which time the execution of the puncture instruction cycle is stopped; wherein the puncture instruction cycle is to read the position information of the first spatial positioning device in real time within a fixed time interval, and compare it with the position information of the first spatial positioning device on the image data; if the respiratory phase and cardiac phase are consistent with the image data, the puncture operation is performed within the current fixed time interval; otherwise, the puncture operation is not allowed to be performed. This solves the problem of difficulty in controlling the puncture timing due to factors such as the patient's respiration and heartbeat.

The invention relates to a position instruction smooth interpolation method for a servo driver. The problems that in the prior art, during interpolation planning of a servo driver, a planning curve of a controller cannot be effectively and reversely fitted, the curve control precision cannot be improved, the position dynamic tracking performance is reduced, and the application effect is poor are solved. The method comprises the following steps: S1, a controller issues a target position instruction at regular time according to an instruction period T, and a servo driver performs internal position interpolation control by taking T0 as a control period; s2, calculating the average speed in an instruction period; s3, acquiring a speed interpolation curve of the servo driver by using the average speed; and S4, obtaining a position increment value of each interpolation discrete point of the servo driver through the speed interpolation curve. The method has the advantages that the tracking precision of the command curve of the controller is improved, and the machining precision is better realized.

This invention relates to the field of cloud service technology and provides an intelligent cloud service management method and system, comprising the following steps: collecting hardware performance counter data on each physical node, predicting the memory bandwidth contention intensity and last-level cache contention intensity of each application in the near future, and determining the interference fingerprint based on the number of instruction cycles per second; calculating the interference potential coefficient between each pair of applications, calculating the global co-location interference entropy of nodes, and classifying nodes into different levels based on the interference entropy; when a node is at a low or medium interference level, identifying aggressive applications, and dynamically adjusting the last-level cache quota, memory bandwidth limit, and CPU scheduling priority of aggressive applications; when a node is at a high interference level, determining candidate migration plans: selecting target nodes through a distributed node negotiation mechanism and executing application migration. This invention achieves the optimal balance between performance assurance and system overhead through a two-level strategy of local resource elastic adjustment and proactive migration.

The invention discloses a big data calculation analysis mining and operation storage system based on a smart machine room, relates to the technical field of big data analysis, and solves the technical problems of equipment state evaluation simplification, equipment grading and monitoring strategy extensibility and insufficient anomaly analysis depth. According to the method, invalid data is removed, the data format is unified, the storage and transmission cost is reduced, a high-quality data basis is provided for subsequent analysis, a dynamic reference is constructed based on historical normal data of equipment, the influence of task types on performance is distinguished in combination with comparison of a real-time instruction period and a historical period, and the limitation of single threshold judgment in the prior art is avoided; the accuracy of equipment state evaluation is improved, importance classification is performed on the equipment based on a multi-dimensional quantitative scoring system of business influence degree, fault cost and operation role, and a differentiated monitoring period is adopted, so that the problem of resource waste or insufficient core equipment monitoring caused by extensive monitoring strategies in the prior art is solved, and the accuracy of equipment state evaluation is improved. And the monitoring precision and the system overhead are balanced.

This invention relates to an automatic servo testing system and method based on a programmable power supply. The testing system includes a host computer module providing a testing software interface; an automatic power supply start-up and test information setting module for reading and storing power supply and test setting information; an automatic power supply on / off control module for automatically controlling the power supply and control power supply; an automatic command sending and feedback acquisition and processing module for acquiring test command types and command cycles, sending test commands, and judging and extracting received feedback data; an automatic fault judgment and processing module for periodically querying the status of the control power supply and power supply, querying and judging feedback data in real time, and receiving and judging position feedback in real time; and an automatic process monitoring and processing module for automatic real-time monitoring. This invention solves the problems of high manpower requirements, low automation, slow fault handling, and low safety and reliability in existing servo product testing.

The embodiment of the invention provides a depth data processing method and a related device. The depth data processing method is applied to a robot terminal. The depth data processing method comprises the following steps: intercepting first depth data with a first length to obtain second depth data with a second length; wherein the second length is smaller than the first length; mapping the plurality of pieces of second depth data into point cloud data in a single mapping instruction period; wherein the total length of the multiple pieces of second depth data is smaller than or equal to the digit of a register; and generating a robot control task for driving the robot terminal to execute a specific operation based on the point cloud data. According to the depth data processing method and the related device, the depth data can be efficiently processed under the condition that the computing power of a robot terminal is limited so as to quickly generate a corresponding robot control task.

The invention relates to the technical field of resource management, in particular to a software resource dynamic management method and system. According to the method, a multi-dimensional physical performance evaluation system is established by fusing the frequency of the central processing unit, the bandwidth of the disk and the state of the network buffer, so that the integrating degree of a resource allocation decision and an actual load of underlying hardware is greatly improved; a fluctuation residual set is constructed by using response delay jitter, verification integrity and instruction period deviation, and an information entropy quantization algorithm is introduced, so that the disorder degree and the uncertainty risk of the operation behavior of the storage node are accurately captured; a dynamic security reference line is determined by referring to a cluster whole deviation degree mean value, so that an outlier sub-health server can be effectively identified, state identification overturning is executed, and a penalty factor and a deviation multiplying power reciprocal are combined to generate a weight adjustment factor to endow a storage cluster with a Byzantine fault self-repairing capability. And a software resource scheduling weight and decline polling assignment mechanism ensures that the high-reliability and high-performance node bears a core service request.

The invention belongs to the technical field of power systems, and discloses a control load distributed control method and system based on user random behaviors. The method comprises the following steps: dividing a building into a plurality of temperature control areas, and generating a first control reference sequence based on user information and environment information of the temperature control areas, whether a control reference sequence with the similarity with the first control reference sequence larger than a first preset value exists in the historical operation data table or not is judged, if yes, the control reference sequence corresponding to the maximum similarity value is defined as a second control reference sequence, a first temperature control instruction is generated based on an air conditioner operation mode corresponding to the second control reference sequence, and if not, a second temperature control instruction is generated. And generating a second temperature control instruction based on the user information and the temperature control mode corresponding to the temperature control area, periodically judging whether feedback information of the user is received or not, and if yes, generating a third temperature control instruction of the temperature control area based on the feedback information. According to the technical scheme, intelligent and personalized control over the building temperature control load can be achieved, and the user satisfaction degree is improved while the building energy efficiency is improved.

A method for executing instructions in a processor core implemented with a source operand collection cache coupled to at least one input of a data path located within the processor core, comprising the method: Decoding an instruction to determine a plurality of operands specified by the instruction, For each operand in the plurality of operands: Determine that the operand is not stored in the source operand collection cache, and load the operand from a local register into the source operand collection cache. Configuring the processor core to execute instructions on the operand stored in the source operand collection cache. Updating a cache table after the operand has been loaded into the source operand collection cache to associate a register index corresponding to the operand with a memory location in the source operand collection cache, determining which register indices to use as operands for the next instruction, to determine whether the register value corresponding to that register index is currently stored in the same memory location as a result of scheduling a previous instruction, and if the same memory location stores that register value, another register value from the same register bank is loaded into a different memory location during the same instruction cycle.

The application provides a communication method of a self anti-interference real-time bus, comprising the following steps: a master controller periodically sends control instructions to a slave station through a real-time bus; the slave station executes corresponding operations after receiving the control instructions, and generates feedback data based on the execution result; wherein the control instructions and the feedback data exist in the form of data packets; the slave station returns the feedback data to the master controller through the real-time bus, and the master controller adjusts the control instructions based on the feedback data; the application periodically sends the control instructions to the slave station in the form of small data packets, realizes high transmission rate for data transmission, encodes the control instructions into data packets, and the data packets of the control instructions are parallel on the bus, so that the slave station can accurately identify the data packets, the bus has strong anti-interference ability, and the use of the bus ensures the stable operation of the whole system.

The application relates to the technical field of data processing, and discloses a computing power server system layer optimization method and system for a high-load scene. The method comprises the following steps: collecting micro-performance indexes such as CPU instruction cycle numbers and page table missing times, constructing a three-layer causal directed acyclic graph through Granger causality test, reducing a parameter search space based on a bottleneck node reverse backtracking, and generating an interpretable optimization decision with a causal path and contribution quantification, so as to solve the problems that an existing technology cannot accurately locate a performance bottleneck root cause and an optimization result lacks transparency. The application performs bottleneck node reverse backtracking and parameter space pruning based on a causal graph, and solves the problems that the existing technology cannot accurately locate the performance bottleneck root cause and blind exploration of the parameter space leads to low optimization efficiency.

The invention relates to the technical field of decision support systems, in particular to a cloud intelligent decision support system and method supporting heterogeneous data sources, and the system comprises a heterogeneous logic alignment module, a pressure parameter derivation module, a self-adaptive simulation deduction module, a computing power value evaluation module and a decision confidence quantification module. According to the method, by means of numerical field combination calculation and topological structure comparison, an attribute constraint graph is constructed to judge logic isomorphism, the problem that heterogeneous source semantics are fuzzy is solved, gradient disturbance parameters are generated based on sliding window statistical superposition pressure coefficients, and extreme scenes are simulated in a definition domain boundary. A high-frequency log stream and a low-frequency aggregation table are dynamically switched according to index deviation, high-granularity data support is guaranteed during abnormal fluctuation, resource occupation is reduced in a stationary period, the storage efficiency ratio is calculated in combination with CPU instruction cycle consumption and access counting, high-calculation-cost data is prevented from being mistakenly deleted, the risk opening and efficiency ratio is evaluated, the reliability of a decision scheme is quantified, and the reliability of the decision scheme is improved. And an explanatory confidence basis is provided.

The invention discloses a heterogeneous multi-core system hybrid task allocation method and device, and the method comprises the steps: carrying out the instruction cycle according to the hierarchy of each task and the worst case of the task, and sorting the tasks, and obtaining the allocation priority of each task; selecting to-be-allocated tasks according to the allocation priority sequence, and allocating the selected task forcing part to a processor core which meets the task deadline and system energy consumption requirements of the tasks and has the highest task execution efficiency; according to the total energy consumption of the distributed task forcing parts and the total energy consumption budget of the system, sequentially carrying out energy consumption extension on the task forcing parts according to the task distribution priority; and selecting the tasks to be distributed according to the distribution priority sequence, and distributing the selectable parts of the selected tasks to the processor core which meets the task deadline of the tasks and has the highest task execution efficiency. According to the technical scheme, system resources are fully utilized to improve the service quality of the system, and collaborative optimization of hybrid task scheduling is achieved.

The application provides a clock synchronization method and device of a virtual machine, a storage medium and an electronic device, wherein the method comprises the following steps: determining a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip, wherein a clock period of a first clock source of the first virtual machine is a non-fixed instruction period, and a clock period of a second clock source of the second virtual machine is a fixed physical clock period; acquiring the first clock source of the first virtual machine; configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization on the first virtual machine and the second virtual machine by using the clock alignment duration. Through the embodiment, the technical problem of clock asynchronization between different virtual machines in the prior art is solved, the communication timing between different virtual machines is ensured to be consistent with the real hardware, and the inconsistency between the virtual and the real caused by the timing error is avoided.

The present application discloses a synchronization method, device and medium for an arbitrary waveform generator, the method comprising: the arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, the cycle ratio being the ratio of an external trigger signal cycle to an FPGA clock cycle; the cycle ratio is set according to the cycle ratio setting instruction, and an external trigger signal sent from a system trigger signal module is obtained; a rising edge of a signal sampled to the external trigger signal is determined, and the FPGA clock cycle is counted with the rising edge of the signal as a starting time node; when the count value of the FPGA clock cycle is determined to reach the cycle ratio, an internal trigger signal is generated inside the FPGA of the arbitrary waveform generator, and the FPGA clock cycle is recounted; and loaded waveform data sent from the measurement and control terminal is received, and a waveform is sent under the triggering of the internal trigger signal.

The invention provides a clock synchronization method and device of virtual machines, a storage medium and an electronic device.The method comprises the steps that a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip are determined, the clock cycle of a first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock cycle of a second clock source of the second virtual machine is a non-fixed instruction cycle; the clock period of a second clock source of the second virtual machine is a fixed physical clock period; acquiring a first clock source of the first virtual machine; and configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization on the first virtual machine and the second virtual machine by adopting the clock alignment duration. Through the embodiment of the invention, the technical problem that clocks among different virtual machines in a heterogeneous chip in the prior art are asynchronous is solved, the communication time sequence among the different virtual machines is ensured to be consistent with real hardware, and virtual-real inconsistency caused by time sequence errors is avoided.

The application provides a lightweight deployment method and system of a large model on an edge computing device. In the application, the hardware instruction set architecture type and the number of parallel computing units of the target edge device are extracted to construct an acceleration capability portrait. Based on the instruction type, the large model weight is grouped and divided by a unified lookup table vectorization engine for precalculation, and a precalculation vector matching the target instruction set is generated. According to the number of parallel units and the instruction level parallelism capability, the precalculation vector is compiled to generate an adaptive parallel lookup table instruction block, the execution threads equal to the number of parallel units are allocated, and the data dependency conflict is eliminated. Finally, the instruction block is loaded into the shared memory area, the topology logic of the light guide switch matrix is configured based on the instruction type, and the data transmission path is dynamically switched within the hardware instruction cycle. The application realizes efficient deployment of the large model on the edge device and low-delay inference in the resource-constrained environment.

The invention relates to the field of integrated circuit automatic test equipment, in particular to a semiconductor test method. The method comprises the following steps: in a compiling process, judging whether the number of instruction cycles in a test vector is fixed or not; and if the instructions with the unfixed period number exist in the test vector, recording the instructions with the unfixed period number according to the fixed number of times. According to the method, the instructions with the unfixed period number are recorded according to the fixed number of times, so that analysis of any fragment offset in the test vector can be simplified, the reduction speed is greatly improved, and the time consumption of AFM data analysis and reduction is reduced.

The invention relates to a high-computing-power application-oriented pipeline processor architecture, which is characterized in that all CPUs (Central Processing Unit) are arranged in sequence, and a computing result of each CPU is directly sent to a next pipeline-level CPU for computing; wherein the first pipeline-level processor is used for data read memory access, and the last pipeline-level processor is used for data write-back memory access. All the CPUs start to operate one later pipeline stage period in sequence according to the pipeline stage sequence, so that it is guaranteed that when the previous pipeline stage CPU finishes calculation and sends data to the next pipeline stage processor, the next pipeline stage processor exactly prepares to start to process data from the previous pipeline stage processor. According to the invention, the arithmetic logic units of the adjacent pipeline-level processors are connected with the registers, so that an additional memory access process is not needed when data is calculated and transmitted among the processors, and an instruction locking function is added, so that the influence of repeated instructions on an instruction cycle is reduced, the arithmetic units of the processors are utilized to the maximum extent, and the data processing efficiency is improved. And the calculation efficiency during large-scale data operation is greatly improved.