164 results about "Instruction cycle" patented technology

A wireless sensor network is installed inside pipelines using sensors and wireless transceivers that are small, low-cost, and rugged. The objective is monitoring the pipeline and recommending maintenance and repair at specific locations in the pipeline. Maintenance includes detection of internal corrosion using sensors that can result in leaks. Furthermore detection of leaks for prevention of catastrophic failures as a result of damage, such as third party mechanical damage. After establishing the wireless sensor network, the network is activated so the sensors can make measurements periodically or continuously using instructions transmitted via a base station. The sensor data from the various sensors are transmitted inside the pipe and extracted to access points in the pipeline to a remote computer that stores the data within the computer. The sensed information can be used for monitoring as well as analysis using a recommendation engine to provide maintenance and repair alerts.

A method for performing a high-performance closed-form single-scan calculation of oblong-shape rotation angles from binary images of arbitrary size on a processor using running sums is disclosed. Running sums are calculated and stored throughout each scan, and the results are obtained in closed form by simple post-scan computation. An algorithmic embodiment may execute on one or more hardware processors with limited or constrained computation power, available instruction cycles, available memory, etc. Exemplary hardware processors are found in one or more CPUs of a desktop, laptop, tablet, or handheld computing device, and may be an embedded processor or a signal processor chip. The resulting method may be used for touch or optical user interfaces, real-time image recognition, real-time machine vision, and other purposes.

Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing dynamic and concurrent adjustment of compression to maximize the benefits of compression in a variety of applications.

An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

A device, system, and method are directed towards managing power consumption in a computer system with one or more processing units, each processing unit executing one or more threads. Threads are characterized based on a cycles per instruction (CPI) characteristic of the thread. A clock frequency of each processing unit may be configured based on the CPI of each thread assigned to the processing unit. In a system wherein higher clock frequencies consume greater amounts of power, the CPI may be used to determine a desirable clock frequency. The CPI of each thread may also be used to assign threads to each processing unit, so that threads having similar characteristics are grouped together. Techniques for assigning threads and configuring processor frequency may be combined to affect performance and power consumption. Various specifications or factors may also be considered when scheduling threads or determining processor frequencies.

A test apparatus includes: an instruction execution unit for sequentially executing instructions in a test program for a DUT in each instruction cycle; a default pattern memory for storing default pattern sequence to be associated with default pattern identification information for identifying that default pattern sequence, the default pattern sequence being a preset one of a plurality of test pattern sequence sets, each formed by a plurality of test patterns to be sequentially output to a terminal of the DUT during an instruction cycle period; a test pattern memory for storing, for each instruction, test pattern sequence output in an instruction cycle period for executing that instruction or the default pattern identification information that is output in the instruction cycle period; a test pattern memory read unit for, in a case of executing one instruction, reading the test pattern sequence or the default pattern identification information that is stored and is associated with that instruction in the test pattern memory; a default pattern read unit for, when the test pattern memory read unit read the default pattern identification information, reading the default pattern sequence that is stored and is associated with the default pattern identification information in the default pattern memory; and a test pattern output unit for outputting the test pattern sequence read by the test pattern memory to correspond to the one instruction, or the default pattern sequence read by the default pattern read unit to a terminal of the DUT during an instruction cycle period for executing that instruction.

A method and apparatus for controlling power consumption in a processor. In one embodiment, a processor includes a pipeline. The pipeline includes logic for fetching instructions, issuing instructions, and executing instructions. The processor also includes a power management unit. The power management unit is configured to input M stalls into the pipeline every N instruction cycles (where M and N are integer value and wherein M is less than N).

A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

A method, system and computer program product enables the granular collection and utilization of hardware statistical samples for the efficient scheduling and allocation of data processing resources. In particular, a Partition Statistics Capture and Analysis (PSCA) utility utilizes special purpose registers to collect statistical samples, such as: (1) instructions completed; (2) Level2 (L2) cache misses; (3) cycles per instruction (CPI); and / or (4) other statistics selected based on the programming of the PSCA utility. Further, these statistical samples are utilized for the several purposes, including: (1) determining how long (time) the footprint of a partition takes to become established during the “cold start” period, i.e., during system instantiation; (2) detecting movement of the CPI curve in order to determine the (shifted) location of the onset of steady state (i.e., the knee) on the CPI curve; and (3) utilizing the statistical samples to guide dispatch decisions and make tuning recommendations.

The present invention discloses a method for adaptive field-weakening control of a permanent magnet synchronous motor. The objective of the invention is to mainly solve the problems that a current field-weakening method depends too much on motor parameters and computation load of an algorithm is large in the prior art. The method provided by the invention, according to specific application conditions of a permanent magnet synchronous motor, calculates a real-time modulation ratio mr, a switching point modulation ratio mf, an exit field-weakening point modulation ratio mq and a modulation hysteresis width [Delta]m0, and determines a basic excitation current value [Delta]id0, a direction coefficient P1 and a field current difference coefficient P2, and a current instruction cycle instructionexcitation current is calculated through a formula. Through the above scheme, an influence of working conditions on field-weakening points is avoided, and field-weakening switching points are automatically switched according to a real-time modulation ratio so as to realize stable field-weakening switching of a permanent magnet synchronous motor with different conditions such as different rotatingspeeds and voltages and have a high practical value and a promotion value.

A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

The invention discloses an apparatus and method for implementing digital predistortion, wherein the method includes utilizing programmable logic structure to realize the following steps: S1. a parameter control module utilizes power amplifier incoming signals and power amplifier feedback signals of a power amplifier to synchronously calculate and renovate all power amplifier model parameters in the memorization multinomial model; S2. a model copy module assigns the value of the power amplifier model parameter to the corresponding model parameters a digital predistortion module; S3. the digital predistortion module carries out a predistortion process to the incoming signals according to model parameters. The inventive apparatus and method utilizes parallel arithmetic advantage of the programmable logic structure, thereby realizing the calculation of all model parameters in an instruction cycle, reducing computing time, improving predistortion process efficiency, and quickly and accurately realizing the digital predistortion process.