A four-stage assembly line RISC-V processor with a rapid data bypass structure

A RISC-V and pipeline technology, applied in the direction of machine execution devices, etc., can solve the problems of lack of versatility, lack of tool chain support, etc., and achieve the effect of simple structure, high hardware resources, and reduced information transmission

Pending Publication Date: 2019-06-21
SUN YAT SEN UNIV
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  • Application Information

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Problems solved by technology

The invention patent with the authorized announcement number CN 101256546A discloses a 32-bit microprocessor, but the inst

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  • A four-stage assembly line RISC-V processor with a rapid data bypass structure
  • A four-stage assembly line RISC-V processor with a rapid data bypass structure
  • A four-stage assembly line RISC-V processor with a rapid data bypass structure

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Embodiment 1

[0044] This embodiment provides a four-stage pipeline RISC-V processor with a fast data bypass structure proposed by the present invention, which includes a four-stage pipeline structure with a total length of four stages that can be dynamically adjusted according to the instruction type, a memory access unit, an exception / interrupt Processing unit, instruction memory, and data memory. Both the data bus and the address bus between the memory and the CPU are 32 bits wide.

[0045] The first stage of the pipeline is the instruction fetch module. The function of the instruction fetch module is to continuously fetch the instruction to be executed by the CPU from the instruction memory according to the running condition of the program. The instruction fetch module includes the following parts:

[0046] 1. PC register

[0047] The PC register stores the PC corresponding to the instruction passed from the instruction memory of the current cycle to the instruction fetch module.

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Abstract

The invention provides a four-stage assembly line RISC-V processor with a rapid data bypass structure. The processor has a four-stage pipeline structure, when the operation except the non-Load instruction is executed, the direct bypass is carried out, and the effective data pipeline is changed into three stages, so that the operation speed is increased. Compared with a traditional four-level assembly line, the structure reduces the instruction period of most instructions and the frequency of occurrence of data danger, and greatly improves the performance of the processor. And the four-stage pipeline structure comprises an instruction fetching module, a decoding module, an execution module and a write-back module. The fetch module can generate a PC of a next instruction according to the instruction fetched from the instruction memory in the current period and an external control signal; The decoding module is used for extracting an operation code, a function code, a source register, a destination register and an immediate of the instruction, and taking a value from the general register; The execution module is responsible for executing various arithmetic operations; And the write-back module is used for recording the information of the memory access instruction and writing the data read from the memory into the general register.

Description

technical field [0001] The invention relates to the field of digital integrated circuit design, and more particularly, to a four-stage pipeline RISC-V processor with a fast data bypass structure. Background technique [0002] In recent years, with the rapid development of Internet of Things technology, the market has an increasing demand for low-power, high-performance processors used in smart terminals. How to reduce the cost and power consumption while meeting the performance requirements of the intelligent terminal on the processor is a relatively popular research direction. The RISC-V instruction set is an open source instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). Compared with the mainstream ARM and x86 instruction sets, RISC-V has the following advantages: [0003] 1. The RISC-V Foundation does not charge any licensing fees. The RISC-V instruction set itself is completely open source and uses the BSD protocol. ...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 谭洪舟何逸飞路崇魏新元谢舜道廖普辉梁羽开周永坤
Owner SUN YAT SEN UNIV
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