A four-stage assembly line RISC-V processor with a rapid data bypass structure

Abstract

The invention provides a four-stage assembly line RISC-V processor with a rapid data bypass structure. The processor has a four-stage pipeline structure, when the operation except the non-Load instruction is executed, the direct bypass is carried out, and the effective data pipeline is changed into three stages, so that the operation speed is increased. Compared with a traditional four-level assembly line, the structure reduces the instruction period of most instructions and the frequency of occurrence of data danger, and greatly improves the performance of the processor. And the four-stage pipeline structure comprises an instruction fetching module, a decoding module, an execution module and a write-back module. The fetch module can generate a PC of a next instruction according to the instruction fetched from the instruction memory in the current period and an external control signal; The decoding module is used for extracting an operation code, a function code, a source register, a destination register and an immediate of the instruction, and taking a value from the general register; The execution module is responsible for executing various arithmetic operations; And the write-back module is used for recording the information of the memory access instruction and writing the data read from the memory into the general register.

Description

technical field [0001] The invention relates to the field of digital integrated circuit design, and more particularly, to a four-stage pipeline RISC-V processor with a fast data bypass structure. Background technique [0002] In recent years, with the rapid development of Internet of Things technology, the market has an increasing demand for low-power, high-performance processors used in smart terminals. How to reduce the cost and power consumption while meeting the performance requirements of the intelligent terminal on the processor is a relatively popular research direction. The RISC-V instruction set is an open source instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). Compared with the mainstream ARM and x86 instruction sets, RISC-V has the following advantages: [0003] 1. The RISC-V Foundation does not charge any licensing fees. The RISC-V instruction set itself is completely open source and uses the BSD protocol. ...

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Problems solved by technology

The invention patent with the authorized announcement number CN 101256546A discloses a 32-bit microprocessor, but the instruction set used is defined by the inventor himself, which is not universal, and there is no supporting tool chain support

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