15 results about "Reduced instruction set computing" patented technology

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

Systems and methods for handling communications between a host Operating System (OS) application and a display controller through an Embedded Controller (EC) are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive, by a kernel driver of a host OS, a message from a host OS application; and at least in part in response to a determination that the processor comprises a Reduced Instruction Set Computer (RISC) processor, send a request to an EC, where the request is configured to cause the EC to trigger a display's Built-In Self-Test (BIST) by a display controller.

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. The embedded controller may be bridged to the ARM based architecture SoC using a bridging agent that bridges enhanced serial peripheral interface (eSPI) format communication to system power management interface (SPMI) format communication.

A method for reporting a hot-swap error, a processor architecture, a device, and a storage medium are provided by an embodiment of the present application. The method is applied to an advanced reduced instruction-set computer (RISC) machine (ARM) platform, the ARM platform includes a baseboard management controller (BMC), an operating system (OS), and a basic input output system (BIOS). Data transmission between the BMC and the OS is performed based on a data interface service configured via the BIOS. During operation of the ARM platform, in response to a system control processor (SCP) in the BIOS detecting a PCIe CE type reporting error information corresponding to any interface, the SCP transmits the PCIe CE type reporting error information to the BMC and the OS.

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. A modified ARM SoC having a single wire interface communication interface may be provided and connected to an embedded controller using a single wire interface. Thermal measurements made by the modified ARM SoC may be provided to the embedded controller across the single wire interface for the embedded controller to provide active and / or passive cooling for the data processing system.

The system may speed up reduced instruction set computing / single instruction, multiple data (RISCV / SIMD) vector processing (VP) by adding a register circuit for an additional vector register file for a total of two VRF registers. One of the VRF registers may be used for data transfers to and from memory, and the other VRF register may be used for arithmetic logic unit (ALU) operands. The VRFs may be switched alternatively to perform the data transfers and operands.

Techniques perform data processing. Such techniques involve obtaining, by a first operating system, first data of a storage system from a data collector. Such techniques further involve synchronizing the first data from the first operating system to a second operating system, wherein an architecture of the second operating system is different from that of the first operating system. Such techniques further involve, in response to that the first operating system has a failure, obtaining, by the second operating system, second data of the storage system from the data collector. Such techniques further involve, in response to that the first operating system is recovered, synchronizing the second data from the second operating system to the first operating system. Accordingly, such techniques can minimize processing time, ensure high availability of data collection, save computing and memory resources of a storage system, and help improve user experience.

The system may speed up reduced instruction set computing / single instruction, multiple data (RISCV / SIMD) vector processing (VP) by adding a register circuit for an additional vector register file for a total of two VRF registers. One of the VRF registers may be used for data transfers to and from memory, and the other VRF register may be used for arithmetic logic unit (ALU) operands. The VRFs may be switched alternatively to perform the data transfers and operands.

The invention discloses a duplicating propagation optimization method oriented to a vectorized predicate execution instruction sequence, and belongs to the field of compilation optimization. Aiming at the problems that an existing copying propagation method is difficult to adapt to strong coupling characteristics of vector variables and predicate registers, identification of copying instructions with predicate domains is insufficient, and cross-basic-block analysis is not adaptive to predicate control flows, the instructions are divided according to whether the predicate domains are contained or not, and only non-predicate instructions are optimized; constructing a control flow graph with predicates and a vector variable-register mapping and DU / UD chain; identifying a local and global rewriting relationship by combining predicate field verification; and a safety propagation rule is designed by adapting to hardware characteristics, and full-process automatic optimization is realized. According to the method, redundant memory access and register operation are reduced, code execution efficiency is improved, manual optimization dependence is reduced, the method is adaptive to architectures based on reduced instruction set computing (RISC), single instruction multiple data (SIMD), VLIW and the like, and the method is particularly suitable for high-performance computing and other scenes based on the RISC principle.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A bladder volume monitoring system based on Advanced Reduced Instruction Set Computing Machines (ARM), characterized in that it comprises: a three-chamber urinary catheter (2), an air supply channel (26), a fluid supply channel (25), and a fluid drainage channel (27); wherein one end of the three-chamber urinary catheter (2) is positioned inside a bladder (24) during use, and the other end of the three-chamber urinary catheter (2) is provided with three openings, each being an air opening (21), a fluid supply opening (22), and a fluid drainage opening (23); wherein the air inlet end of the air supply channel (26) is connected to an external air source, and the air outlet end of the air supply channel (26) is connected to the air opening (21);wherein the fluid inlet end of the fluid supply channel (25) is connected to an external fluid container and the fluid outlet end of the fluid supply channel (25) is connected to the fluid supply port (22); wherein the fluid inlet end of the fluid drainage channel (27) is connected to the fluid drainage port (23) and the fluid outlet end of the fluid drainage channel (27) is connected to an external container; wherein the end of the three-chamber urinary catheter (2) located inside the bladder (24) is provided with several three-chamber urinary catheter fluid inlet ports (22a) connected to the fluid supply port (22) and a three-chamber urinary catheter fluid drainage port (23a) connected to the fluid drainage port (23);wherein the end of the three-chamber urinary catheter (2) located inside the bladder (24) is further equipped with a balloon (20), and the balloon (20) is connected to the air opening (21); wherein a sensor (16) is arranged on the fluid supply channel (25), and the sensor (16) serves to monitor the pressure in the fluid supply channel (25) in order to determine the pressure in the bladder (24).

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. The embedded controller may be bridged to the ARM based architecture SoC using a bridging agent that bridges enhanced serial peripheral interface (eSPI) format communication to system power management interface (SPMI) format communication.

A method for reporting a hot-swap error, a processor architecture, a device, and a storage medium are provided by an embodiment of the present application. The method is applied to an advanced reduced instruction-set computer (RISC) machine (ARM) platform, the ARM platform includes a baseboard management controller (BMC), an operating system (OS), and a basic input output system (BIOS). Data transmission between the BMC and the OS is performed based on a data interface service configured via the BIOS. During operation of the ARM platform, in response to a system control processor (SCP) in the BIOS detecting a PCIe CE type reporting error information corresponding to any interface, the SCP transmits the PCIe CE type reporting error information to the BMC and the OS.

Systems and methods for using an embedded controller (EC) integrated into a heterogenous computing platform as a hardware Root-of-Trust (RoT). In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled thereto; and an EC integrated into the heterogeneous computing platform, wherein the EC is configured to operate as a hardware RoT for at least one of: the IHS, or the heterogeneous computing platform.

Methods and systems for managing cooling of a data processing system. In particular, active cooling using a fan controlled by an embedded controller is provided in a data processing system having a processor installed on a system on a chip (SoC) that is originally only capable of providing passive cooling to the data processing system through throttling of the processor. The system temperature of the data processing system may be communicated from the SoC to the embedded controller using an application digital signal processor (ADSP) configured to communicate with the embedded controller using an inter-integrated circuit (I2C) / improved inter-integrated circuit (I3C) interface.