89results about "Conditional code generation" patented technology

The invention discloses an agent configuration method and device based on front-end interaction and a medium, and relates to the technical field of computers.The method comprises the steps that a user interaction behavior is received through a front-end interaction interface, the user interaction behavior is analyzed, and a corresponding response instruction is generated; executing the response instruction, creating a plurality of agent nodes, and configuring corresponding role information; determining a task dependency relationship between the agent nodes, and constructing an agent node relationship graph through a preset task execution rule; receiving and analyzing a to-be-executed task, extracting required agent role information, determining to-be-executed agent nodes, and determining a to-be-executed sequence corresponding to the to-be-executed agent nodes according to the agent node relation graph; and calling the agent models corresponding to the to-be-executed agent nodes in sequence, executing the to-be-executed task, and updating the state parameters. Through deep fusion of front-end visual interaction and automatic process arrangement, the intuition and efficiency of the configuration process are improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes such as personal intelligence, financial science and technology, medical health and the like, and discloses an action instruction sequence generation method, device, equipment and medium. Generating an attention weight based on the visual feature vector and the tactile feature vector, fusing the visual feature vector and the tactile feature vector to generate a fusion feature vector, and constructing a reinforcement learning model state space containing environment state information and the fusion feature vector; a sequence of action instructions is generated by a reward function in response to a task target approach event or an obstacle collision event based on the state space. According to the method, through combination of multi-modal information fusion and reinforcement learning state space construction, the perception ability and action decision-making ability of the intelligent agent in a complex environment are improved, and autonomy, flexibility and stability of task execution are remarkably enhanced.

The invention relates to the technical field of knitting, and discloses a circular weft knitting machine multi-jacquard process weaving method, device and equipment and a storage medium, the method is used for splicing process files so as to achieve multi-jacquard continuous weaving operation of circular weft knitting machines, and the method comprises the steps of obtaining target cloth design requirements, and according to the target cloth design requirements, obtaining a multi-jacquard process of the circular weft knitting machines; determining a jacquard pattern number, a jacquard pattern weaving frequency and a jacquard pattern weaving sequence corresponding to the target cloth design requirement, and querying from a pre-constructed process file library according to the jacquard pattern number to obtain a process file corresponding to the jacquard pattern number, splicing the process files according to the jacquard pattern weaving times and the jacquard pattern weaving sequence to generate a spliced file; analyzing the spliced file to obtain weaving data corresponding to the target cloth design requirement; and generating a weaving instruction according to the weaving data to control the circular weft knitting machine to perform weaving operation.

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention relates to the technical field of intelligent network connection, in particular to a driving task arrangement generation method and device, a vehicle, a medium and a program product, and the method comprises the steps: obtaining task information and resource information of at least two tasks in driving task arrangement; determining at least one optimization target of task arrangement based on the task information and the resource information; and inputting the task information and the resource information into a pre-trained large language model to output initial task scheduling data meeting at least one optimization target, and verifying the initial task scheduling data until task scheduling data meeting a preset verification condition is obtained. Therefore, the problems that in the related technology, manual analysis is prone to errors, the management efficiency is low, and the actual use scene cannot be adapted are solved; model processing depends on a fixed rule, is lack of dynamic scheduling capability, increases response delay of a system, causes task timeout, and cannot guarantee reliability and safety of a driving task.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a set of graphics instructions. The apparatus may also determine whether each graphics instruction in the set of graphics instructions is associated with a resonance frequency that is above or below a threshold. Further, the apparatus may adjust an activity level for each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold.

In response to an authentication code generating class of instruction, processing circuitry generates an authentication code associated with an authentication target value by applying a code generating function to the authentication target value, a key, a first modifier value and a second modifier value. For an authentication code setting instruction, the generated authentication code is written to a destination register. For an authentication code checking instruction, the processing circuitry checks whether the authentication code generated based on the authentication target value in response to the authentication code checking instruction corresponds to a reference authentication code obtained from a source register, and triggers an error response when they do not correspond. The first modifier value comprises a stack-pointer- dependent value. For at least one of the authentication code setting / checking instructions, the second modifier value comprises a program-counter-dependent value.

The embodiment of the invention provides a control program generation method and device of equipment, the equipment and a medium. The method comprises the steps that a program generation request of a user for target equipment is received; the program generation request comprises equipment information of target equipment and a target control instruction of the target equipment; determining a use scene of the target equipment according to the equipment information of the target equipment; determining a dependency relationship of the target control instruction according to the use scene of the target equipment; the dependency relationship is a relationship between a target control instruction and at least one other control instruction required to be executed for realizing the target control instruction; and determining a target control program according to the dependency relationship of the target control instruction. According to the embodiment of the invention, the target control instruction of the user is combined with the equipment information and mapped to the specific equipment use scene, the control dependency relationship and the constraint condition are identified based on the use scene, the control program conforming to the actual working condition is generated, manual code writing is not needed, and the industrial control program development efficiency and scene adaptability are improved.

An instruction configured to perform data conversion is executed. The executing the instruction includes determining that an overflow condition exists in a change of a value, specified by the instruction, from one data format to another data format. It is determined that an overflow result control of the instruction is set to a selected value. A result of executing the instruction is provided. The providing the result includes placing a chosen default value in a result location based on determining that the overflow condition exists and that the overflow result control is set to the selected value.

A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

Provided in the present disclosure are a command processing circuit, a command processing method, and a PIM apparatus. The command processing circuit comprises: a PIM command identification module, which is electrically connected to a command address bus of a PIM apparatus and is configured to receive a command signal by means of the command address bus, determine the type of the currently received command signal, send, when it is determined that the currently received command signal is a conventional DRAM command, the command signal to a conventional command processing module, and send, when it is determined that the currently received command signal is a PIM-related command, the command signal to a PIM command processing module; the PIM command processing module, which is electrically connected to the PIM command identification module and is configured to receive the PIM-related command, decode the PIM-related command, and perform a corresponding operation on the basis of a decoding result; and the conventional command processing module, which is electrically connected to the PIM command identification module and is configured to receive the conventional DRAM command and decode the conventional DRAM command. The present disclosure is at least conducive to avoiding mode switching and improving system performance.

The present application relates to the technical field of artificial intelligence, is applied to robot control, machine vision, automatic driving and other business scenes, performs action prediction by using an action prediction model obtained by performing potential action pre-training and real action post-training based on an unsupervised mode, can effectively improve the accuracy of action prediction, and improves the accuracy of action prediction. And therefore, the probability of operation errors when task operation is performed according to the predicted action is reduced. Relates to an action prediction method and device, equipment and a medium. The method comprises the following steps: acquiring video stream data of a target object and a language instruction corresponding to the video stream data; inputting a language instruction corresponding to the video stream data and the video stream data into a trained action prediction model for action prediction to obtain an action prediction result, the action prediction model being a model obtained by performing potential action pre-training and real action post-training based on an unsupervised mode in advance; and determining an action instruction according to the action prediction result, and controlling the target object to perform task operation based on the action instruction.

The embodiment of the invention discloses an excitation instruction generation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and aims to quickly generate an excitation instruction for an abnormal test and effectively reduce test case generation time. The method comprises the following steps: acquiring a standard instruction set and abnormal condition description information of the standard instruction set; wherein the standard instruction set comprises a standard instruction; the abnormal condition description information comprises an interrupt vector number and an interrupt error code; according to the abnormal condition description information, abnormal error injection codes are constructed for the standard instructions in the standard instruction set; and generating an excitation instruction for an abnormal test based on the standard instruction and the abnormal error injection code. The method is suitable for excitation instruction generation.

A processor is able to re-encode a normal value of a first floating point format to a normalized floating point format, and re-encode a subnormal value of the first floating point format to the normalized floating point format. A subset of the exponent bits of the exponent field of a normalized floating point format is used to encode a predetermined indication of being an exceptional value, wherein a combination of bit values used to encode this predetermined indication does not occur within a range of the exponent field of the normalized floating point format used to represent any possible non-exceptional, normal and subnormal values.

The invention discloses an instruction generation method and device, equipment, a storage medium and a program product, and relates to the technical field of machine learning. The method comprises the following steps: acquiring a first natural language instruction, wherein the first natural language instruction is used for indicating to realize a first function through computer equipment; obtaining a function vector set, wherein the function vector set comprises function feature vectors corresponding to a plurality of performance functions respectively; recalling at least one candidate performance function meeting a correlation degree requirement from a function vector set based on a vector correlation degree between a first feature vector corresponding to the first natural language instruction and a plurality of function feature vectors; based on the first natural language instruction and the at least one candidate performance function, an equipment driving instruction is constructed, and the content of the equipment driving instruction comprises a target performance function in the at least one candidate performance function and a first parameter of the target performance function when the first function is achieved, the first parameter is a function parameter obtained based on analysis of the first natural language instruction.

A method, device, and system for performing a partial sum accumulation of a product of input vectors and weight vectors in a wordwise-input and bitwise-weight manner results in a partial accumulated product sum. The partial accumulated product sum is compared with a threshold condition after each weight bit, and when the partial accumulated product sum meets the threshold condition, a skip indicator is asserted to indicate that remaining computations of a sum accumulation are skipped.

There is included a method and apparatus comprising computer code configured to cause a processor or processors to perform obtaining an input of at least one of a task and a workflow, setting a timeout for the input of the at least one of the task and the workflow, determining whether the at least one of the task and the workflow observes a lack of data of the input for a duration equal to the timeout, determining, in response to determining that the at least one of the task and the workflow observed the lack of data of the input for the duration equal to the timeout, an unavailability of further data of the input, applying an update to the at least one of the task and the workflow based on determining the unavailability, and processing the at least one of the task and the workflow.

The application provides an independent graphics card management method, an independent graphics card and an electronic device. The method comprises: a first programmable management module performing graphics card service management, comprising obtaining a command from a host memory through a host bus interface, interpreting the command into an instruction, and controlling a sub-engine in the independent graphics card to execute the instruction; and a second programmable management module performing graphics card system management, comprising managing power-on initialization, reset and working performance dynamic adjustment of the sub-engine in the independent graphics card, and managing power-on initialization of graphics card memory. The method simplifies hardware logic, the two management modules have clear division of labor, service management and system management are isolated, and the system is safer and more stable.

The application discloses a multi-device timing control method, which performs timing control on each to-be-executed instruction, and executes each to-be-executed instruction based on an execution time sequence, so that the instruction sending precision reaches a sub-millisecond level, and the high real-time task requirement is met. In addition, the address jump function is used for realizing dynamic instruction adjustment, adapting to various task scenes, and improving the flexibility of multi-device timing control. In addition, the block random access memory and the nonvolatile memory support a plurality of large-scale instruction sets, reduce rewriting overhead, and can reduce hardware upgrade cost, extend functions through software configuration, and improve system reusability.

This disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. The method includes: responding to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the second prediction result differing from the first prediction result, using the second prediction result to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

Techniques are disclosed involving fusing instruction pairs and executing corresponding fused instruction operations. A processor includes fusion detection circuitry to detect a pair of fetched instructions and fuse the instructions into a fused instruction operation, and execution circuitry to execute the fused instruction operation. In one embodiment, a first instruction is executable to perform an operation and a second instruction is executable to adjust a sign of a result of the operation. In another embodiment, the first instruction is executable to perform an operation and the second instruction is executable to find a maximum or minimum, as compared to a comparison operand, of a result of the operation. In another embodiment, the first instruction is executable to perform a vector operation and the second instruction is executable to read a first element of the vector result and overwrite one or more additional elements of the vector result.

The application provides an instruction issuing method and device, electronic equipment and readable storage medium. The method comprises: constructing a track section graph and displaying based on track collection point data to be processed; in response to a selection interaction operation of a user on a section contained in the track section graph, determining a target section group indicated by the selection interaction operation, and determining an operation instruction corresponding to the selection interaction operation; and issuing the operation instruction to a target section contained in the target section group. Instead of determining the section to be controlled by manual input, the target section is selected and the operation instruction is selected by constructing the track section graph, displaying the track section graph to the user, and the user performing the selection interaction operation on the section in the track section graph. The user does not need to manually input, which reduces the complexity of determining the target section to a certain extent, and improves the efficiency of issuing the instruction to the target section.

The invention relates to the technical field of RPA, in particular to a batch task monitoring method and device, equipment and a storage medium, and the method comprises the steps: obtaining basic task data, and setting a control parameter corresponding to the basic task data; generating a batch task checking instruction based on the basic task data and the control parameters; matching the basic task data with a batch task checking instruction corresponding to the control parameter to obtain a target checking instruction; and executing the target inspection instruction to obtain an execution result, and monitoring a batch task corresponding to the target inspection instruction based on the execution result and the control parameter. According to the invention, the reliability and efficiency of monitoring the batch tasks can be improved.

The invention provides an 8Fs instruction receiving and IO control method in array server UART communication based on an FPGA, belongs to the technical field of array server hardware control, and is suitable for multi-node server cluster hardware management. According to the method, a purple light syncretic PGL50H-6FG484 FPGA is adopted as a main control unit, and a BMC sends a 0x8F single-byte 8Fs instruction through a UART (Universal Asynchronous Receiver / Transmitter); and after receiving the instruction, the FPGA analyzes the operation command through a frame header, an equipment address and additional data verification, matches 20 calculation modules, outputs an IO control signal, and simultaneously acquires the state of the module and returns the state to the BMC. The BMC is triggered to give an alarm through continuous three times of invalid instructions, and a flash enable signal and a power supply control signal are interlocked. According to the method, the UART control accuracy and reliability are improved, hardware resources are efficiently utilized, and the system security is enhanced.

The disclosure relates to a processor which can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floa

The disclosure relates to a processor which can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floating point format to a normalized narrower floating point format. According to the disclosure, when performing a wider-format sign injection operation on a NaN-boxed value of the normalized narrower floating point format held in a source register of a set of normalized-format registers, a bit manipulation is performed on a bit in the respective source register at a most-significant bit-position of the normalized wider floating point format. And when de-normalizing the NaN-boxed value of the normalized narrower floating point format from the respective source register, the bit at the most-significant bit-position of the normalized wider floating point format is ignored in detecting NaN-boxing.

This application provides an instruction generation method, apparatus, and storage medium. It receives instruction parameters through a unified interface of a preset instruction category, whereby the instruction parameters include at least two operands and an output address. The method determines the representation of each operand based on the instruction parameters and generates a corresponding target instruction based on the operand representation and the instruction parameters. This application provides only a unified interface for receiving instruction parameters from the user for the preset instruction category. The compiler automatically selects and generates target hardware instructions adapted to the user-input instruction parameters. Users do not need to concern themselves with multiple hardware instructions, nor do they need to select or write corresponding API interface programs for each hardware instruction, thus providing convenience for users and avoiding the cumbersome process of writing corresponding APIs for each hardware instruction, and reducing the complexity of programs and documentation.

The embodiment of the invention provides a request scheduling method and computing equipment, the method is applied to management equipment, and the management equipment manages at least one computing equipment through a baseboard management controller (BMC) of the computing equipment. The method comprises the steps of obtaining a target management request for target computing equipment; sending a target management request to the target BMC under the condition that the target BMC is determined to meet a first condition based on the system load of the target BMC; wherein the target BMC is the BMC of the target computing device, and the first condition is used for representing that the target BMC has the capability of processing the target management request. The management request is sent to the BMC only when it is determined that the BMC has the capability of processing the management request based on the system load of the BMC. Therefore, it is ensured that the BMC can normally process the received management request based on the own chip performance, and a series of problems caused by the fact that the BMC performance is difficult to meet the high-concurrency request are avoided.

The invention is in the field of computer technology. The invention describes an architecture of a safety automation system and a method for safely autonomously operating a technical device. The architecture solves the problem that every possible Byzantine error, whether caused by an accidental malfunction of hardware, a design error in software or an intrusion, must be identified and contained, so that no safety-relevant event occurs. The architecture consists of four largely independent subsystems, which are arranged hierarchically and each form an encapsulated fault containment unit. At the top of the hierarchy is the safety subsystem, i.e. the fault-tolerant decision subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are unsafe because they contain complex software. It is empirically difficult to find all design errors in a complex software system and to prevent intrusions. Due to redundancy and diversity, every error of the unsafe subsystems is masked so that no safety-critical malfunction occurs.