259results about "Conditional code generation" patented technology

The invention provides an in-memory computing AI accelerator design architecture based on an RISC-V architecture and a control method. The architecture comprises an RISC-V processor used for executing a general-purpose computing task and a control instruction; the in-memory computing accelerator is used for executing a computing task in an AI algorithm, is connected with the RISC-V processor and comprises a tensor processing unit and a vector processing unit; the in-memory computing accelerator further comprises a data rearrangement unit which is used for carrying out format conversion and rearrangement on the data before the data are transmitted to the tensor processing unit or the vector processing unit. And the data format management unit is used for defining and managing a unified data format in the in-memory computing accelerator. According to the invention, the calculation performance and the resource utilization rate of the AI algorithm can be improved, and meanwhile, the accuracy of data transmission and the parallelism of processing are ensured.

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

The invention discloses an off-line function verification system for an intelligent electric actuating mechanism, and the system comprises an off-line function verification unit which achieves the data interaction through the connection with a system signal terminal unit of the intelligent electric actuating mechanism, so as to achieve the off-line function verification function of the intelligent electric actuating mechanism. The offline function verification unit is an integrated module and comprises a man-machine interaction module, a host control module, an interface module, an instruction control module, a control power supply control module and a power supply control module; the problems that a large amount of manpower and time are consumed, the test process is tedious, the work efficiency of the original test process is low, human errors and test record detection errors are prone to occurring, data analysis depends on manpower, and the error risk is increased due to the fact that a traditional test method at the present stage consumes operations such as frequently changing used tools and modifying wiring in the test process are solved.

The invention relates to the technical field of processor design and test, and discloses an instruction sequence generation method for verifying floating point operation of a processor, which comprises the following steps: constructing a floating point test coverage model, generating a floating point test database, and constructing a basic RISC-V instruction sequence generator; adding a register updating mechanism bound with a memory on the basis of the basic instruction RISC-V sequence generator, and generating initialized data of the memory; and injecting the generated instruction machine code and the memory initialization data into the memory of the processor to be verified for simulation, and comparing the execution track obtained by simulation with the execution track of the instruction set simulator to find potential errors in the processor. According to the method, an efficient coverage model is constructed to generate representative floating point test data, a floating point data path of the processor can be verified more comprehensively, the defects of an existing method in the aspect of floating points in the RISC-V instruction generation process are overcome, and potential design defects in the processor are found.

Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.

The invention discloses an agent configuration method and device based on front-end interaction and a medium, and relates to the technical field of computers.The method comprises the steps that a user interaction behavior is received through a front-end interaction interface, the user interaction behavior is analyzed, and a corresponding response instruction is generated; executing the response instruction, creating a plurality of agent nodes, and configuring corresponding role information; determining a task dependency relationship between the agent nodes, and constructing an agent node relationship graph through a preset task execution rule; receiving and analyzing a to-be-executed task, extracting required agent role information, determining to-be-executed agent nodes, and determining a to-be-executed sequence corresponding to the to-be-executed agent nodes according to the agent node relation graph; and calling the agent models corresponding to the to-be-executed agent nodes in sequence, executing the to-be-executed task, and updating the state parameters. Through deep fusion of front-end visual interaction and automatic process arrangement, the intuition and efficiency of the configuration process are improved.

The invention relates to a control method, device and equipment of a combine harvester, a storage medium and a product. The control method of the combine harvester comprises the following steps: acquiring target parameters of a target combine harvester; generating a control instruction according to the target parameter and the parameter threshold; and according to the control instruction, controlling and adjusting operation parameters of the target combine harvester. By the adoption of the method, grain loss can be effectively reduced, the grain breakage rate is reduced, the cleanliness of the grains is improved, and then the overall quality of grain harvesting is improved. Besides, manual intervention is not needed in the process, dependence on experience of operators can be reduced, the problems of improper parameter adjustment and the like caused by errors in the manual adjustment process are avoided, and stability and consistency of operation parameters are ensured.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes such as personal intelligence, financial science and technology, medical health and the like, and discloses an action instruction sequence generation method, device, equipment and medium. Generating an attention weight based on the visual feature vector and the tactile feature vector, fusing the visual feature vector and the tactile feature vector to generate a fusion feature vector, and constructing a reinforcement learning model state space containing environment state information and the fusion feature vector; a sequence of action instructions is generated by a reward function in response to a task target approach event or an obstacle collision event based on the state space. According to the method, through combination of multi-modal information fusion and reinforcement learning state space construction, the perception ability and action decision-making ability of the intelligent agent in a complex environment are improved, and autonomy, flexibility and stability of task execution are remarkably enhanced.

The invention relates to the technical field of knitting, and discloses a circular weft knitting machine multi-jacquard process weaving method, device and equipment and a storage medium, the method is used for splicing process files so as to achieve multi-jacquard continuous weaving operation of circular weft knitting machines, and the method comprises the steps of obtaining target cloth design requirements, and according to the target cloth design requirements, obtaining a multi-jacquard process of the circular weft knitting machines; determining a jacquard pattern number, a jacquard pattern weaving frequency and a jacquard pattern weaving sequence corresponding to the target cloth design requirement, and querying from a pre-constructed process file library according to the jacquard pattern number to obtain a process file corresponding to the jacquard pattern number, splicing the process files according to the jacquard pattern weaving times and the jacquard pattern weaving sequence to generate a spliced file; analyzing the spliced file to obtain weaving data corresponding to the target cloth design requirement; and generating a weaving instruction according to the weaving data to control the circular weft knitting machine to perform weaving operation.

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention provides a single lamp control instruction generation method and device based on a large model, and the method comprises the steps: a user inputs a question to a main controller through a client, the client generates a session, the main controller calls the large model, achieves the intelligent semantic understanding through the large model, and transmits the session to a vector database. A vector database searches corresponding agent information, the agent information is enhanced according to a session and a single lamp control system, a single lamp control agent is generated, a large model generates instruction information, optimization verification is carried out, and diversified user requirements can be automatically met; the method is based on an existing architecture, can be easily expanded to cope with more complex scenes and requirements, and has good maintainability and upgradability; various technologies and platforms are integrated, the efficiency and the cost effectiveness are greatly improved, the device can achieve efficient and intelligent instruction generation and execution by applying the method, and the overall reliability of user experience is improved.

The invention relates to a chip configuration method and device, computer equipment and a storage medium. The method comprises the following steps: receiving a trigger instruction sent by an external host, wherein the trigger instruction is used for triggering a configuration agent module; configuration instructions in an external memory are obtained in batches through the configuration agent module, and the configuration instructions are stored in a buffer area of the configuration agent module; the configuration instructions are read one by one from the buffer area, the configuration instructions comprise control instructions and expression instructions, and one control instruction and a plurality of expression instructions form an expression sequence; and sequentially executing the configuration instructions in the expression sequence to configure the programmable register of the target module. By adopting the method, the control instruction can be obtained and executed through the configuration agent module, tedious, fixed or repeated function module configuration work executed by the processor is replaced, and the computing power of the processor is released.

The invention relates to the technical field of intelligent network connection, in particular to a driving task arrangement generation method and device, a vehicle, a medium and a program product, and the method comprises the steps: obtaining task information and resource information of at least two tasks in driving task arrangement; determining at least one optimization target of task arrangement based on the task information and the resource information; and inputting the task information and the resource information into a pre-trained large language model to output initial task scheduling data meeting at least one optimization target, and verifying the initial task scheduling data until task scheduling data meeting a preset verification condition is obtained. Therefore, the problems that in the related technology, manual analysis is prone to errors, the management efficiency is low, and the actual use scene cannot be adapted are solved; model processing depends on a fixed rule, is lack of dynamic scheduling capability, increases response delay of a system, causes task timeout, and cannot guarantee reliability and safety of a driving task.

Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

Techniques for explicit integrity check value initialization are described. In an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the single instruction, including storing data indicated by the single instruction into the destination location, and storing the ICV in the memory.

Disclosed in the present application is a tensor processing unit. The tensor processing unit comprises: an instruction sequence module, which is configured to generate a first instruction sequence and / or a second instruction sequence on the basis of a tensor operation instruction and preset configuration information, wherein the first instruction sequence comprises a plurality of first operation instructions, the second instruction sequence comprises a plurality of second operation instructions, and the preset configuration information comprises first configuration information and / or second configuration information; a data loading module, which is configured to sequentially load, on the basis of the first instruction sequence or the second instruction sequence, into corresponding registers data to be operated; a first computing module, which is configured to sequentially read, on the basis of the first instruction sequence, data from the registers, so as to perform in-memory computing; and a second computing module, which is configured to sequentially read, on the basis of the second instruction sequence, data from the registers, so as to perform non-in-memory computing. Further provided in the present application is a tensor processing method. A unified macro instruction is used to call different computing modules for in-memory computing or non-in-memory computing, thereby reducing the programming complexity and improving the computing efficiency.

The invention discloses a multi-dimensional sensing system, device and method based on an end-side large model, and the method comprises the steps: obtaining multi-modal sensor data in real time, including environment data, audio data and visual motion data; based on the signal variation, the historical standard deviation and the preset environment weight of each sensor, an environment anomaly index is calculated in combination with the time period factor; calculating a user intention confidence coefficient based on a cross-correlation value of the audio data and the visual motion data, a visual motion information entropy and a personnel existence probability; and when the environment anomaly index is greater than a preset safety threshold value or the user intention confidence coefficient is greater than a preset intention threshold value, triggering an end-side large model to analyze multi-modal sensor data and generate a control instruction. The invention relates to the technical field of multi-dimensional perception, and solves the technical problems of overhigh equipment energy consumption and potential safety hazard early warning lag caused by large-model real-time reasoning in a smart home scene.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

Disclosed are an instruction generation method and an electronic device. The method includes: determining an input memory layout and an output memory layout that correspond to a data transfer operator, and a transfer parameter of the data transfer operator; determining conversion path groups for converting the input memory layout to the output memory layout based on the transfer parameter, the input memory layout, the output memory layout, and multiple first layouts supported by a neural network processor; determining a target conversion path based on conversion path groups; and generating an instruction sequence executable by the processor based on the target conversion path. According to this disclosure, during processing of the data transfer operator, an optimal path can be determined from the path groups to serve as the target conversion path, the instruction sequence executable by the processor can be generated based on the target conversion path.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a set of graphics instructions. The apparatus may also determine whether each graphics instruction in the set of graphics instructions is associated with a resonance frequency that is above or below a threshold. Further, the apparatus may adjust an activity level for each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold.

Disclosed are an instruction generation method and apparatus and an electronic device. The method includes: determining first parameter information of a memory transfer operator and a first memory layout corresponding to input feature data; determining a second memory layout supported by a hardware unit executing the memory transfer operator; in response to that the first memory layout is different from the second memory layout, determining whether the first memory layout meets a rearrangement condition; and in response to that the first memory layout meets the rearrangement condition, generating an executable instruction for the neural network processor based on the first parameter information, the first memory layout, and the second memory layout. According to technical solutions of this disclosure, the input feature data can be accessed according to a memory layout supported by the neural network processor, without designing an additional memory layout conversion instruction, thereby reducing instruction overhead.

In response to an authentication code generating class of instruction, processing circuitry generates an authentication code associated with an authentication target value by applying a code generating function to the authentication target value, a key, a first modifier value and a second modifier value. For an authentication code setting instruction, the generated authentication code is written to a destination register. For an authentication code checking instruction, the processing circuitry checks whether the authentication code generated based on the authentication target value in response to the authentication code checking instruction corresponds to a reference authentication code obtained from a source register, and triggers an error response when they do not correspond. The first modifier value comprises a stack-pointer- dependent value. For at least one of the authentication code setting / checking instructions, the second modifier value comprises a program-counter-dependent value.

The embodiment of the invention provides a control program generation method and device of equipment, the equipment and a medium. The method comprises the steps that a program generation request of a user for target equipment is received; the program generation request comprises equipment information of target equipment and a target control instruction of the target equipment; determining a use scene of the target equipment according to the equipment information of the target equipment; determining a dependency relationship of the target control instruction according to the use scene of the target equipment; the dependency relationship is a relationship between a target control instruction and at least one other control instruction required to be executed for realizing the target control instruction; and determining a target control program according to the dependency relationship of the target control instruction. According to the embodiment of the invention, the target control instruction of the user is combined with the equipment information and mapped to the specific equipment use scene, the control dependency relationship and the constraint condition are identified based on the use scene, the control program conforming to the actual working condition is generated, manual code writing is not needed, and the industrial control program development efficiency and scene adaptability are improved.

Systems and methods for synchronizing enhanced global markers of a coprocessor. An example processor system includes a plurality of co-processors configured to compute processing tasks, where an individual co-processor is connected to individual remaining co-processors via a plurality of connections, where each connection from a co-processor to a different co-processor is configured to be asserted or de-asserted, the plurality of co-processors are configured to indicate a state associated with a global tag of the plurality of global tags, and wherein the global tag is set based on the plurality of co-processors asserting the global tag.

Systems and methods for enhanced global flags for synchronizing coprocessors. An example processor system includes a plurality of coprocessors configured to compute a processing task, wherein individual coprocessors are connected to individual remaining coprocessors via a plurality of connections, wherein each connection from a coprocessor to a different coprocessor is configured to be asserted, or de-asserted, to indicate a status associated with a global flag of a plurality of global flags, and wherein the global flag is set based on the plurality of coprocessors asserting the global flag.

The invention discloses a method for generating a test case in a satellite program control execution process, which comprises the following steps of: classifying instructions by collecting instruction characteristics in the satellite program control process, and establishing a program control output instruction library; collecting execution process characteristics in a satellite program control process, and establishing a program control instruction process table; and setting a test characteristic value as required, reading the program control instruction process table according to the test characteristic value, and generating a corresponding test program sequence. All paths of the specified program control instruction sequence can be effectively covered, paths of the program control instruction sequence related to the specified test characteristic value can be accurately covered, and the efficiency, coverage and effectiveness of the satellite program control instruction sequence test are improved.

Devices and methods of operating such devices are disclosed. Vector processing circuitry performs data processing in a plurality of parallel processing channels, wherein the data processing is performed in a subset of the plurality of parallel processing channels, the subset being determined by set bit values ​​of a vector predicate. Predicate monitoring circuitry is responsive to the vector predicate and generates a predicate summary value based on the bit values ​​of the vector predicate. A first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit value of the vector predicate includes a set bit corresponding to a vector element at a higher index and an immediately following unset bit corresponding to a vector element at a lower index. A second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate. Thus, improved predicate-controlled vector processing is supported.

An instruction configured to perform data conversion is executed. The executing the instruction includes determining that an overflow condition exists in a change of a value, specified by the instruction, from one data format to another data format. It is determined that an overflow result control of the instruction is set to a selected value. A result of executing the instruction is provided. The providing the result includes placing a chosen default value in a result location based on determining that the overflow condition exists and that the overflow result control is set to the selected value.