52results about "Conditional code generation" patented technology

The invention relates to the technical field of data processing systems, and discloses a conference information intelligent data processing system based on multi-modal data fusion, and the system comprises a transaction template generation unit which calls a model from a preset rule base to generate a structured data container with an attribute field; the dual-channel feature extraction unit is used for distributing the voice to service data and a control instruction channel, extracting the service data to an independent cache region and monitoring a control keyword; the state control unit is used for unlocking the container only when the confirmation instruction is received, verifying data and writing a field to generate a transaction submission instruction; according to the system and the method, physical isolation of data flow and control flow is realized through a dual-channel architecture, a control instruction is used as a unique logic gating, non-decisive negotiation noise is filtered from the source, and atomicity and compliance of conversion from unstructured conference data to structured management transactions are ensured.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a set of graphics instructions. The apparatus may also determine whether each graphics instruction in the set of graphics instructions is associated with a resonance frequency that is above or below a threshold. Further, the apparatus may adjust an activity level for each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold.

The embodiment of the invention provides a control program generation method and device of equipment, the equipment and a medium. The method comprises the steps that a program generation request of a user for target equipment is received; the program generation request comprises equipment information of target equipment and a target control instruction of the target equipment; determining a use scene of the target equipment according to the equipment information of the target equipment; determining a dependency relationship of the target control instruction according to the use scene of the target equipment; the dependency relationship is a relationship between a target control instruction and at least one other control instruction required to be executed for realizing the target control instruction; and determining a target control program according to the dependency relationship of the target control instruction. According to the embodiment of the invention, the target control instruction of the user is combined with the equipment information and mapped to the specific equipment use scene, the control dependency relationship and the constraint condition are identified based on the use scene, the control program conforming to the actual working condition is generated, manual code writing is not needed, and the industrial control program development efficiency and scene adaptability are improved.

Provided in the present disclosure are a command processing circuit, a command processing method, and a PIM apparatus. The command processing circuit comprises: a PIM command identification module, which is electrically connected to a command address bus of a PIM apparatus and is configured to receive a command signal by means of the command address bus, determine the type of the currently received command signal, send, when it is determined that the currently received command signal is a conventional DRAM command, the command signal to a conventional command processing module, and send, when it is determined that the currently received command signal is a PIM-related command, the command signal to a PIM command processing module; the PIM command processing module, which is electrically connected to the PIM command identification module and is configured to receive the PIM-related command, decode the PIM-related command, and perform a corresponding operation on the basis of a decoding result; and the conventional command processing module, which is electrically connected to the PIM command identification module and is configured to receive the conventional DRAM command and decode the conventional DRAM command. The present disclosure is at least conducive to avoiding mode switching and improving system performance.

The embodiment of the invention discloses an excitation instruction generation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and aims to quickly generate an excitation instruction for an abnormal test and effectively reduce test case generation time. The method comprises the following steps: acquiring a standard instruction set and abnormal condition description information of the standard instruction set; wherein the standard instruction set comprises a standard instruction; the abnormal condition description information comprises an interrupt vector number and an interrupt error code; according to the abnormal condition description information, abnormal error injection codes are constructed for the standard instructions in the standard instruction set; and generating an excitation instruction for an abnormal test based on the standard instruction and the abnormal error injection code. The method is suitable for excitation instruction generation.

A processor is able to re-encode a normal value of a first floating point format to a normalized floating point format, and re-encode a subnormal value of the first floating point format to the normalized floating point format. A subset of the exponent bits of the exponent field of a normalized floating point format is used to encode a predetermined indication of being an exceptional value, wherein a combination of bit values used to encode this predetermined indication does not occur within a range of the exponent field of the normalized floating point format used to represent any possible non-exceptional, normal and subnormal values.

The invention discloses an instruction generation method and device, equipment, a storage medium and a program product, and relates to the technical field of machine learning. The method comprises the following steps: acquiring a first natural language instruction, wherein the first natural language instruction is used for indicating to realize a first function through computer equipment; obtaining a function vector set, wherein the function vector set comprises function feature vectors corresponding to a plurality of performance functions respectively; recalling at least one candidate performance function meeting a correlation degree requirement from a function vector set based on a vector correlation degree between a first feature vector corresponding to the first natural language instruction and a plurality of function feature vectors; based on the first natural language instruction and the at least one candidate performance function, an equipment driving instruction is constructed, and the content of the equipment driving instruction comprises a target performance function in the at least one candidate performance function and a first parameter of the target performance function when the first function is achieved, the first parameter is a function parameter obtained based on analysis of the first natural language instruction.

There is included a method and apparatus comprising computer code configured to cause a processor or processors to perform obtaining an input of at least one of a task and a workflow, setting a timeout for the input of the at least one of the task and the workflow, determining whether the at least one of the task and the workflow observes a lack of data of the input for a duration equal to the timeout, determining, in response to determining that the at least one of the task and the workflow observed the lack of data of the input for the duration equal to the timeout, an unavailability of further data of the input, applying an update to the at least one of the task and the workflow based on determining the unavailability, and processing the at least one of the task and the workflow.

The application provides an independent graphics card management method, an independent graphics card and an electronic device. The method comprises: a first programmable management module performing graphics card service management, comprising obtaining a command from a host memory through a host bus interface, interpreting the command into an instruction, and controlling a sub-engine in the independent graphics card to execute the instruction; and a second programmable management module performing graphics card system management, comprising managing power-on initialization, reset and working performance dynamic adjustment of the sub-engine in the independent graphics card, and managing power-on initialization of graphics card memory. The method simplifies hardware logic, the two management modules have clear division of labor, service management and system management are isolated, and the system is safer and more stable.

This disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. The method includes: responding to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the second prediction result differing from the first prediction result, using the second prediction result to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

Techniques are disclosed involving fusing instruction pairs and executing corresponding fused instruction operations. A processor includes fusion detection circuitry to detect a pair of fetched instructions and fuse the instructions into a fused instruction operation, and execution circuitry to execute the fused instruction operation. In one embodiment, a first instruction is executable to perform an operation and a second instruction is executable to adjust a sign of a result of the operation. In another embodiment, the first instruction is executable to perform an operation and the second instruction is executable to find a maximum or minimum, as compared to a comparison operand, of a result of the operation. In another embodiment, the first instruction is executable to perform a vector operation and the second instruction is executable to read a first element of the vector result and overwrite one or more additional elements of the vector result.

The application provides an instruction issuing method and device, electronic equipment and readable storage medium. The method comprises: constructing a track section graph and displaying based on track collection point data to be processed; in response to a selection interaction operation of a user on a section contained in the track section graph, determining a target section group indicated by the selection interaction operation, and determining an operation instruction corresponding to the selection interaction operation; and issuing the operation instruction to a target section contained in the target section group. Instead of determining the section to be controlled by manual input, the target section is selected and the operation instruction is selected by constructing the track section graph, displaying the track section graph to the user, and the user performing the selection interaction operation on the section in the track section graph. The user does not need to manually input, which reduces the complexity of determining the target section to a certain extent, and improves the efficiency of issuing the instruction to the target section.

The invention provides an 8Fs instruction receiving and IO control method in array server UART communication based on an FPGA, belongs to the technical field of array server hardware control, and is suitable for multi-node server cluster hardware management. According to the method, a purple light syncretic PGL50H-6FG484 FPGA is adopted as a main control unit, and a BMC sends a 0x8F single-byte 8Fs instruction through a UART (Universal Asynchronous Receiver / Transmitter); and after receiving the instruction, the FPGA analyzes the operation command through a frame header, an equipment address and additional data verification, matches 20 calculation modules, outputs an IO control signal, and simultaneously acquires the state of the module and returns the state to the BMC. The BMC is triggered to give an alarm through continuous three times of invalid instructions, and a flash enable signal and a power supply control signal are interlocked. According to the method, the UART control accuracy and reliability are improved, hardware resources are efficiently utilized, and the system security is enhanced.

The disclosure relates to a processor which can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floa

The disclosure relates to a processor which can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floating point format to a normalized narrower floating point format. According to the disclosure, when performing a wider-format sign injection operation on a NaN-boxed value of the normalized narrower floating point format held in a source register of a set of normalized-format registers, a bit manipulation is performed on a bit in the respective source register at a most-significant bit-position of the normalized wider floating point format. And when de-normalizing the NaN-boxed value of the normalized narrower floating point format from the respective source register, the bit at the most-significant bit-position of the normalized wider floating point format is ignored in detecting NaN-boxing.

The invention is in the field of computer technology. The invention describes an architecture of a safety automation system and a method for safely autonomously operating a technical device. The architecture solves the problem that every possible Byzantine error, whether caused by an accidental malfunction of hardware, a design error in software or an intrusion, must be identified and contained, so that no safety-relevant event occurs. The architecture consists of four largely independent subsystems, which are arranged hierarchically and each form an encapsulated fault containment unit. At the top of the hierarchy is the safety subsystem, i.e. the fault-tolerant decision subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are unsafe because they contain complex software. It is empirically difficult to find all design errors in a complex software system and to prevent intrusions. Due to redundancy and diversity, every error of the unsafe subsystems is masked so that no safety-critical malfunction occurs.

The invention relates to the field of battery management data processing, in particular to a battery management system of FTU (Feeder Terminal Unit) terminal equipment, which comprises a data acquisition module for acquiring battery management data, and a data preprocessing module for preprocessing the battery management data, the system constructs a fault feature recognition model through a model prediction module, a decision generation module generates a basic decision, and an instruction generation module performs on-off processing on an execution layer according to a configuration instruction. The aging condition of the battery is predicted, data comprehensiveness and battery data precision are still kept in a severe environment, interruption is not likely to happen in the face of strong interference, and therefore the management and monitoring precision of the battery state is improved.

A system and method for an improved global flag for synchronizing coprocessors. An exemplary processor system includes a plurality of coprocessors configured to compute processing tasks, each coprocessor connected to each remaining coprocessor via a plurality of connections, each connection from a coprocessor to a different coprocessor configured to be asserted or deasserted to indicate a status associated with a global flag of the plurality of global flags, the global flag being set based on the plurality of coprocessors asserting the global flag.

The invention belongs to the technical field of data interaction, and relates to a data interaction method, system and device based on an efficient data pool and a medium. The interaction method comprises the following steps: generating instruction queues to form an instruction pool according to software operation of each working mode task, generating a task instruction by an instruction producer when receiving task excitation, writing the task instruction into the instruction pool, and obtaining, analyzing and executing the task instruction from the pool by an instruction consumer; meanwhile, telemetering packets are generated according to the task related data volume to form a telemetering pool, and the telemetering packets are used for storing shared data. According to the scheme, by constructing the instruction pool and the telemetering pool, centralized management and efficient interaction of instructions and data are achieved, an instruction producer and a consumer are decoupled, the instructions can be written in, acquired and executed in order, and the efficiency and flexibility of data interaction are improved; the telemetering pool can store shared data, data sharing and access are facilitated, the processing capacity of the system for tasks in different working modes is enhanced, and the overall performance and stability of the system are improved.

The application discloses a BMC, comprising a plurality of virtual VGA controllers, each of which is used for connecting a server host; a plurality of display memories, each of which is connected with a virtual VGA controller; a configuration controller, which has a plurality of input ends and an output end, each of the input ends being connected with a virtual VGA controller; and a VGA controller, which is connected with the output end of the configuration controller. The application can be applied to the scene of managing a plurality of host hosts by using one BMC chip, and only one VGA controller is used in the scene.

A processor is enabled to execute instructions encoded according to compact register specifiers. A compact register specifier includes a register identification field, and a register offset field. The register identification field and the register offset field collectively specify two of the registers of the logical register address space using fewer resources of an instruction encoding (e.g., fewer bits) than two full length logical register specifiers. The register identification field is a full-length register specifier that enables, without any additional information, addressing any register of a logical register address space. The register offset is usable with additional information to address any register of the logical register address space. The additional information includes the register identification field and a function, such as an arithmetic function (e.g., addition) or a logical function (e.g., exclusive-OR).

The invention provides a database management method and device, equipment and a storage medium, and relates to the technical field of information. The method comprises the steps that a service processing request is obtained and responded to, a service processing instruction is generated, and a service requested by the service processing request is associated with data of a first database and data of a second database. The business processing instruction comprises a first instruction and / or a second instruction, the first instruction is used for requesting to call first data in a first database, and the second instruction is used for requesting to call second data in a second database. And processing the service processing request according to the service processing instruction.

Digit validation check control for instruction execution. A process receives an instruction to perform one or more operations using one or more input values. The instruction includes a "No Validation" indicator to check whether the digit validation check control is enabled for instruction execution. The process executes the instruction based on the "No Validation" indicator, including determining whether the digit validation check control is enabled for instruction execution and performing the processing based on this determination.Based on the "No Validation" indicator, which is set to a defined value, the "Digit Validation Check" control is activated, and the processing includes forcing a "Digit Validation Error" indicator, which is output by the execution to indicate "No Digit Validation Error" with respect to the at least one input value.

The application relates to an API controller-based instruction issuing method, which comprises the following steps: a client sends an HTTP request to an API controller, the request containing the address of a registered API and an input model; the API controller locates the corresponding API according to the API address, and distributes the API and the input model to a protocol adapter; the protocol adapter first calls a model checker, checks the input model according to a model checking scheme bound in the API, and distributes the input model to a model analysis executor; the model analysis executor analyzes the input model, assembles an instruction set or a message according to an instruction set scheme or a message scheme bound in the API, and issues the whole set of instruction set or message to a specific device or a proxy machine at a time to generate a response code; the model analysis executor calls a rollback executor to analyze the response code, returns corresponding issuing success information according to the analysis result, or extracts a rollback instruction set according to a rollback scheme bound in the API to perform corresponding rollback issuing operation.

The invention discloses a direction control state priority arbitration method and system, and relates to the technical field of automotive electronics, and the method comprises the steps: receiving an original key signal of a steering wheel and a state activation request of a vehicle-mounted execution end through a central decision-making unit, and dynamically establishing a direction control state context; arbitrating and determining a target function from the active request according to a preset state priority mapping table; and according to the logic conflict relationship between the target function and the current function mode, matching and executing strategy scripts of new starting and old closing, new starting and old closing, new waiting and old closing, new layer prohibition or new and old simultaneous execution, generating a final control instruction, and sending the final control instruction through a bus. And the system is also integrated with a hardware watchdog and a multiplexer, and is forcibly switched to a safe direct connection mode when the logic unit fails, so that the physical control authority of the core driving function is guaranteed. According to the invention, dynamic management and logic decoupling of the steering wheel control right are realized, resource conflicts during multi-function concurrence are effectively solved, and the driving safety is improved.

This invention provides a method, apparatus, electronic device, and storage medium for converting control programs. The method includes: storing instructions from a non-standard control program in a first global instruction list in line-by-line order; storing variables and their data types in a variable mapping table; inserting and deleting ladder identifiers in the first global instruction list according to the positions of the first operator and the serial block operator of the parallel loop to obtain a second global instruction list; inserting omitted instructions in the second global instruction list according to the operators of each instruction in the second global instruction list to obtain a third global instruction list; and determining a standard control program based on the third global instruction list and the variable mapping table. This invention enables the conversion of non-standard control programs into standard control programs.

This invention relates to the field of CPU technology, specifically to a method and system for implementing L2 early wake-up of L1, comprising the following steps: allocating a load miss request to the CRQ, and having the load miss request participate in and win arbitration to be added to the pipeline; determining the specific situation of hit L2 or miss L2 in the pipeline, and generating a relevant allocation scheme; updating the L2 tag_ram data_ram and returning the data to the core; finally, dealing with the entry item corresponding to the outstanding request queue and ending the process. This invention allows L2 to wake up the LSU to the pipeline earlier. When a load instruction needs data in the pipeline, L2 has already sent the data to the LSU, meaning the load instruction can obtain the data when it needs it. This allows the load instruction to be added to the pipeline 4 cycles earlier, thereby effectively improving the overall performance of the CPU.

The application relates to a radio frequency parameter updating system which comprises a server, a host and terminals, the server, the host and the terminals being in communication connection; the host comprises a transmission control module, a backup restoration module and a process control module, the transmission control module, the backup restoration module and the process control module being in communication connection; the process control module is used for receiving an updating instruction, and the updating instruction is used for updating target radio frequency parameters of target terminals; the target terminals are at least one of the terminals; the process control module is used for generating a plurality of control instructions in response to the updating instruction, and controlling the transmission control module and the backup restoration module to update the target radio frequency parameters of the target terminals through the plurality of control instructions, so as to obtain a target encrypted file system. In the system, the process control module on the host generates a plurality of control instructions in response to the updating instruction to control corresponding modules to update the target radio frequency parameters of the target terminals, so that automatic updating of the target radio frequency parameters of the target terminals is realized.

A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.