Processor executing SIMD instructions

Abstract

A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Description

[0001] This application is a divisional of application Ser. No. 10 / 668,358, filed Sep. 24, 2003.BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The present invention relates to a processor such as a DSP and a CPU, and more particularly to a processor suitable for performing signal processing for sounds, images and others. [0004] (2) Description of the Related Art [0005] With the development in multimedia technologies, processors are increasingly required to be capable of high-speed media processing represented by sound and image signal processing. As existing processors responding to such requirement, there exist Pentium (R) / Pentium (R) III / Pentium 4 (R) MMX / SSE / SSE2 and others produced by the Intel Corporation of the United States supporting SIMD (Single Instruction Multiple Data) instructions. Of them, MMX, for example, is capable of performing the same operations in one instruction on a maximum of eight integers stored in a 64-bit MMX register. [0006] However...

AI Technical Summary

Benefits of technology

[0009] As is obvious from the above explanation, the processor according to the present invention is capable of executing a characteristic SIMD instruction for judging whether or not results of operations performed under a SIMD compare instruction are all zero and setting such results to condition flags. This allows a faster extraction of results of SIMD compare instructions (especially, agreement / disagreement of results), as well as a faster comparison processing to be performed on more than one pixel value as a processing unit and a faster detection of the EOF (End Of File) of a file.

[0023] As described above, the processor according to the present invention is capable of performing sophisticated SIMD operations and a wide range of digital signal processing required for multimedia processing at a high speed, and is capable of being employed as a core processor to be commonly used in mobile phone, mobile AV device, digital television, DVD and other devices, the processor according to the present invention is extremely useful in the present age in which the advent of high-performance and cost effective multimedia apparatuses is desired.

Problems solved by technology

However, there is a problem that such existing processors do not fully satisfy a wide range of requirements concerning media processing.

For example, although capable of operating on multiple data elements in a single instruction and comparing multiple data elements in a single instruction, the existing processors cannot evaluate the results of such comparisons in a single instruction.

However, it cannot make a judgment on whether all values of these four flags are zero or not in one instruction.

This requires a plurality of instructions for evaluating results every time a comparison is made against another set of pixel values when four pixel values are used as a unit of comparison, resulting in an increased number of instructions and therefore a decreased speed of image processing.

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