70results about "Computation using denominational number representation" patented technology

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention relates to the field of optical computing, and provides a signal processing method and device based on an optical computing chip and a photoelectric fusion computing system.The signal processing device comprises an optical input modulation module, a first weight mapping module, a second weight mapping module and an optical output combining module, and the optical input modulation module converts an input signal into a modulated optical signal; the first weight mapping module obtains a first output optical signal based on the first weight; the second weight mapping module acquires a second output optical signal based on a second weight; the optical output combining module obtains a comprehensive output signal based on the first output optical signal and the second output optical signal; the second weight mapping module comprises a light dimension reduction unit, a low-dimensional light modulation unit and a light dimension raising unit, and the light dimension reduction unit performs low-dimensional projection on a modulated light signal; the low-dimensional optical modulation unit adjusts the second weight based on the second weight update signal and obtains an optical signal after low-dimensional processing; and the light dimension raising unit carries out high-dimensional projection on the light signal after low-dimensional processing.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

The decimal quantization logic gate is a hardware logic operation design based on quantization logic, and the main design idea of the decimal quantization logic gate is that a linear multi-valued logic operation is used as a logic operation part to execute logic operations such as AND (small), OR (large) and NOT (complement); the multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like, and a multi-valued logic operation and multi-valued quantization'quantization logic 'circuit is formed by combining the structures of multi-valued quantization and logic operation together, and a multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like. The logic circuit always executes'quantization 'and'logic operation', so that the logic circuit is called'quantization logic '. The design of all previous'multi-valued logic gate 'and'two-valued logic gate' circuits is as follows: 'logical operation '(AND, OR, NOT) is firstly carried out, and then'quantization' (threshold detection) is carried out to set'fault-tolerant intervals'. Therefore, the quantization logic is the most original thought of logic hardware design.

We propose a hybrid wave-based logic model for optical computing that integrates both Total Wave Modified Schrödinger Equation (TWMSE) formulations and non-TWMSE interference field logic. This system enables deterministic collapse behavior through physical wave interactions, rather than relying on conventional transistor logic or probabilistic quantum models. In the TWMSE regime, collapse thresholds are governed by field interference between signal and control waves, allowing dynamic selection of tasks based on intensity and phase alignment. In the generalized non-TWMSE regime, similar collapse-like logic can be achieved using thresholded interference models that are classically engineered for optical domain systems. Together, these formulations enable adaptive task selection, nonlinear logic gating, and scalable parallel processing in optical chips. Our architecture supports real-time wavefield decisions and is compatible with standard photonic components such as interferometers, microring resonators, variable attenuators, and optical threshold comparators. The result is a unified logic framework for next-generation AI hardware that harnesses both quantum-inspired and classical wave interference dynamics.

A superconducting circuit and a quantum computer capable of implementing four-body interaction using a plurality of superconducting qubit circuits supplied with signals of the same frequency are provided. A superconducting circuit (1) includes four superconducting qubit circuits (10), a coupling circuit (20) directly connected to the four superconducting qubit circuits (10). Each of the superconducting qubit circuits (10) indicates a qubit by being in a first phase state or a second phase state, when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an even number, an interaction term of Hamiltonian of the superconducting circuit (1) takes a first value, and when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an odd number, the interaction term takes a second value.

A method for performing computations in a system having a matrix multiplication unit that converts an optical input vector to an analog output vector based on a plurality of weight control signals, the method comprising: receiving a computation request comprising at least one digital input vector and a first plurality of weights; storing the digital input vector and the first plurality of weights in a storage unit; generating a first plurality of modulator control signals based on the digital input vector, generating a first plurality of weight control signals based on the first plurality of weights; generating an optical input vector based on the first plurality of modulator control signals; obtaining a first plurality of digital outputs corresponding to the analog output vector, the first plurality of digital outputs forming a first digital output vector; performing, by the controller, a non-linear conversion on the first digital output vector to produce a first converted digital output vector; storing the first converted digital output vector in a storage unit; an output generated based on the first converted digital output vector is output by the controller.

The superconducting circuit includes a first port and a plurality of second ports, a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter coupling two consecutive filter poles to each other. When operating as a demultiplexer, the plurality of filter poles and associated admittance inverters define a plurality of current branches such that an input current input through the first port is routed to a selected one of the plurality of second ports by application of a first set of magnetic flux biases.

This enables the creation of an ion trap chip with high photon collection efficiency. [Solution] The ion trap chip (1) comprises an electrode substrate (10) that holds ions (I) which become qubits in space, a first optical circuit board (300) having a first optical waveguide (110), and a light-receiving unit (120) that receives photons emitted from the ions and introduces the photons into the first optical waveguide, with the light-receiving unit facing the electrode substrate with the ions in between.

The invention discloses a storage and calculation integrated photon calculation system and method based on a phase change metasurface and holographic light field modulation, and aims to solve the problems that storage and calculation are separated, the dynamic modulation speed is low and the precision is limited in an existing photon calculation framework. The invention provides a hybrid computing architecture which takes a blue-ray disc or a phase change storage wafer as a high-density holographic weight storage medium and is combined with a high-speed spatial light modulator and a photoelectric nonlinear activation circuit. Through an area array parallel reading mechanism, a large-scale weight matrix is read at one time by using beam-expanded coherent light, light velocity matrix multiplication is completed, and interlayer fast switching of the deep neural network is realized in combination with a streaming rotation or light beam scanning technology. According to the invention, the non-volatility and multistage refractive index characteristics of the phase change material are utilized to realize high-density on-chip storage and zero-power-consumption lossless reading of large model weight, and the problems of a video memory wall and an energy consumption wall in large model reasoning are effectively solved.

To provide a processing system, a processing method, and a program for accurately adjusting a resonance frequency in a quantum bit device.SOLUTION: The processing system 1 includes a calculation means 701 that calculates a first current value, which is a current value of a current flowing through a resonance circuit, based on a value of a residual magnetic flux in the resonance circuit included in a quantum bit device.SELECTED DRAWING: Figure 9

A quantum device includes a silicon layer in which a plurality of quantum dots 201 can be induced, a first gate of a first inductive quantum dot and a second gate of a second inductive quantum dot that control an electrical potential defining the induced quantum dots 201, and a first integrated circuit element and a second integrated circuit element 204 that control voltages of the first gate and the second gate. The integrated circuit element 204 has an adjustable non-volatile resistance value. The integrated circuit element 204 has an input voltage V in and first and second output voltages V out . The output voltages depend on the input voltage, the first non-volatile resistance value, and the second non-volatile resistance value. The integrated circuit element 204 is electrically connected to the gates such that the output voltages are applied to respective gates of the inductive quantum dots 201.

The present disclosure relates to a TWPA device (1) for a quantum computer, which has a two-band dispersion relation and is configured to perform three-wave mixing. The TWPA device (1) comprises a chain of unit cells (φ), each comprising a non-linear inductance element (5) and a capacitor (6) connected to its ground (7). The unit cell (φ) further comprises a resonator circuit (8) and one of the periodically modulated input parameters. The two-band dispersion relation is composed of a lower frequency band and a higher frequency band, sandwiching a frequency gap. Further, the TWPA device (1) is configured to receive an amplified signal and a pump signal at the input (2). The pump signal is in the higher frequency band described above and has a frequency that is at least 2 / 3 of the cut-off frequency of the TWPA device (1) described above, or the pump signal described above is in the lower frequency band described above and its second harmonic has a frequency within the frequency gap described above.

The present disclosure provides embodiments for entangling two or more trapped ions. To this end, a common motional mode of two or more trapped ions is used by conditionally exciting and / or de-exciting the common motional mode depending on the internal states of the two or more trapped ions. The common motional mode is conditionally excited / de-excited by inducing, on each of the two or more trapped ions, a respective perpendicular state-dependent force (SDF) that is modulated depending on the frequency of the motional mode. More specifically, each perpendicular SDF is induced by a laser beam and acts perpendicular to the propagation direction of the laser beam inducing the perpendicular SDF. The SDF may be modulated by (i) modulating the intensity and / or amplitude of the electromagnetic field of a first laser beam, (ii) changing the position and / or direction of the first laser beam relative to the first trapped ion, and / or (iii) including light of a different frequency in the laser beam.

The present invention generally relates to the field of quantum computing, and in particular to a quantum processing unit comprising at least one superconducting qubit based on phase-biased linear and nonlinear inductive energy elements. The superconducting phase difference between the linear inductive energy element and the nonlinear inductive energy element is biased, for example, by an external magnetic field, so that the quadratic potential energy terms of the linear and nonlinear inductive energy elements are at least partially cancelled. In a preferred embodiment, such cancellation is at least 30%. By doing so, it is possible to implement the design of a superconducting qubit with high coherence and high anharmonicity.

The application provides an optical computing device, method, equipment and storage medium. The device comprises a processor configured to obtain a target vector and a target matrix to be subjected to multiplication calculation; the processor is further configured to decompose the target matrix to obtain at least one sub-matrix and a weight vector; a modulator configured to configure a phase difference of an optical computing unit in a corresponding optical computing array based on an element attribute of a matrix element in the sub-matrix; a laser configured to generate an optical signal; the modulator is further configured to configure a phase of the optical computing unit in the corresponding optical computing array based on an element attribute of a vector element in the target vector; an optical computing array configured to receive the optical signal and output a corresponding optical computing result; and the processor is further configured to perform weighted calculation on the optical computing result based on the weight vector to obtain a calculation result vector of the target vector and the target matrix. The application can reduce the complexity of the configuration of the optical computing unit and avoid information loss.

To provide a calculation device that can improve characteristics.SOLUTION: According to an embodiment, a calculation device includes an element part, a first conductive part, a second conductive part, a first coupling conductive part, and a control part. The element part includes a first structure, a second structure, and a first coupling structure. The first structure includes a first cavity resonator, a first another cavity resonator, and a first coupler. The second structure includes a second cavity resonator, a second another cavity resonator, and a second coupler. The first coupling structure can couple the first structure and the second structure to each other. The control part can supply a first AC signal including an AC component to the first conductive part. The control part can supply a second AC signal including an AC component to the second conductive part. The control part can supply a first DC pulse signal to the first coupling conductive part.SELECTED DRAWING: Figure 1

In a quantum bit device having a coupling line for forming capacitive coupling between quantum bits, leakage of a control signal to the coupling line is suppressed. [Solution] The quantum bit device includes a first quantum bit substrate having a first quantum bit, a second quantum bit, and a ground electrode extending between the first quantum bit and the second quantum bit, and a connection substrate having a first coupling line that forms capacitive coupling between the first quantum bit and the second quantum bit.

The disclosure relates to a processor which can re-encode from an unnormalized wider floating point format to a normalized wider floating point format, and re-encode from an unnormalized narrower floating point format to a normalized narrower floating point format. According to the disclosure, when performing a wider-format sign injection operation on a NaN-boxed value of the normalized narrower floating point format held in a source register of a set of normalized-format registers, a bit manipulation is performed on a bit in the respective source register at a most-significant bit-position of the normalized wider floating point format. And when de-normalizing the NaN-boxed value of the normalized narrower floating point format from the respective source register, the bit at the most-significant bit-position of the normalized wider floating point format is ignored in detecting NaN-boxing.

By adding technical innovations to the coupling lines formed between one quantum bit and multiple other adjacent quantum bits, the efficiency of extracting the electromagnetic field from the quantum bit can be improved while suppressing crosstalk. The quantum bit device includes a quantum bit substrate having a first quantum bit and a second quantum bit, a connection substrate disposed opposite the quantum bit substrate, and a coupling line including a first wiring and a second wiring that form a differential pair and form capacitive coupling between the first quantum bit and the second quantum bit, wherein at least one of the first wiring and the second wiring is disposed on the connection substrate.

The invention discloses a method and system for accelerating construction of a constellation model and a storage medium. The method comprises the following steps: decomposing an algorithm for constructing a constellation model into an algorithm serial part and an algorithm parallel part according to a preset decomposition mode; coding modification suitable for the CPU process is carried out on the serial part of the algorithm, and parallel coding modification suitable for the AI accelerator process is carried out on the parallel part of the algorithm. And merging and reconstructing the transformed algorithm serial part and algorithm parallel part, and executing the merged and reconstructed algorithm for constructing the constellation model by using an on-board computer carrying an AI accelerator. According to the method, the AI accelerator is used for parallel computing, the constellation model construction algorithm is optimized in parallel, and the number of serial cycles of a CPU is reduced, so that the problem of low operation efficiency of the model construction algorithm is solved, and the acceleration effect is achieved.

To reduce computation time of quantum calculation.SOLUTION: An information processing device 10, when a quantum gate working for an encoded logic quantum bit is a rotary gate 2, sets a target rotation angle set in the rotary gate 2 as a designation rotation angle. The information processing device 10 generates a first logic quantum bit 4 having a predetermined accessory state, on the basis of the designation rotation angle. The information processing device 10 sets the first logic quantum bit 4, and the second logic quantum bit 5 working the rotary gate 2 as input, and executes probabilistic rotational operation of forward rotation of the designation rotation angle or reverse rotation having a sign opposite that of the designation rotation angle. Then, the information processing device 10, until the rotational operation becomes the forward rotation, while updating the designation rotation angle on the basis of the target rotation angle, repeats processing which generates the first logic quantum bit 4 and the processing which executes the rotational operation.SELECTED DRAWING: Figure 1

Various embodiments provide a method, apparatus, system, or computer program product for performing detection of loss of a quantum object. The method, performed by a controller of a quantum computer, includes controlling one or more voltage sources to cause a quantum object confinement device to confine a crystal of a quantum object, the crystal of the quantum object (i) including at least one of (a) a first species quantum object or (b) a second species quantum object and (ii) defining a crystal axis aligned along an RF null axis of the quantum object confinement device; causing at least one control electrode of a plurality of control electrodes to provide at least one first control signal, the at least one first control signal causing the at least one control electrode to generate a pushing field configured to rotate the crystal axis of the quantum object relative to the RF null axis.

To accelerate the transition time of a current supplied to a quantum bit.SOLUTION: A quantum bit array chip comprises: a semiconductor layer; an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes which are disposed on the insulating layer and which apply voltage to trap electrons having a predetermined spin state in the semiconductor layer; a plurality of second gate electrodes which are adjacent to the first gate electrodes and alternately disposed with the first gate electrodes in order to allow a current for forming a magnetic field that acts on an electron to flow in an extension direction of the first gate electrodes when the spin state of the electron is changed; and a third gate electrode having substantially the same resistance as the second gate electrodes. If the spin state of the electron trapped by the first gate electrode is changed, the quantum bit array chip controls to allow a current to flow to the third gate electrode, and after the current has stabilized, to stop the current to the third gate electrode, and allow a current to flow to the second gate electrode.SELECTED DRAWING: Figure 8A

A system and method are provided for generating entangled photon pairs containing two photons having different wavelengths. The technique involves pumping an atomic vapor of an alkali species using a pump laser and a coupled laser configured to drive a spontaneous four-wave mixing process within the atomic vapor. The pump laser and the coupled laser are detuned with respect to atomic transitions of the alkali species, thereby increasing the brightness of the entangled photon pair source.

A quantum gate device 1 comprises: a quantum bit substrate unit 10 on which at least two data quantum bits, that is, a first data quantum bit 11 and a second data quantum bit 12, and a coupler quantum bit 13 disposed between the first data quantum bit 11 and the second data quantum bit 12 are mounted; and a drive microwave irradiation unit 20 which irradiates the coupler quantum bit 13 with a drive microwave that causes fg-ge transitions between the first data quantum bit 11 and the coupler quantum bit 13. Each of the first data quantum bit 11, the second data quantum bit 12, and the coupler quantum bit 13 has a ground state, a first excited state with higher energy than the ground state, and a second excited state with higher energy than the first excited state. The transition frequency of fg-ge transitions between the first data quantum bit 11 and the coupler quantum bit 13 obtained when the second data quantum bit 12 is in the ground state is defined as ωfgge g. The transition frequency of fg-ge transitions between the first data quantum bit 11 and the coupler quantum bit 13 obtained when the second data quantum bit 12 is in the first excited state is defined as ωfgge e. The frequency ωd of the drive microwave takes a value between ωfgge e and ωfgge g.