185results about "Computation using denominational number representation" patented technology

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The invention discloses an optical computing system, a data processing method, a product, equipment and a medium, and relates to the technical field of optical computation.The method comprises the steps that two input and output modules and an optical computing module are arranged, a parameter matrix in the optical computing module is updated according to a to-be-processed feature matrix, and in each iteration, the parameter matrix of the optical computing module is updated; the optical signal modulated by the first input and output module is positively input to the optical calculation module and calculated with the parameter matrix, and the optical signal modulated by the second input and output module is reversely input to the optical calculation module and calculated with a transpose matrix of the parameter matrix, so that an output vector of current iteration is obtained; the key feature information of the feature matrix is determined according to the output vector obtained by the last iteration at the end of iteration, so that the problems of high processing complexity and low processing efficiency caused by processing data through electric calculation are solved, efficient calculation of the parameter matrix and the transpose matrix is completed through optical calculation, the processing complexity is reduced, and the processing efficiency is improved. And the treatment efficiency is improved.

[Problem] To provide an information processing method which further minimizes quantum bit exponential measurement frequency. [Solution] One aspect of the present invention provides an information processing method. The information processing method is provided with the following steps. A conversion step converts an operator for n number of quantum bits into a unitary gate by using fewer than (n / 2) ancillary bits. The format of the unitary gate makes it possible to directly apply the operator. A circuit generation step involves generating a quantum circuit which functions as a time evolution operator when an ancillary bit is observed as a prescribed state, on the basis of the unitary gate.

A quantum bit array chip includes first gate electrodes that are arranged on an insulating layer and trap electrons in a predetermined spin state in a semiconductor layer by applying a voltage, second gate electrodes arranged alternately with the first gate electrodes to cause a current for forming a magnetic field acting on the electrons to flow in an extending direction of the first gate electrodes when the spin state of the electrons is changed, and a third gate electrode. The third gate electrode has the same resistance as the second gate electrodes, and when the spin state of electrons trapped in the first gate electrodes is changed, control is performed to cause a current to flow to the third gate electrode, and after the current is stabilized, stop the flowing of the current to the third gate electrode and cause a current to flow to the second gate electrodes.

The invention is directed to solving an optimization problem. The method operates a photonic crossbar array structure including N input lines and M output lines, which are interconnected at junctions via N×M photonic memory devices, where N≥2 and M≥2. The photonic memory devices are programmed to store respective weights in accordance with the optimization problem. The photonic crossbar array structure is operated as follows. First, the method determines values of L input vectors of N components each, where L≥2. Second, based on the determined values, N electromagnetic signals are generated, where each of the generated signals multiplexes L input signals encoded at respective wavelengths, so as for the N electromagnetic signals to map the L input vectors of N components each. Third, the N electromagnetic signals generated are applied to the N input lines of the photonic crossbar array structure.

According to the bit weight amplitude weight quantizer and the quantization discretization method, the maximum amplitude of input continuous simulation information is discretely divided into a plurality of amplitude paragraphs of a content interval GS, the amplitude paragraphs are associated with a carry system, the amplitude of the input continuous simulation information is discretely divided into a plurality of paragraphs through a number of carry systems, and the amplitude of the input continuous simulation information is divided into a plurality of paragraphs. If a decimal system exists, the amplitude of the continuous analog information is discretized into ten paragraphs, the discretized paragraphs are converted into thermometer coding information through a comparator, and then the thermometer coding information is converted into bit weight information through XOR and XNOR logical operation; the value of the bit weight in the bit weight information is generated by comparing the binary states 0 and 1 on the node, one state on the unique node is compared with different states on other nodes to indicate that the node has the weight, and the position number of the node with the weight is used for indicating the bit weight of all the nodes in the bracket.

The invention relates to the field of optical computing, and provides a signal processing method and device based on an optical computing chip and a photoelectric fusion computing system.The signal processing device comprises an optical input modulation module, a first weight mapping module, a second weight mapping module and an optical output combining module, and the optical input modulation module converts an input signal into a modulated optical signal; the first weight mapping module obtains a first output optical signal based on the first weight; the second weight mapping module acquires a second output optical signal based on a second weight; the optical output combining module obtains a comprehensive output signal based on the first output optical signal and the second output optical signal; the second weight mapping module comprises a light dimension reduction unit, a low-dimensional light modulation unit and a light dimension raising unit, and the light dimension reduction unit performs low-dimensional projection on a modulated light signal; the low-dimensional optical modulation unit adjusts the second weight based on the second weight update signal and obtains an optical signal after low-dimensional processing; and the light dimension raising unit carries out high-dimensional projection on the light signal after low-dimensional processing.

A method and system for data processing. The method comprises the following steps: converting input data into optical signals (S1); performing a matrix-vector multiplication on the input data carried by the optical signals and a weight matrix using a plurality of photonic multipliers, wherein the weight matrix determines the problem to be solved by the data processing (S2); and converting the optical signals resulting from the multiplication into output data (S3). The method can be applied to systems and algorithms for solving the problems of data clustering, labeling, classification, and semantic segmentation. Using photonic multipliers for the most time-and energy-consuming matrix-vector multiplications can greatly reduce both computation time and energy consumption, resulting in faster processing speeds and improved energy efficiency.

[0003] Devices and / or computer-implemented methods are provided for facilitating quantum gates between qubits using tunable couplers and capacitor devices. According to one embodiment, the quantum coupler device can include a tunable coupler coupled between like-polarity terminals of a first qubit and a second qubit, the tunable coupler configured to control a first coupling between the first qubit and the second qubit. The quantum coupler device can further include a capacitor device coupled to opposite-polarity terminals of the first qubit and the second qubit, the capacitor device configured to provide a second coupling that is opposite in sign to the first coupling.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

An optical arrangement for generating a plurality of conditioned optical signals is presented. The optical device (305) includes at least one temporally incoherent light source (310) coupled to a plurality of amplitude modulators (341, 342). Each amplitude regulator is configured to attenuate or amplify an optical signal derived from the at least one temporally incoherent light source (310) to provide a corresponding regulated optical signal. An optical computing system is also presented that includes an optical arrangement coupled to a processing device having a plurality of inputs for receiving conditioned optical signals.

A quantum entanglement generation device 10 comprises, when n is an integer of 2 or more, two superconducting quantum bit elements 20a and 20b each having three electrodes, a coupled resonator 30 disposed between the adjacent superconducting quantum bit elements 20a and 20b, and waveguides 50a and 50b capacitive-coupled to the superconducting quantum bit elements 20a and 20b, respectively. The coupled resonator 30 generates quantum entanglement between the adjacent superconducting quantum bit elements 20a and 20b by applying a two-qubit gate between the adjacent superconducting quantum bit elements 20a and 20b. The superconducting quantum bit elements 20a and 20b generate a two-dimensional cluster state by emitting the quantum entanglement as propagating microwave photons to the waveguides 50a and 50b.

The decimal quantization logic gate is a hardware logic operation design based on quantization logic, and the main design idea of the decimal quantization logic gate is that a linear multi-valued logic operation is used as a logic operation part to execute logic operations such as AND (small), OR (large) and NOT (complement); the multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like, and a multi-valued logic operation and multi-valued quantization'quantization logic 'circuit is formed by combining the structures of multi-valued quantization and logic operation together, and a multi-valued quantizer is used as a quantization part to execute multi-valued quantization of two values, three values, four values,... ten values, sixteen values,... fifty values, one hundred values and the like. The logic circuit always executes'quantization 'and'logic operation', so that the logic circuit is called'quantization logic '. The design of all previous'multi-valued logic gate 'and'two-valued logic gate' circuits is as follows: 'logical operation '(AND, OR, NOT) is firstly carried out, and then'quantization' (threshold detection) is carried out to set'fault-tolerant intervals'. Therefore, the quantization logic is the most original thought of logic hardware design.

The invention relates to the field of computing devices. A pipelined multiplier comprises an intermediate value generator configured to be capable of receiving first and second operands and generating intermediate multiplication results, a Wallace tree-type triple-layer pipeline for the convolution of the intermediate values, and a multiplexer for selecting a multiplication or combined multiplication and addition operation with a third operand. The units are configured so that each subsequent unit operates on the inverse edge of a clock signal in relation to the preceding unit. The intermediate value generator is based on a Booth algorithm which generates all the intermediate values in parallel in a half-cycle. The technical result of the invention is an increase in the speed of the device.

The invention relates to a processor comprising: an integer processing unit (ALU), a floating-point processing unit (FPU), a register bank (RGBK), an external data bus (DTB), a data path connecting the register bank to the floating-point processing unit, the integer processing unit, and the external data bus, and a processing chain configured to process at least partially simultaneous integer and floating-point instructions, the processing chain comprising common stages for processing an integer and a floating-point instruction, and at least one additional execution stage for executing a floating-point operation. Figure 1

We propose a hybrid wave-based logic model for optical computing that integrates both Total Wave Modified Schrödinger Equation (TWMSE) formulations and non-TWMSE interference field logic. This system enables deterministic collapse behavior through physical wave interactions, rather than relying on conventional transistor logic or probabilistic quantum models. In the TWMSE regime, collapse thresholds are governed by field interference between signal and control waves, allowing dynamic selection of tasks based on intensity and phase alignment. In the generalized non-TWMSE regime, similar collapse-like logic can be achieved using thresholded interference models that are classically engineered for optical domain systems. Together, these formulations enable adaptive task selection, nonlinear logic gating, and scalable parallel processing in optical chips. Our architecture supports real-time wavefield decisions and is compatible with standard photonic components such as interferometers, microring resonators, variable attenuators, and optical threshold comparators. The result is a unified logic framework for next-generation AI hardware that harnesses both quantum-inspired and classical wave interference dynamics.

A superconducting circuit and a quantum computer capable of implementing four-body interaction using a plurality of superconducting qubit circuits supplied with signals of the same frequency are provided. A superconducting circuit (1) includes four superconducting qubit circuits (10), a coupling circuit (20) directly connected to the four superconducting qubit circuits (10). Each of the superconducting qubit circuits (10) indicates a qubit by being in a first phase state or a second phase state, when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an even number, an interaction term of Hamiltonian of the superconducting circuit (1) takes a first value, and when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an odd number, the interaction term takes a second value.

A method for performing computations in a system having a matrix multiplication unit that converts an optical input vector to an analog output vector based on a plurality of weight control signals, the method comprising: receiving a computation request comprising at least one digital input vector and a first plurality of weights; storing the digital input vector and the first plurality of weights in a storage unit; generating a first plurality of modulator control signals based on the digital input vector, generating a first plurality of weight control signals based on the first plurality of weights; generating an optical input vector based on the first plurality of modulator control signals; obtaining a first plurality of digital outputs corresponding to the analog output vector, the first plurality of digital outputs forming a first digital output vector; performing, by the controller, a non-linear conversion on the first digital output vector to produce a first converted digital output vector; storing the first converted digital output vector in a storage unit; an output generated based on the first converted digital output vector is output by the controller.

Systems and methods are provided for performing fault-tolerant quantum operations for a four-leg Cat code. The quantum system includes an ancilla qubit dispersively coupled to a first logical qubit, and the quantum system may be manipulated at least in part by: generating and applying a first drive waveform to the ancilla qubit, where the first drive waveform includes a first comb of 7t pulses having selective frequencies corresponding to a first selection of even and odd cavity resonant frequencies of the first logical qubit; and reading out the state of the ancilla qubit.

To achieve data communication via wiring with low power consumption in a semiconductor device.SOLUTION: A second control device includes a signal modulation section that changes the impedance of a path by selecting one of two control values, and a first control device includes a signal demodulation section that reproduces a data value from the impedance of the path.SELECTED DRAWING: Figure 1

Various embodiments of the present disclosure are directed to a photonic circuit for a vector-matrix operation. A source pixel is configured to generate a light beam. An optical fan-out structure is configured to generate a plurality of copies of the light beam. A plurality of modulator pixels are configured to respectively transmit the plurality of copies with individual transmissivities to generate a plurality of transmitted light beams. A plurality of detector pixels are configured to accumulate charge respectively in response to the plurality of transmitted light beams. A controller is configured to control the source pixel and the plurality of modulator pixels to modulate an intensity of the light beam and the individual transmissivities to perform the vector-matrix multiplication operation. The intensity is modulated to temporally encode an input row vector, and the individual transmissivities are modulated to temporally encode corresponding column vectors of a weight matrix.

Various embodiments of the present disclosure relate to a photonic circuit for vector matrix operation. The source pixel is configured to generate a light beam. The optical fan-out structure is configured to produce a plurality of copies of the light beam. A plurality of modulator pixels are configured to transmit the plurality of replicas at individual transmittances, respectively, to produce a plurality of transmitted beams. A plurality of detector pixels are configured to accumulate charge in response to the plurality of transmitted light beams, respectively. A controller is configured to control the source pixel and the plurality of modulator pixels to modulate the intensity of the light beam and the individual transmittances to perform a vector matrix multiplication operation. The intensities are modulated to temporally encode input row vectors, and the individual transmittances are modulated to temporally encode corresponding column vectors of a weight matrix. The embodiment of the invention also provides a method for executing a multiply-accumulate-add (MAC) operation.

The present application relates to an optimization device, an optimization program, and an optimization method. The optimization device includes a solving unit. The solving unit is configured to: among a plurality of bits for solving a plurality of combinatorial optimization problems, assign a plurality of first bits to a first combinatorial optimization problem included in the plurality of combinatorial optimization problems, and assign a plurality of second bits to a second combinatorial optimization problem included in the plurality of combinatorial optimization problems. The solving unit is further configured to set an interaction between each of the plurality of first bits and each of the plurality of second bits to zero, and solve the plurality of combinatorial optimization problems.

A system for scalable, fault-tolerant optical quantum computing includes multiple optical circuits, multiple photon-number-resolving detectors (PNRs), a multiplexer, and an integrated circuit (IC). In operation, the optical circuits generate output states by Gaussian boson sampling (GBS), and the PNRs generate qubit clusters based on the output states. The multiplexer multiplexes the qubit clusters and replaces empty modes with squeezed vacuum states to generate multiple hybrid resource states. The IC stitches the hybrid resource states into a high-dimensional cluster state containing states for fault-tolerant quantum computing.

The superconducting circuit includes a first port and a plurality of second ports, a plurality of filter poles, each filter pole including an inductor and a capacitor connected in parallel between the first port and a second port of the plurality of second ports, and an admittance inverter including at least one of a coupling capacitor, a coupling inductor, and a Josephson junction, the admittance inverter coupling two consecutive filter poles to each other. When operating as a demultiplexer, the plurality of filter poles and associated admittance inverters define a plurality of current branches such that an input current input through the first port is routed to a selected one of the plurality of second ports by application of a first set of magnetic flux biases.

1. A method of performing a computation using an ion trap quantum computing system comprising a classical computer, a system controller, and a quantum processor, the method comprising: computing, by the classical computer, a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the computed circuit on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; and outputting, by the classical computer, the population of qubit states measured in the quantum processor.

A method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The method may further include adjusting the plurality of device parameters at least in part by determining whether the plurality of MZMs have ground state degeneracy. If it is determined that the plurality of MZMs do not exhibit ground state degeneracy, altering the plurality of device parameters may further include altering one or more device parameters of the plurality of device parameters. If it is determined that the plurality of MZMs exhibit ground state degeneracy, the method may further include altering one or more parameters of a measurement device coupled to the qubit architecture.

This enables the creation of an ion trap chip with high photon collection efficiency. [Solution] The ion trap chip (1) comprises an electrode substrate (10) that holds ions (I) which become qubits in space, a first optical circuit board (300) having a first optical waveguide (110), and a light-receiving unit (120) that receives photons emitted from the ions and introduces the photons into the first optical waveguide, with the light-receiving unit facing the electrode substrate with the ions in between.