87 results about "Code cache" patented technology

A method is shown for selecting active, or hot, code traces in an executing program for storage in a code cache. A trace is a sequence of dynamic instructions characterized by a start address and a branch history which allows the trace to be dynamically disassembled. Each trace is terminated by execution of a trace terminating condition which is a backward taken branch, an indirect branch, or a branch whose execution causes the branch history for the trace to reach a predetermined limit. As each trace is generated by the executing program, it is loaded into a buffer for processing. When the buffer is full, a counter corresponding to the start address of each trace is incremented. When the count for a start address exceeds a threshold, then the start address is marked as being hot. Each hot trace is then checked to see if the next trace in the buffer shares the same start address, in which case the hot trace is cyclic. If the start address of the next trace is not the same as the hot trace, then the traces in the buffer are checked to see they form a larger cycle of execution. If the traces subsequent to the hot trace are not hot themselves and are followed by a trace having the same start address as the hot trace, then their branch histories are companded with the branch history of the hot trace to form a cyclic trace. The cyclic traces are then disassembled and the instructions executed in the trace are stored in a code cache.

Hijacking of an application is prevented by monitoring control flow transfers during program execution in order to enforce a security policy. At least three basic techniques are used. The first technique, Restricted Code Origins (RCO), can restrict execution privileges on the basis of the origins of instruction executed. This distinction can ensure that malicious code masquerading as data is never executed, thwarting a large class of security attacks. The second technique, Restricted Control Transfers (RCT), can restrict control transfers based on instruction type, source, and target. The third technique, Un-Circumventable Sandboxing (UCS), guarantees that sandboxing checks around any program operation will never be bypassed.

A runtime system using thread-shared code caches is provided which avoids brute-force all-thread-suspension and monolithic global locks. In one embodiment, medium-grained runtime system synchronization reduces lock contention. The system includes trace building that combines efficient private construction with shared results, in-cache lock-free lookup table access in the presence of entry invalidations, and a delayed deletion algorithm based on timestamps and reference counts. These enable reductions in memory usage and performance overhead.

Subject program code is translated to target code in basic block units at run-time in a process wherein translation of basic blocks is interleaved with execution of those translations. A shared code cache mechanism is added to persistently store subject code translations, such that a translator may reuse translations that were generated and / or optimized by earlier translator instances.

A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide efficient and comprehensive manipulation of an application running on an operating system and hardware. The code cache includes a system for automatically keeping the code cache at an appropriate size for the current working set of an application running.

A system and method for dynamically patching code. In one embodiment, a method includes intercepting original program instructions during execution of the program using a software interface, determining whether associated instructions have been cached in a code cache of the software interface and, if so, executing the cached instructions from the code cache, if associated instructions have not been cached, determining if the original program instructions require unavailable hardware functionality, and dynamically replacing the original program instructions with replacement instructions that do not require unavailable hardware functionality if it is determined that the original program instructions require unavailable hardware functionality, the dynamic replacing including fetching replacing instructions, storing the replacement instructions in the code cache, and executing the replacement instructions from the code cache.

Techniques for increasing the performance of virtual machines are disclosed. It can be determined whether a program instruction which is to be executed by the virtual machine is a branch instruction, and whether a basic block of code is present in a code cache. If so, the basic block of code can be executed. The basic block includes code that can be executed for the program instruction. A cache can be used to store the basic block for program instructions that are executed by the virtual machine. The program instruction may be a bytecode and the code cache can be implemented as a native code cache.

A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

The invention discloses a multi-core and multi-thread construction method for a heat path in a dynamic binary translator. The method comprises the following steps: a basic block translation and object code execution part works as a main thread, and a heat path construction and super block translation part works as a sub-thread; an independent code cache structure in a dynamic binary translator for adaption adopts a design mode of dual code cache, the cache of two codes is under unified management of a hash table function, so that the main thread and the sub-thread can be conducted in parallel in the process of data inquiry and data renewal; and the main thread and the sub-thread are appointed to work on different cores of a multi-core processor combined with hard affinity, and a continuous segment of memory space and two counters are utilized to stimulate a segment of queue, so as to carry out the communication between the threads in machine language level and high-level language level. The invention has the favorable characteristics of high parallelism and low synchronous consumption, and provides new conception and new frame for the optimization work of dynamic binary translators in the future.

A runtime system using thread-shared code caches is provided which avoids brute-force all-thread-suspension and monolithic global locks. In one embodiment, medium-grained runtime system synchronization reduces lock contention. The system includes trace building that combines efficient private construction with shared results, in-cache lock-free lookup table access in the presence of entry invalidations, and a delayed deletion algorithm based on timestamps and reference counts. These enable reductions in memory usage and performance overhead.

The invention relates to a platform virtualization system comprising a CPU simulator, a memory virtualization module, and an external virtualization module. The CPU simulator reads an X86 architecture code instruction and judges whether an instruction basic block is translated or not; a binary translator is used for translation and comprises a translation engine and an execution engine; the translation engine translates an X86 architecture code into a Loongson platform code; the execution engine prepares the operational context of the Loongson platform code, locates the Loongson platform code corresponding to the X86 architecture code from a Loongson platform code cache and executes the code. The memory virtualization module uses a shadow page-table method. The external virtualization module establishes a corresponding device model for each external device. An X86 architecture virtual machine interacts with the external devices through the device models, thereby discovering and accessing the devices. The platform virtualization system allows information systems not matching with the domestic Loongson hardware platform yet to run in the domestic software-hardware environments in a virtualized manner, and contributions are made for the smooth transition between new and old technical systems in the automatic upgrading process of the information systems.

A subfield (SF) coding circuit including an SF coding cache memory, a look-up table (LUT) memory, and an SF coding control unit. The coding control unit reads setting gradation values and SF coding data from the coding cache memory for writing to the LUT memory SF by SF. The control unit accesses the LUT memory by using the gradation value of an image signal from a frame memory control unit as an address, and outputs the SF coding data corresponding to the gradation value of the image signal input to the LUT memory to a serial-to-parallel conversion unit.

The present invention provides a translation cache management method based on code popularity in dynamic binary translation. The method includes the steps of: dividing the entire translation cache into two levels of cache; when there is a new basic block to be translated, according to the basic block Find the code block in the hot code cache according to the address; look up the code block in the sub-code cache according to the address of the basic block; calculate the space required for caching the code block; clear the sub-code cache; translate the basic block, and store the translated code block into the sub-code cache; execute the code block; count the number of executions of the code block, if the number of executions is greater than the threshold, the code block is cached into The hot code cache; adding the basic block into the slow hash table, and adding the result into the fast hash table.

The invention provides a file size heterogeneous distributed coding cache placement method and system; the method considers file sizes in the server, local cache capacity limitations of each user terminal and file download request conditions of different user terminals, and employs a distributed coding cache optimal placement method to determine cache proportions of all files cached by all user terminals, thus finally minimizing the server shared link code rate that satisfies various file download requests of the user terminals. The method and system can improve the local cache utilization rate of all user terminals, thus effectively mitigating the server shared link load.

The present invention relates to a replacement method of thread sharing code cache in binary translator and a system thereof. The replacement method comprises the following steps: step 10, dividing local code space into N replaceable units with same magnitude and a never-replaceable unit; step 20, allocating local code from the present replaceable unit until the volume capacity of present replaceable unit obtains a high limit, then allocating local code from the next replaceable unit; and step 30, when the space of local code obtains the high limit of volume capacity, executing local code replacement with the replaceable unit as unit according to a first-in first-out strategy. In the steps N is a natural number. The replaceable unit is used for allocating the common local code and actualizing replacement strategy. The invention presents and realizes the replacement plan of multithread code cache. The replacement plan can be widely suitable for the binary translator on various architectures, and guarantees the concurrency of threads with less expenditure.

The invention discloses a container-based mobile code unloading support system under cloud environment and an unloading method thereof. The mobile code unloading support system comprises a front-end processing layer, a runtime layer and a rear-end resource layer, wherein the front-end processing layer is responsible for responding arrived requests and management container states, and is realized through a request distribution module, a code cache module and a monitoring and dispatching module; the runtime layer is used for providing execution environment same as a terminal for code unloading, and is realized through a runtime module which consists of a plurality of mobile cloud containers; the rear-end resource layer is used for solving the incompatibility, with mobile terminal environment, of a cloud platform and providing bottom resource support for runtime, and is realized through a resource sharing module and a kernel extension module in a host operation system. According to the mobile code unloading support system and the unloading method, the constructed mobile cloud containers are used as runtime environment for code unloading, so that the execution demands of unloading tasks are ensured, the calculated performance of cloud is improved and the request response time is shortened; through the cooperative relationship among the modules, the platform performance is optimized and guarantee is provided for the efficient work of the system.

The invention discloses a method and device for program upgrading, and a controller. The method comprises the steps that a controller reads a verification document stored in a mobile storage device, and unit identification information and a bin document verification code are obtained, wherein the unit identification information and the bin document verification code are stored in the verification document; the controller matches the read unit identification information with identification information of the controller; when matching is successful, the controller copy an update document stored in the mobile storage device in a code cache area; the controller computes a verification code of the code cache area according to the update document written into the code cache area; and the controller uses the update document to achieve updating when the verification code of the code cache area is matched with the bin document verification code. According to the invention, the technical problem in the prior art that wrong document updating can take place easily in application of a USB-based program updating method can be solved.

The invention discloses a communication method and a system based on coding cache and a storage medium. The method comprises the steps of acquiring resident user information in an area; recording a request file of the resident user, and constructing a common file database; when determining that the current time period is the network low-peak time period, updating the resident user information andthe common file database by adopting a file size-based coding cache scheme, and sending a file to the user according to the file size and the file popularity; and when the current time period is determined to be the network peak time period, identifying the size of the request file and determining the group to which the user belongs according to the received user request information, and then sending the same data packet file to the users in the same group by adopting a multicast transmission technology. According to the communication method, the network congestion during peak hours can be relieved, the network pressure is reduced through the multicast transmission technology, the efficiency and the practicability are improved, and the method can be widely applied to the technical field ofcommunication.

The embodiment of the invention discloses an identity authentication method and device, an agent server and a storage medium. The method comprises the steps of: when it is detected that an agent program of a local is started, sending an identity request to a center client, wherein the identity request comprises the identification information of the local; receiving an identity authentication codefrom the center client, and performing cache for the identity authentication codes during the operation of the agent program; receiving a transfer request of the center client, and performing identityauthentication for the center client according to the identity authentication codes carried in the transfer request and the identity authentication codes cached on the local. According to the technical scheme provided by the embodiment of the invention, the instant obtaining and the cache for the identity authentication codes by the agent server when the agent program is started each time so as to ensure the timeliness of identity authentication information and reduce the risk caused by verification failure and illegal authentication because identity authentication information is easily lostand easily obtained.

A system for an agnostic runtime architecture. The system includes a close to bare metal JIT conversion layer, a runtime native instruction assembly component included within the conversion layer for receiving instructions from a guest virtual machine, and a runtime native instruction sequence formation component included within the conversion layer for receiving instructions from native code. The system further includes a dynamic sequence block-based instruction mapping component included within the conversion layer for code cache allocation and metadata creation, and is coupled to receive inputs from the runtime native instruction assembly component and the runtime native instruction sequence formation component, and wherein the dynamic sequence block-based instruction mapping component receives resulting processed instructions from the runtime native instruction assembly component and the runtime native instruction sequence formation component and allocates the resulting processed instructions to a processor for execution.

The invention relates to a dynamic binary translation technology in the field of computer application, and discloses a code Cache management method in the dynamic binary translation. The code Cache comprises a non-skip target Cache and a skip target Cache, and adopts an FIFO (first in and first out) strategy. The method comprises the following steps: determining types of translation basic blocks; executing a non-skip target basic block processing procedure when the basic blocks are non-skip target basic blocks; and executing a skip target basic block processing procedure when the basic blocks are skip target basic blocks. The code Cache management method in the dynamic binary translation has the advantages that translated codes can be cached effectively, and the repeated translation is reduced.

Embodiments of the invention provide a dynamic compilation method and apparatus. The method comprises the steps of obtaining a predicted value of a parameter of a to-be-compiled hotspot method from a code cache of a virtual machine; if it is determined that an input value of parameter input is different from the predicted value, updating the predicted value to the input value; replacing a corresponding variable in an intermediate code with the predicted value after converting the to-be-compiled hotspot method into the intermediate code; and optimizing the replaced intermediate code and converting the optimized intermediate code into a to-be-executed local target code. According to the dynamic compilation method and apparatus provided by the embodiments of the invention, the scale of codes generated by compilation can be reduced and the system performance of the virtual machine can be improved.

A method and apparatus for providing support for self modifying guest code. The apparatus includes a memory, a hardware buffer, and a processor. The processor is configured to convert guest code to native code and store converted native code equivalent of the guest code into a code cache portion of the processor. The processor is further configured to maintain the hardware buffer configured for tracking respective locations of converted code in a code cache. The hardware buffer is updated based a respective access to a respective location in the memory associated with a respective location of converted code in the code cache. The processor is further configured to perform a request to modify a memory location after accessing the hardware buffer.

The invention discloses a verification code verification method and device, which are used for solving the problem of verification code verification failure when a cache server crashes or a network isabnormal in the prior art. The verification code verification method comprises: enabling a verification server to receive a verification request sent by a terminal; allocating a verification code tothe terminal according to the verification request, and sending the allocated verification code to a cache server for caching; encrypting the allocated verification code and the validity period thereof by using a private key to generate an encrypted string; writing the encrypted string into a verification code picture carrying the allocated verification code by using picture steganography, and returning the verification code picture to the terminal; receiving a verification code input by a user and sent by a terminal, obtaining the verification code cached by the cache server and allocated tothe terminal, and performing verification code verification; and when it is determined that acquisition of the verification code cached by the cache server fails, returning cache exception informationto the terminal, so as to enable the terminal to perform local verification code verification according to the verification code input by the user and the verification code picture.

The invention discloses a distributed memory column type database compilation actuator architecture, which solves the problem of execution speed defect on a DAG operator execution mode in a distributed memory column type database. A compiling actuator system on a single machine comprises a matching and scheduling device, an IR / Bitcode generator, a local IR code cache manager, a compiler, an executable code cache manager and an actuator. The local IR code cache manager comprises a local IR code cache unit, and the executable code cache manager comprises an executable code cache unit. The architecture also comprises a matching and scheduling device, an IR / Bitcode generator and a local IR code caching unit. The device is used for coordinating the local IR code cache manager and the executablecode cache manager, managing mapping information, carrying out matching code execution on an DAG task of an external request or generating a code, and responding to the external request. The IR / Bitcode generator is used for generating IR codes for the DAG task which are not matched with the executable code. The local IR code caching unit is used for performing caching management on the IR code generated by the IR / Bitcode generator.