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18 results about "Memory virtualization" patented technology
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In computer science, memory virtualization decouples volatile random access memory (RAM) resources from individual systems in the data centre, and then aggregates those resources into a virtualized memory pool available to any computer in the cluster. The memory pool is accessed by the operating system or applications running on top of the operating system. The distributed memory pool can then be utilized as a high-speed cache, a messaging layer, or a large, shared memory resource for a CPU or a GPU application.
The invention relates to a virtualized nested translation method and system and a readable medium. The method comprises the following steps: receiving a virtual address translation request, judging an address translation mode of the virtual address translation request, and determining a virtual address type; selecting a corresponding translation cache according to the determined virtual address type; under the selected translation cache, executing address translation in the multi-level translation cache by adopting a parallel or serial lookup mode to obtain a lookup result; judging whether the search result hits a leaf item of the page table or not; if the searching result hits the leaf item, the corresponding physical address is returned to complete translation; and if the leaf item is not hit, performing page table traversal to obtain the physical address. According to the method, the speed of virtualization nested translation can be increased, the translation cache redundant virtual address and the translation path cache redundant PTE under the single technical condition are reduced, and the translation delay from the virtual address to the physical address in memory virtualization or peripheralvirtualization is improved.
This invention discloses a GPU memory virtualization method and apparatus based on deep parsing of the ioctl protocol, belonging to the field of electronic information technology. The method includes: intercepting ioctlsystem call requests initiated by the target container to obtain ioctlsystem call requests for GPU memory management; parsing its parameter blocks and extracting memory-related instructions to obtain memory-related instructions for subsequent auditing; constructing a shadow object tree and intelligently auditing memory allocation and mapping operations to obtain a precise memory usage ledger; determining whether the quota has been exceeded and executing interception during the physical admission control phase to obtain a control result on whether instruction pass-through is allowed; implementing view virtualization and returning virtualized memory information to the application in the target container to achieve transparent application adaptation, thereby completing precise virtualization isolation and multi-tenant secure sharing of GPU memory. This invention combines kernel-level control strength with user-space deployment flexibility.
The application relates to a memory virtualization address substitution efficiency improving method and device, wherein the method comprises the following steps: a core analyzes received last address reading response data and forms a current address, and sends a memory access request for the current address; an out-core Cache control component receives the memory access request for the current address, judges whether the generation of a next address depends on the current address, registers a prefetch starting flag and a low-bit address if the generation of the next address depends on the current address, and judges whether the prefetch request for the current address is executed; if the prefetch request for the current address is executed, reading response data of the current address is directly generated; if the prefetch request for the current address is not executed, the reading request for the current address is combined into the prefetch request for the current address, and the reading response data of the current address is generated after data from other cores or a main memory is received; the next address is formed based on the reading response data of the current address and the low-bit address, and a prefetch request for the next address is triggered. The application can improve the efficiency of substituting a guest machine virtual address into a host machinephysical address.
A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.
Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.
The invention belongs to the technical field of aviationelectromechanics, and particularly relates to an embedded software SPI interface memory virtualization device and method. The system is composed of an SPI bus module, a monitoring module, a storage module and a configuration module, and the SPI bus module is composed of a chip selection signal line, a clocksignal line, an input data line and an output data line and used for being cross-linked with an SPI interface of a virtual processor; the monitoring module is crosslinked with the SPI bus module and the storage module at the same time; the storage module is crosslinked with the SPI bus module and the monitoring module at the same time; and the configuration module is crosslinked with the monitoring module and the storage module. The method provided by the invention does not aim at a specific hardware platform, can be suitable for any hardware platform after abstracting the hardware model, and does not need hardware investment due to the adoption of the virtualization method, so that the economic benefit is good, and the application and popularization value is relatively high.
The invention discloses a memory virtualization method, which comprises the following steps of: firstly, configuring an address conversion table, and then performing conversion between a virtual address and a physical address of a memory through the address conversion table. Through memory virtualization, memory resources of the deep learningsystem can be stored in a delayed manner during task switching, so that the memory moving amount stored on site is reduced.
A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.
The present invention relates to a virtualization nested translation method, system and readable medium, comprising receiving a virtual address translation request, judging the address translation mode of the virtual address translation request, and determining the virtual address type; selecting a corresponding translation cache according to the determined virtual address type; performing address translation in a multi-level translation cache in a parallel or serial search mode under the selected translation cache to obtain a search result; judging whether the search result hits a leaf item of a page table; if the search result hits a leaf item, returning a corresponding physical address to complete the translation; if the leaf item is not hit, performing a page table traversal to obtain a physical address. The method can improve the speed of virtualization nested translation, reduce redundant virtual addresses of a translation cache and redundant PTEs of a translation path cache under a single technical condition, and improve the translation delay from a virtual address to a physical address in memory virtualization or peripheralvirtualization.
The invention relates to a memory virtualization address substitution efficiency improving method and device, and the method comprises the steps: a core analyzes the received previous address read response data, forms a current address, and sends a memory access request for the current address; after receiving the memory access request of the current address, the off-core Cache control component judges whether the generation of the next address depends on the current address or not; if yes, registering a prefetching start flag and a low address, and judging whether the prefetching request of the current address is executed or not; if the execution is finished, directly generating read response data of the current address; if the execution is not completed, merging the read request of the current address into the prefetch request of the current address, and generating read response data of the current address after receiving data of other cores or main memories; and forming a next address based on the read response data of the current address and the low address, and triggering a pre-fetching request for the next address. According to the invention, the efficiency of replacing the virtual address of the client into the physical address of the host can be improved.
The present application relates to the technical field of computer systemvirtualization, in particular to a virtual machinememory virtualization method and system for a Sunway processor. The method manages the reserved continuous physical memory through a virtual memory device, and provides a standard interface to the user state; the virtual machine obtains continuous memory as the guest physical memory through the interface; and then the direct mapping of the guest physical address to the host physical address is established by using the segment mapping of the virtual mode of the Sunway processor. The system comprises corresponding memory pools, driving modules and other components. The scheme realizes near-zero overhead address conversion on the Sunway platform without hardware assistance, and solves the flexible management and efficient sharing of the guest memory across processes through the device interface for the first time.
The invention discloses an embedded model scheduling method and device based on video memory optimization and electronic equipment, through combination of fine-grained video memoryvirtualization and a dynamic compression technology, precise scheduling and efficient utilization of limited video memory resources of embedded equipment are realized, and the embedded model scheduling efficiency is improved. Meanwhile, environmental dependence is eliminated through self-adaptive matching of the container mirror image, so that the technical problems of serious video memory fragmentation and insufficient resource utilization rate caused by neglecting the physical constraint of the video memory of the embedded equipment in the prior art can be solved, and the purposes of remarkably improving the video memory utilization rate, reducing the resource fragmentation and improving the resource utilization rate are achieved. And the large-scale deployment stability of the real-time reasoning task in the edge calculation scene is ensured.