13results about How to "Reduce switching overhead" patented technology

The invention discloses a computer multi-process fair scheduling method, and relates to the technical field of multi-process resource allocation in a parallel computer architecture, the processes are dynamically divided into an I / O intensive type and a CPU intensive type through process classification and feature recognition, and the types of the processes are judged by monitoring the CPU use time and the I / O waiting time of each process. A scheduling strategy is set for each process, different priority adjustment strategies are formulated for different types of processes in dynamic priority adjustment, the length of time slices is dynamically adjusted according to the types of the processes, short time slices are allocated for I / O intensive processes, frequent I / O operation is allowed, returning is conducted in time, and waiting time is shortened. Compared with the prior art, the method has the advantages that long time slices are distributed for CPU intensive processes, frequent context switching expenses are reduced, the CPU utilization rate is increased, the execution requirements of different types of processes are better balanced by dynamically adjusting the lengths of the time slices, and the resource utilization efficiency of a system is improved.

The present application discloses a beam switching prediction method, device and storage medium for an antenna array, including: determining the first position of the mobile body in the next period based on the navigation information of the predetermined mobile body, wherein the mobile body is provided with an antenna array; determining multiple beams connected to the mobile body at the first position of the mobile body in the next period according to the ephemeris information and the beam scheduling information of each first satellite; predicting the target beam connected to the mobile body from multiple beams based on a preset neural network model; generating a corresponding antenna connection optimization function based on an initialized population including multiple first antenna connection vectors corresponding to the antenna array, and determining the optimal solution of the target optimization function corresponding to the multiple antenna connection optimization functions using a genetic algorithm; and predicting the target antenna connected to the target beam when the optimal solution of the target optimization function is determined. The technical effect of reducing the switching overhead of the antenna array is achieved.

This application discloses a method, apparatus, device, and storage medium for large file transmission, relating to the field of computer storage and network transmission technology. The method includes: allocating independent virtual threads to each segment of file content; using the virtual threads to perform parallel compression on each segment of file content to obtain segmented compressed data; employing a two-layer key derivation algorithm to determine a segment-level derivation key and a one-time random number for each segment of file content; encrypting the segmented compressed data using the virtual threads to obtain encrypted segmented data for each segment of file content and uploading it to an object storage space; and, upon successful uploading of all segmented file content, obtaining signed encrypted metadata and uploading it to the object storage space, and binding it to the encrypted segmented data. This scheme, with its two-layer key structure, intelligent dynamic compression, and parallel streaming processing via virtual threads, improves the efficiency and security of large file transmission.

The application provides a communication frequency selection method and system based on multi-factor heuristic adaptive scoring, which first initializes a candidate frequency point set and related parameters, and then collects channel state parameters of each frequency point in each decision time slot. After normalization processing, the collected parameters enter the EWMA history smoothing link to obtain more stable frequency point evaluation results. According to the current communication environment, corresponding weight configuration is selected, and the comprehensive heuristic score of each selected frequency point is calculated. If the SINR of the current working frequency point is lower than the set threshold or the packet loss rate is higher than the set threshold, the fast reselection mechanism is triggered to directly select the frequency point with the better score; if the fast reselection mechanism is not triggered, the regular hysteresis judgment is entered, and only when the selected frequency point has sufficient score advantage over the current frequency point and overcomes the switching cost, the frequency switching is performed, thereby improving the stability of the communication frequency selection.

The invention discloses a design for improving the concurrency capability of an NoSQL non-relational database under a multi-core architecture, and belongs to the field of database system architectures. Multiple threads of the Sudis make full use of the multi-core advantage, different thread pool configurations can be carried out according to different cpu, the Sudis is divided into multiple thread pools, the thread pools can not interfere with one another, the performance of the Sudis is improved, long connection can be established between a user and the Sudis, the long connection exists in the form of clients in the Sudis, each client has a unique ID, and the service life of the user is prolonged. The method comprises the steps that a client side sends a request to a receiving thread for processing, the request of the Sudis is divided into processing of one key or multiple keys, when a single key is processed, calculation distribution is directly carried out, all the requests of the key are distributed to the same thread for processing, locking is not needed, multi-thread locking expenses are saved, aggressive distribution processing is carried out on the multiple keys in sequence, and the processing efficiency is greatly improved. And after the last thread finishes key processing, results are summarized, so that the performance of the whole system is improved.

The present invention proposes a model generation and real-time construction method for unsupervised learning models, including: step 1, obtaining the original model; step 2, generating a model block, obtaining a derived model block according to the model block, and constructing a training environment for each derived model block; step 3, training the derived model block and updating the parameters of the derived model block; step 4, evaluating all model blocks to quantify the performance indicators and use value of the model block; step 5, modeling the edge reasoning scenario, constrained optimization problem; step 6, solving the constructed optimization problem; step 7, generating a new model according to the solved model block selection scheme, and scaling the model. The method avoids the influence of instability in unsupervised learning on the generation of derived models, ensures the high precision of derived models; reduces the offline generation cost of derived models in unsupervised learning and the online cost of real-time scaling models in edge reasoning.

This invention discloses a vector processor system and method, wherein the system includes: a status recording unit for storing a first identifier in a corresponding vector register status information table; a vector execution unit for sending a first vector instruction and its corresponding arbitration request instruction to an arbitrator; the arbitrator for determining, based on the arbitration request instruction and the status information tables of each vector register, whether the first vector instruction has a write-after-read data dependency; if not, determining that the first vector instruction has obtained execution permission; an address generation unit for determining the real-time access address of the data segment to be accessed based on the first vector instruction that has obtained execution permission and vector configuration parameters; and the vector execution unit for retrieving data from the vector register stack based on the real-time access address and performing vector processing. This invention can realize data segment-level dependency determination in long vector chain execution scenarios, improving the utilization rate of the vector execution unit and the overall execution efficiency and throughput of the vector processor.

The invention discloses a method in a wireless local area network system and a non-access point station. According to various embodiments, a multi-link device (MLD) operating in a plurality of links including a first link may transmit, by a first STA (station), a request frame to a first AP of the AP MLD, where the request frame includes an information field for requesting each element included in an element set specified for a second link. The MLD may receive each element included in a set of elements specified for the second link based on the request frame.

The invention relates to a convolutional neural network acceleration technology, and provides a convolutional neural network accelerator designed on an ARM + FPGA heterogeneous platform. The ARM end generates a task descriptor containing Deadline, Cbudget and Bbudget, and predicts a budget; dynamic scheduling based on slack is adopted at the FPGA end, preemptive execution is implemented with tile as granularity, and context such as paraalsum and output buffer is stored / recovered at the boundary of the tile; and meanwhile, bandwidth shaping is carried out on DMA access by using a token bucket and a time slice, so that the bandwidth of each task does not exceed Bbudget. According to the scheme, DDR contention and delay jitter are reduced in a multi-task scene, and the real-time deadline satisfaction rate and the array utilization rate are improved.

The invention discloses a method in a wireless local area network system and a non-access point station. According to various embodiments, a multi-link device (MLD) operating in a plurality of links including a first link may transmit, by a first STA (station), a request frame to a first AP of the AP MLD, where the request frame includes an information field for requesting each element included in an element set specified for a second link. The MLD may receive each element included in a set of elements specified for the second link based on the request frame.

The present invention provides a time synchronization method for integrated inter-satellite and intra-satellite communications based on TSN, which can implement a time-sensitive network protocol within the inter-satellite satellite to achieve time synchronization of inter-satellite and intra-satellite data communications. The present invention studies the corresponding scheduling mechanism algorithms respectively according to the business requirements of intra-satellite and inter-satellite communications, implements a time-sensitive network protocol within the inter-satellite satellite, and performs data communication, which involves the TSN standard. The present invention has low time synchronization requirements while meeting time-sensitive business requirements, and the implementation cost and complexity are reduced compared to the TTE network. The TTE clock synchronization is based on the IEEE 1588 protocol, and its time synchronization accuracy reaches 100ns; the TSN clock synchronization is based on the IEEE802.1AS protocol, and the end-to-end synchronization time is maintained on the devices running and controlling the applications.

The application relates to a kind of MC-DSSS space-air-ground integrated network energy efficiency collaborative optimization methods, belong to wireless communication field.The application implementation method is: the physical layer transmission model based on constant envelope MC-DSSS is constructed, the high PAPR of multicarrier spread spectrum signal is suppressed using CEMIC, and the operating efficiency of high power amplifier is improved.The application ensures the constant envelope characteristics of the transmitted signal while ensuring the signal orthogonality by accurate power allocation and intermodulation optimization, reduces the energy efficiency loss of the system.The application introduces the network layer switching strategy based on improved binary particle swarm optimization IBPSO-HO, establishes the hysteresis trigger mechanism and multi-attribute decision model, reduces unnecessary satellite switching and signaling overhead.The application realizes the joint optimization of physical layer waveform parameters and network layer switching decision through double-layer collaborative optimization, maintains the stability and efficiency of the system under dynamic channel conditions, ensures the communication quality, and realizes the energy efficiency collaborative optimization of MC-DSSS space-air-ground integrated network.

The application relates to the technical field of task scheduling, and discloses an NPU resource management method, device and system, electronic equipment and a storage medium. The method comprises the following steps: pre-allocating and persisting physical display memory as a shared display memory pool for multiple client processes to share and access through a lease mode; when it is necessary to release NPU resources, releasing the lease of a target client process to give up the use right of the display memory, and keeping the virtual address mapping of the target client process unchanged, wherein the virtual address mapping is established based on a target display memory region allocated to the target client process in the shared display memory pool; when it is necessary to restore the NPU resources, re-acquiring the lease for the target client process to restore the use right of the display memory, and reusing the kept virtual address mapping. The application decouples the allocation and release of the physical display memory from the Sleep / Wake switching of the client process, so that the display memory switching time is no longer proportional to the display memory occupancy, and the efficiency of the multi-process dynamic scheduling and the overall throughput of the system are significantly improved.