4results about How to "Reduce switching overhead" patented technology

This application discloses a method, apparatus, device, and storage medium for large file transmission, relating to the field of computer storage and network transmission technology. The method includes: allocating independent virtual threads to each segment of file content; using the virtual threads to perform parallel compression on each segment of file content to obtain segmented compressed data; employing a two-layer key derivation algorithm to determine a segment-level derivation key and a one-time random number for each segment of file content; encrypting the segmented compressed data using the virtual threads to obtain encrypted segmented data for each segment of file content and uploading it to an object storage space; and, upon successful uploading of all segmented file content, obtaining signed encrypted metadata and uploading it to the object storage space, and binding it to the encrypted segmented data. This scheme, with its two-layer key structure, intelligent dynamic compression, and parallel streaming processing via virtual threads, improves the efficiency and security of large file transmission.

This invention discloses a vector processor system and method, wherein the system includes: a status recording unit for storing a first identifier in a corresponding vector register status information table; a vector execution unit for sending a first vector instruction and its corresponding arbitration request instruction to an arbitrator; the arbitrator for determining, based on the arbitration request instruction and the status information tables of each vector register, whether the first vector instruction has a write-after-read data dependency; if not, determining that the first vector instruction has obtained execution permission; an address generation unit for determining the real-time access address of the data segment to be accessed based on the first vector instruction that has obtained execution permission and vector configuration parameters; and the vector execution unit for retrieving data from the vector register stack based on the real-time access address and performing vector processing. This invention can realize data segment-level dependency determination in long vector chain execution scenarios, improving the utilization rate of the vector execution unit and the overall execution efficiency and throughput of the vector processor.

The invention relates to a convolutional neural network acceleration technology, and provides a convolutional neural network accelerator designed on an ARM + FPGA heterogeneous platform. The ARM end generates a task descriptor containing Deadline, Cbudget and Bbudget, and predicts a budget; dynamic scheduling based on slack is adopted at the FPGA end, preemptive execution is implemented with tile as granularity, and context such as paraalsum and output buffer is stored / recovered at the boundary of the tile; and meanwhile, bandwidth shaping is carried out on DMA access by using a token bucket and a time slice, so that the bandwidth of each task does not exceed Bbudget. According to the scheme, DDR contention and delay jitter are reduced in a multi-task scene, and the real-time deadline satisfaction rate and the array utilization rate are improved.

The application relates to the technical field of task scheduling, and discloses an NPU resource management method, device and system, electronic equipment and a storage medium. The method comprises the following steps: pre-allocating and persisting physical display memory as a shared display memory pool for multiple client processes to share and access through a lease mode; when it is necessary to release NPU resources, releasing the lease of a target client process to give up the use right of the display memory, and keeping the virtual address mapping of the target client process unchanged, wherein the virtual address mapping is established based on a target display memory region allocated to the target client process in the shared display memory pool; when it is necessary to restore the NPU resources, re-acquiring the lease for the target client process to restore the use right of the display memory, and reusing the kept virtual address mapping. The application decouples the allocation and release of the physical display memory from the Sleep / Wake switching of the client process, so that the display memory switching time is no longer proportional to the display memory occupancy, and the efficiency of the multi-process dynamic scheduling and the overall throughput of the system are significantly improved.