459results about "Program saving/restoring" patented technology

An online system trains a transformer architecture by an initialization method which allows the transformer architecture to be trained without normalization layers of learning rate warmup, resulting in significant improvements in computational efficiency for transformer architectures. Specifically, an attention block included in an encoder or a decoder of the transformer architecture generates the set of attention representations by applying a key matrix to the input key, a query matrix to the input query, a value matrix to the input value to generate an output, and applying an output matrix to the output to generate the set of attention representations. The initialization method may be performed by scaling the parameters of the value matrix and the output matrix with a factor that is inverse to a number of the set of encoders or a number of the set of decoders.

The invention relates to the technical field of script execution, and provides a multi-script execution method for a virtual controller, and the method comprises the steps: setting a script structure, a graph model structure and a graph node structure; the method comprises the following steps: performing grammar and semantic check on script data to be executed, converting the script data into a script object according to a script structure, converting the script data into a directed acyclic graph according to a graph model structure, and traversing the directed acyclic graph to obtain an execution sequence of graphs in each level of the directed acyclic graph; and scheduling the script object according to an FIFO algorithm, traversing the directed acyclic graph during scheduling to obtain graph nodes in each execution sequence, and performing interpretive execution on the script object according to an ignition rule and the graph nodes in each execution sequence. The method aims at analyzing and executing various scripts, the reliability of the virtual production line is further improved, and the use cost of the platform is reduced.

Disclosed herein are systems and method for restoring a process. An exemplary method may include detecting a crash of an operating system (OS) on a computing device; collecting a memory state of at least one page of physical memory of the OS on the computing device; generating a checkpoint file that includes information related to one or more processes from the collected memory state, wherein the information comprises a state for each of the one or more processes at a time of the crash; for each respective process of the one or more processes, creating, on the computing device or another computing device, a new process corresponding to the respective process; and restoring, based on the checkpoint file, a state of the respective process at the time of the crash such that the new process initiates execution from the restored state.

Systems and methods for efficient context switching in multithread processors are disclosed. A processing system comprises a direct memory access module configured to detect a preemption request generated by the scheduling circuit. Responsive to the preemption request, the direct memory access module determines whether execution of a first task from a plurality of tasks needs to be replaced by execution of a second task. When the replacement is necessitated, the module saves a first plurality of registers associated with the first task at a memory location transmitted by the scheduling circuit and queues the second task for execution. The memory location is transmitted by the scheduling circuit as part of the preemption request.

The embodiment of the invention provides a process freezing method and device, relates to the field of terminals, and can reduce resource consumption of background processes and improve performance and endurance of electronic equipment. The method is applied to the electronic equipment and comprises the steps of creating a target thread in response to that the electronic equipment is in a first scene; determining a to-be-frozen process based on the target thread; and the process to be frozen is set to be in an uninterruptible sleep state based on the target thread, and the process to be frozen is set to be in an uninterruptible sleep state based on the target thread.

The invention discloses a graphics processor thread mid-term preemption. Techniques are provided that enable thread mid-term (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Execution of a kernel program by a graphics processor is triggered using threads of the graphics processor to dispatch hardware to facilitate hardware-based thread mid-term preemption, the graphics processor holding thread states of preempted processing resources and facilitating subsequent recovery of the thread states to the same or different sets of processing resources.

Systems and methods for crowdsourcing cloud application execution are described. An application system receives, from a client device, a first request to initiate an application session. The application system identifies a host device to fulfill the first request. The application system then initiates execution of the application session on the host device and generates, for the client device, a plurality of controls to control the application session executing on the host device. The host device is incentivized for each application session hosted.

This disclosure describes a large language model (LLM)-based agent operating system comprising an application layer, a kernel layer, and a hardware layer. The kernel layer comprises an AIOS kernel comprising: LLM core(s), an agent scheduler, a context manager, a memory manager, a storage manager, and a system call interface configured to manage interactions among the agent scheduler, the context manager, the memory manager, and the storage manager.

A microprocessor includes a function-specific architecture, an interface configured to communicate with an external memory via at least one memory channel, a first architecture block configured to perform a first task associated with a thread, and a second architecture block configured to perform a second task associated with the thread. The second task includes a memory access via the at least one memory channel. The microprocessor further includes a third architecture block configured to perform a third task associated with the thread. The first architecture block, the second architecture block, and the third architecture block are configured to operate in parallel such that the first task, the second task, and the third task are all completed during a single clock cycle associated with the microprocessor.

The invention is suitable for the technical field of terminals, and particularly relates to a memory management method, electronic equipment and a computer readable storage medium. According to the method, when it is detected that the first application is switched to the background state, the electronic device can determine that the first application does not need to display an image and does not need to carry out graphic rendering, that is, it can be determined that the first application does not need to use a GPU physical memory currently. At the moment, the electronic equipment can store the first content stored in the first GPU physical memory corresponding to the first application to a disk, and can release the first GPU physical memory, so that the occupation of the GPU physical memory is reduced, the remaining available physical memory of the electronic equipment can be increased, the response speed of the electronic equipment to user operation is increased, the fluency of the system is improved, and the user experience is improved. And user experience is improved.

The invention provides a virtual machine crashing event processing method and device and a storage medium. According to the method, when a crashing event occurs in a second virtual machine facing a hardware layer of the electronic equipment, a first virtual machine which does not generate the crashing event and bears an operating system temporarily takes over resources occupied by the second virtual machine, the second virtual machine is restarted independently, and after the second virtual machine is restarted, the first virtual machine does not generate the crashing event and bears the operating system. And returning the resources of the second virtual machine taken over by the first virtual machine to the second virtual machine. Therefore, only the second virtual machine with the crashing event is self-recovered, and the electronic equipment is not triggered to restart the whole machine, so that the user perception is reduced, and the user experience is improved.

The invention discloses an RISC-V context switching optimization method and device and a medium, and belongs to the technical field of processors. The method comprises the steps of executing a current task based on the computing core; when a context switching operation is triggered, determining the residual space of the register stack based on the numerical value of the stack top register; judging whether the register stack can store the current task or not based on the residual space and the current task; if not, storing the current task based on the memory; if yes, storing the current task based on the register stack; and executing a replacement task based on the computing core, and switching back to the current task through the stack top register when the replacement task is completed. According to the method, the effect of improving the context switching speed in the RISC-V is achieved.

In an apparatus for data processing comprising a data processing pipeline and decoder101: extension processing circuitry 103, e.g. threadlet extension, performs delegated tasks in response to delegati

The embodiment of the invention discloses a thread priority adjustment method and related equipment which are applied to electronic equipment, and the electronic equipment runs a first application. A first process of the first application comprises a plurality of first threads; identifying an associated thread of the first thread from the threads of the second process; the second process is a process which is operated by the electronic equipment, except the first process and the resident process and provides service for the first application; when it is detected that the running state of the first application is changed, the priority of the first thread is adjusted, the priority of the associated thread is adjusted, and the priority adjustment trend of the associated thread is consistent with the priority adjustment trend of the first thread. By adopting the embodiment of the invention, the response speed and performance of the system can be improved, and the user experience is improved.

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

A task scheduling method is provided, including: acquiring task data of all to-be-started tasks, with the task data including procedure numbers, processing durations, processing positions, and processing-position stop durations corresponding to all procedures corresponding to the to-be-started tasks; and inputting the task data of each to-be-started task to a task scheduling model to obtain a start moment of each to-be-started task which is output by the task scheduling model. The task scheduling model takes minimizing total time required for performing all the to-be-started tasks as an objective function, and constraint conditions of the task scheduling model are associated with the task data. The method includes performing task scheduling on the to-be-started tasks according to the start moment of each to-be-started task.

The embodiment of the invention discloses a multi-thread scheduling method, a server and a computer system, which are used for avoiding multi-thread cross-node far-end access and reducing the overhead for running a first thread and a second thread. The method comprises the steps that genetic relationship information between a first thread and a second thread is determined according to first memory access information of the first thread in a first operation stage and second memory access information of the second thread in a second operation stage; determining a first node according to the first memory access information, the second memory access information and the genetic relationship information; determining that the resource metric value of the first node is smaller than a resource threshold value; a processor unit for running the first thread and the second thread is selected from the first node.

Computer devices and management methods are provided. In an implementation, a computer device includes a subrack common component and a plurality of service nodes, wherein each of the plurality of service nodes comprises a baseboard management controller (BMC connected to the subrack common component and configured to manage the subrack common component when being in a primary status.

The embodiment of the invention discloses a test system and method and chip test equipment. The test system comprises a task flow scheduling module, a plurality of distribution modules and a plurality of test execution modules, the task flow scheduling module is used for splitting and sorting test tasks to obtain a plurality of sub-task flow sequences; the distribution module is used for splitting and sorting the test items in the plurality of sub-task flow sequences to obtain a plurality of test item sequences; and the test execution module is used for controlling the chip test equipment to execute each test item in the plurality of test item sequences so as to perform parallel test on the to-be-tested device to obtain a test result. Therefore, the execution mode of the test task is automatically converted into the parallel execution mode, and the situation that the chip test equipment cannot test the test device due to parallel test item determination errors and test code modification errors caused by manual adjustment to the parallel execution mode is avoided.

The invention discloses an agent context management system and device based on importance sampling, and belongs to the technical field of artificial intelligence and agents, the agent context management system and device based on importance sampling comprise a global context manager used for maintaining and managing eight types of context information; the task stack manager is used for receiving a new request and performing task splitting; and the recursive execution engine is used for executing the task in a recursive mode and controlling the recursive depth. Eight types of context information are maintained through a global context manager, splitting and storage of complex tasks are achieved through a task stack manager, a recursive execution engine provides an efficient task execution mechanism and controls the recursive depth, an importance sampler selects related contexts based on a joint probability model, and the task execution efficiency is improved. And the context compressor combines the sampling fragments into a final context, and the task scheduler coordinates the working process of each component, so that a complete agent collaborative context management system is constructed.

Disclosed in the embodiments of the present application are a multi-thread scheduling method, a server and a computer system, used for avoiding multi-threading cross-node remote access and reducing overhead of running a first thread and a second thread. The method in the embodiments of the present application comprises: according to first memory access information of a first thread in a first running stage and second memory access information of a second thread in a second running stage, determining information of affinity between the first thread and the second thread; according to the first memory access information, the second memory access information and the information of affinity, determining a first node; determining that a resource metric value of the first node is less than a resource threshold value; and selecting from the first node a processor unit used for running the first thread and the second thread.

The invention provides a frozen screen processing method and electronic equipment. The first component can be displayed on a screen of the electronic device. The first component has the ability to respond to a first operation. When a first operation on the first component is detected, the electronic device may detect whether the first component responds to the first operation. If the first component does not respond to the first operation, the electronic device can redraw the first component on the screen. According to the method, whether the frozen screen occurs in the electronic equipment or not can be detected according to whether the component displayed on the screen responds to the user operation or not, and when the frozen screen occurs in the electronic equipment, the component required to be used by the user is quickly recovered and responded by locally redrawing the component, so that the frozen screen problem is quickly solved, and the waiting time of the user is shortened.

The invention discloses a satellite-borne operating system-oriented RISCV processor abnormal context protection and recovery method, which supports that the satellite-borne operating system is allowed to be abnormally interrupted no matter in a task, in an interrupt processing program or in an interrupt context protection or recovery process, and can effectively store and recover a site. In a space environment where single-particle events frequently occur, the context can be effectively protected and recovered under the abnormal condition of a processor, normal and continuous operation of software is ensured, and the reliability of a spaceborne computer is improved.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, one or more circuit elements trigger saving of architecture state information of at least one PE to at least one memory prior to the at least one PE transitioning from a first state to a second state and triggering restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

An apparatus and method for efficiently performance among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with an instantiated copy of particular integrated circuitry for processing a work block. One or more of the functional blocks of the integrated circuit belong in a different performance category or bin than other functional blocks due to manufacturing variations across semiconductor dies. A scheduler assigns work blocks to the functional blocks based on whether a functional block is from a high-performance bin and whether a workload of a work block is a computation intensive workload. The scheduler assigns work blocks work blocks marked as having a memory access intensive workload to functional blocks from a lower performance bin.

The disclosure herein describes platform-level checkpointing for deep learning (DL) jobs. The checkpointing is performed through capturing two kinds of state data: (i) GPU state (device state), and (ii) CPU state (host state). The GPU state includes GPU data (e.g., model parameters, optimizer state, etc.) that is located in the GPU and GPU context (e.g., the default stream in GPU, various handles created by the libraries such as DNN, Blas, etc.). Only a fraction of the GPU memory is copied because the checkpointing is done in a domain-aware manner. The “active” memory contains useful data like model parameters. To be able to capture the useful data, memory management is controlled to identify which parts of the memory are active. Also, to restore the destination GPU to the same context / state, a mechanism is used to capture such state-changing events on an original GPU and replayed on a destination GPU.

In accordance with an embodiment, described herein are systems and methods for auto-completion of ICS flow using artificial intelligence / machine learning. Next actions prediction is a service that assists users in modeling the flows quickly by predicting and suggesting the next set of actions a user might be thinking of adding. The service also assists the user to follow some of the best practices while creating an integration flow.

The invention provides a target object control method and device, electronic equipment, a medium and a product, and relates to the technical field of intelligent robots, a target object comprises dual-core heterogeneous processors, instruction sets and / or operating systems corresponding to the dual-core heterogeneous processors are different, and the dual-core heterogeneous processors share hardware resources; the method comprises the steps that in the starting process of any subsystem in an operating system of a target object, the running state of the dual-core heterogeneous processor is detected; in the embodiment of the invention, under the condition that the running state is determined to be abnormal, the information of the currently running task of the dual-core heterogeneous processor is stored, and the operating system of the target object is restarted based on the task information, so that the task is quickly recovered when the operating system has a problem, the task can be continuously executed from an interruption point after restarting, and the downtime is reduced.

The embodiment of the invention provides a virtual processor context switching method and device, a storage medium and electronic device.The method comprises the steps that under the condition that a current virtual processor receives an interrupt signal, the affinity attribute of a current task executed on the current virtual processor is determined; under the condition that the affinity attribute represents that the virtual processor associated with the current task is the first virtual processor, predicting the switching probability of the current task; under the condition that the switching probability is greater than or equal to a preset probability threshold value, pre-caching context information of the first virtual processor in a cache region; when a context switching request is received, the current task is interrupted, the context information of the first virtual processor is extracted from the cache region and loaded to the first virtual processor, and the interrupted current task continues to be executed on the first virtual processor. And the problem of low virtualization real-time performance is solved.

Techniques are provided for backing up virtual machines from a computing environment to a storage environment. A virtual machine agent is utilized to generate a snapshot of the virtual machine. Metadata comprising a snapshot identifier of the snapshot and virtual disk information of virtual disks captured by snapshot is generated at the computing environment. The metadata is retrieved and used to create a metafile that is transferred to the storage environment within which snapshots of the virtual machine are to be stored. The snapshot is retrieved from the computing environment and is packaged into a snapshot package having a protocol format used by the storage environment. The snapshot package is transferred to the storage environment.