275results about "Program saving/restoring" patented technology

An online system trains a transformer architecture by an initialization method which allows the transformer architecture to be trained without normalization layers of learning rate warmup, resulting in significant improvements in computational efficiency for transformer architectures. Specifically, an attention block included in an encoder or a decoder of the transformer architecture generates the set of attention representations by applying a key matrix to the input key, a query matrix to the input query, a value matrix to the input value to generate an output, and applying an output matrix to the output to generate the set of attention representations. The initialization method may be performed by scaling the parameters of the value matrix and the output matrix with a factor that is inverse to a number of the set of encoders or a number of the set of decoders.

The embodiment of the invention provides a process freezing method and device, relates to the field of terminals, and can reduce resource consumption of background processes and improve performance and endurance of electronic equipment. The method is applied to the electronic equipment and comprises the steps of creating a target thread in response to that the electronic equipment is in a first scene; determining a to-be-frozen process based on the target thread; and the process to be frozen is set to be in an uninterruptible sleep state based on the target thread, and the process to be frozen is set to be in an uninterruptible sleep state based on the target thread.

The invention discloses a graphics processor thread mid-term preemption. Techniques are provided that enable thread mid-term (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Execution of a kernel program by a graphics processor is triggered using threads of the graphics processor to dispatch hardware to facilitate hardware-based thread mid-term preemption, the graphics processor holding thread states of preempted processing resources and facilitating subsequent recovery of the thread states to the same or different sets of processing resources.

This disclosure describes a large language model (LLM)-based agent operating system comprising an application layer, a kernel layer, and a hardware layer. The kernel layer comprises an AIOS kernel comprising: LLM core(s), an agent scheduler, a context manager, a memory manager, a storage manager, and a system call interface configured to manage interactions among the agent scheduler, the context manager, the memory manager, and the storage manager.

The invention is suitable for the technical field of terminals, and particularly relates to a memory management method, electronic equipment and a computer readable storage medium. According to the method, when it is detected that the first application is switched to the background state, the electronic device can determine that the first application does not need to display an image and does not need to carry out graphic rendering, that is, it can be determined that the first application does not need to use a GPU physical memory currently. At the moment, the electronic equipment can store the first content stored in the first GPU physical memory corresponding to the first application to a disk, and can release the first GPU physical memory, so that the occupation of the GPU physical memory is reduced, the remaining available physical memory of the electronic equipment can be increased, the response speed of the electronic equipment to user operation is increased, the fluency of the system is improved, and the user experience is improved. And user experience is improved.

The embodiment of the invention discloses a thread priority adjustment method and related equipment which are applied to electronic equipment, and the electronic equipment runs a first application. A first process of the first application comprises a plurality of first threads; identifying an associated thread of the first thread from the threads of the second process; the second process is a process which is operated by the electronic equipment, except the first process and the resident process and provides service for the first application; when it is detected that the running state of the first application is changed, the priority of the first thread is adjusted, the priority of the associated thread is adjusted, and the priority adjustment trend of the associated thread is consistent with the priority adjustment trend of the first thread. By adopting the embodiment of the invention, the response speed and performance of the system can be improved, and the user experience is improved.

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

Computer devices and management methods are provided. In an implementation, a computer device includes a subrack common component and a plurality of service nodes, wherein each of the plurality of service nodes comprises a baseboard management controller (BMC connected to the subrack common component and configured to manage the subrack common component when being in a primary status.

The invention discloses an agent context management system and device based on importance sampling, and belongs to the technical field of artificial intelligence and agents, the agent context management system and device based on importance sampling comprise a global context manager used for maintaining and managing eight types of context information; the task stack manager is used for receiving a new request and performing task splitting; and the recursive execution engine is used for executing the task in a recursive mode and controlling the recursive depth. Eight types of context information are maintained through a global context manager, splitting and storage of complex tasks are achieved through a task stack manager, a recursive execution engine provides an efficient task execution mechanism and controls the recursive depth, an importance sampler selects related contexts based on a joint probability model, and the task execution efficiency is improved. And the context compressor combines the sampling fragments into a final context, and the task scheduler coordinates the working process of each component, so that a complete agent collaborative context management system is constructed.

The invention provides a frozen screen processing method and electronic equipment. The first component can be displayed on a screen of the electronic device. The first component has the ability to respond to a first operation. When a first operation on the first component is detected, the electronic device may detect whether the first component responds to the first operation. If the first component does not respond to the first operation, the electronic device can redraw the first component on the screen. According to the method, whether the frozen screen occurs in the electronic equipment or not can be detected according to whether the component displayed on the screen responds to the user operation or not, and when the frozen screen occurs in the electronic equipment, the component required to be used by the user is quickly recovered and responded by locally redrawing the component, so that the frozen screen problem is quickly solved, and the waiting time of the user is shortened.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, one or more circuit elements trigger saving of architecture state information of at least one PE to at least one memory prior to the at least one PE transitioning from a first state to a second state and triggering restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

The invention provides a target object control method and device, electronic equipment, a medium and a product, and relates to the technical field of intelligent robots, a target object comprises dual-core heterogeneous processors, instruction sets and / or operating systems corresponding to the dual-core heterogeneous processors are different, and the dual-core heterogeneous processors share hardware resources; the method comprises the steps that in the starting process of any subsystem in an operating system of a target object, the running state of the dual-core heterogeneous processor is detected; in the embodiment of the invention, under the condition that the running state is determined to be abnormal, the information of the currently running task of the dual-core heterogeneous processor is stored, and the operating system of the target object is restarted based on the task information, so that the task is quickly recovered when the operating system has a problem, the task can be continuously executed from an interruption point after restarting, and the downtime is reduced.

Techniques are provided for backing up virtual machines from a computing environment to a storage environment. A virtual machine agent is utilized to generate a snapshot of the virtual machine. Metadata comprising a snapshot identifier of the snapshot and virtual disk information of virtual disks captured by snapshot is generated at the computing environment. The metadata is retrieved and used to create a metafile that is transferred to the storage environment within which snapshots of the virtual machine are to be stored. The snapshot is retrieved from the computing environment and is packaged into a snapshot package having a protocol format used by the storage environment. The snapshot package is transferred to the storage environment.

Techniques are provided to enable mid-thread (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Hardware based mid-thread preemption is facilitated using the thread dispatch hardware of the graphics processor to trigger execution of a kernel program by the graphics processor that saves the thread state of preempted processing resources and facilitates the subsequent restoration of that thread state to the same or a different set of processing resources.

Techniques are provided for backing up virtual machines from a computing environment to a storage environment. A virtual machine agent is utilized to generate a snapshot of the virtual machine. Metadata comprising a snapshot identifier of the snapshot and virtual disk information of virtual disks captured by snapshot is generated at the computing environment. The metadata is retrieved and used to create a metafile that is transferred to the storage environment within which snapshots of the virtual machine are to be stored. The snapshot is retrieved from the computing environment and is packaged into a snapshot package having a protocol format used by the storage environment. The snapshot package is transferred to the storage environment.

One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task.

Techniques are disclosed for capturing information surrounding a user's interactions with an application for enriching application context to be used by a digital assistant for supporting the user's interactions. In one aspect, a method includes detecting an event from a client device, where the event is associated with a user's interaction with an application on the client device. In response to detecting the event, application context is obtained for the application. The obtaining includes accessing the application context from a data store based on an identifier. A first generative artificial intelligence model can then be used to generate a list having an executable action based on the event and the application context. An execution plan is then created and executed, which includes executing the executable action using an asset to obtain an output. The output or a communication derived from the output is sent to the client device.

In a microprocessor having an instruction execution unit and first and second sets of process execution resources, context information for a process next-to-be-executed by the instruction execution unit is loaded into a register file, translation lookaside buffer and first-level data cache of the first set of process execution resources during a first interval. During the first interval and concurrently with the loading of context information for the process next-to-be executed, the instruction execution unit executes a current process, including accessing context information for the current process within the register file, translation lookaside buffer and first-level data cache of the second set of process execution resources.

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, techniques involve triggering, via one or more circuit elements, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; and triggering, via the one or more circuit elements, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

Described herein is a technique to enable hardware driven checkpointing within an accelerator device without requiring explicit host software intervention to generate the checkpoint. One embodiment provides an accelerator device comprising a memory interconnect, a plurality of accelerator cores, and a scheduler coupled with the plurality of accelerator cores. The scheduler is configured to receive an checkpoint creation job to cause generation of a compressed checkpoint for a training operation executed via the plurality of accelerator cores, atomically create a compressed checkpoint for at least a portion of the training operation, and store the compressed checkpoint to checkpoint storage associated with the accelerator device.

The invention provides a learning machine voice instruction interaction method and system, is applied to the technical field of learning machines, and realizes fine management of help seeking of a user by starting an independent'temporary session state record 'for each knowledge point. By generating'multi-level guide prompts' and'multi-level question exploration ', the system can gradually guide the user to think instead of directly giving answers, so that not only is the independent thinking ability of the user cultivated, but also the system can more accurately judge the real mastering degree of the user on the knowledge point. When the user answers correctly, the system confirms the mastering of the user; and when the answer is incorrect, the system adjusts an auxiliary strategy, such as recommending a teaching video, so that more targeted help is provided. Therefore, according to the method provided by the invention, false triggering of dependence intervention caused by multi-user sharing can be avoided, the accuracy and individuation of an auxiliary strategy of the learning machine are ensured, and the user experience and learning efficiency are remarkably improved.

An apparatus comprises exception return state register storage, and processing circuitry. In response to a guarded control stack (GCS) exception return state push instruction, the processing circuitry obtains exception return state information from the exception return state register storage and push the state information to a GCS data structure. In response to a GCS exception return state pop instruction, the processing circuitry obtains GCS-protected exception return state information from the GCS data structure. In at least one operating state, the processing circuitry detects, in response to an attempt to modify the exception return state information stored in the exception return state register storage, whether an exception return state lock parameter is in a locked state or an unlocked state, and signals a fault when it is in the locked state.

Described herein is a technique to enable hardware driven checkpointing within an accelerator device without requiring explicit host software intervention to generate the checkpoint. One embodiment provides an accelerator device comprising a memory interconnect, a plurality of accelerator cores, and a scheduler coupled with the plurality of accelerator cores. The scheduler is configured to receive an checkpoint creation job to cause generation of a compressed checkpoint for a training operation executed via the plurality of accelerator cores, atomically create a compressed checkpoint for at least a portion of the training operation, and store the compressed checkpoint to checkpoint storage associated with the accelerator device.

The present disclosure relates to a method for configuring a relay register module, including: receiving a start allocation request for at least one task sent by a task scheduler; determining, based on the start allocation request, a number of relay registers to be allocated to each task of the at least one task; allocating the corresponding number of relay registers to each task; and sending a wake-up signal to the task scheduler in a case where the allocation is completed, the wake-up signal is used by the task scheduler to start a task to which relay registers are allocated; wherein the relay register module is configured to store an intermediate result obtained from an operation based on an instruction of the task. The present disclosure further relates to an apparatus for configuring a relay register module.

Certain aspects of the present disclosure provide techniques for hardware¬ based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, one or more circuit elements trigger saving of architecture state information of at least one PE to at least one memory prior to the at least one PE transitioning from a first state to a second state and triggering restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.

Techniques are provided for orchestrating operations between a storage environment and a computing environment hosting virtual machines. A virtual machine proxy, associated with a computing environment hosting a virtual machine, is accessed by an orchestrator to identify the virtual machine and properties of the virtual machine. A storage proxy, associated with a storage environment comprising a volume within which snapshots of the virtual machine are to be stored, is accessed by the orchestrator to initialize a backup procedure. The orchestrator utilizes the virtual machine proxy to create a snapshot of the virtual machine. The orchestrator utilizes the storage proxy to back up the snapshot to the volume using the backup procedure.

Approaches presented herein provide for the management of resources to be used to process a request, such as may involve orchestration of nodes for an inference request. Upon receiving an inference request, an orchestrator can determine a sequence of context nodes and inference nodes to be used to process the inference request, based in part upon a determined class of inferencing to be performed. The orchestrator can append metadata to the inference request that identifies the sequence, and can transmit the appended request to one or more first nodes in the sequence. If the nodes have a network programmable device, or similar capability, the request can be forwarded to the nodes in sequence without having to go back to the orchestrator between nodes.

The invention discloses a data interaction method and device, a storage medium and electronic equipment, and relates to the technical field of computer storage, the data interaction method comprises the steps that a user mode thread group is created, and the user mode thread group comprises an equipment interaction thread and M request processing threads, the device interaction thread is a unique thread allowing interaction with the storage device by calling the user mode execution thread; in response to a received first service instruction, converting the first service instruction into a first data interaction request, and allocating the first data interaction request to a first request processing thread in the M request processing threads; submitting the first data interaction request to an equipment interaction thread through a first request processing thread; the user mode execution thread is called through the device interaction thread, and the first data interaction request is sent to the first storage device, so that the first storage device executes the corresponding first data interaction operation, and the technical problems of low efficiency and performance waste existing in a data interaction method in related technologies are solved.

A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture / shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.

For an application having a software portion for implementation in a data processing engine array (DPE) of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation process is executed on the hardware portion using a processor executing a hardware compiler based on an interface block plan, wherein the interface block plan maps logic resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to design specifications not being met during the implementation process, interface block constraints are provided from the hardware compiler to the DPE compiler. In response to receiving the interface block constraints, an updated interface block plan is generated using the processor executing the DPE compiler and provided from the DPE compiler to the hardware compiler.