Method, apparatus and computer program product for efficient per thread performance information

Abstract

A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, remains consistent despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent way to update performance counts.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention relates to performance monitoring of a computer system or of some aspect of a computer system, such as a processor or memory or software running on the system, and, more particularly, to managing counters for such performance monitoring.[0003]2. Related Art[0004]According to the IBM AIX operating system, a performance monitor function of the operating system (“OS”) services a performance monitoring API. This servicing includes accessing 64-bit performance monitoring accumulators. (The AIX operating system is a product of, and “AIX” is a trademark of, International Business Machines Corporation.) The accesses to the accumulators are by means of operations in the “system” state since the accumulators are conventionally located in system memory. The Power and PowerPC processor architectures provide a set of 32-bit performance monitor counters. These counters are registers on the Power and PowerPC processors. (Power an...

AI Technical Summary

Benefits of technology

[0008]The foregoing problem is addressed in the present invention. Since the 32-bit performance monitoring counters are hardware registers on the processor they are accessible in the “user” state, which involves less sample time overhead. However, according to the present convention, as described above, the 32-bit counters are constantly being reset in connection with thread switches to avoid overflow and counter interaction. The invention involves a recognition of the usefulness of reading the 32-bit counters directly despite the fact that their values are conventionally corrupted by resetting with each thread switch. The invention provides a way to use the accumulators and the 32-bit counters in a manner that permits the counters to be accessed more directly for performance measurement and that overcomes the complications of thread switching, counter resetting, overflow and interaction.

[0009]According to one form of the invention, a value in a performance monitoring counter register on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in a performance monitoring accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator (instead of resetting the counter value). In this way, a performance monitoring counter register may be read, and its value, for the first thread, for example, provides a coherent meaning relative to a previous value for the same thread, despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent means for updating performance counts. Moreover, the value is saved in the accumulator in a manner consistent with the conventional accumulator format so that a larger accumulated value for the measured value can still be read using the conventional performance monitoring API.

Problems solved by technology

Unfortunately, the overhead for invoking the system state involves perhaps thousands of instructions.

However, the above described arrangement does not provide consistent measurement overhead.

Thus, the previously known arrangement for measuring performance of short-duration events is problematic.

Images