The application provides a
hybrid structure analog-to-
digital converter, belonging to the technical field of
integrated circuit design, comprising a 7 bit first-order feed-forward incremental
delta sigma ADC and an 8 bit single-stage cyclic ADC. The incremental
delta sigma ADC adopts a first-order feed-forward structure, so that an input
signal is directly fed to a
comparator input end for comparison without passing through a modulator loop, thereby reducing the influence of non-ideal factors in the modulator loop on the input
signal. In addition, the input end of the
comparator is reset to a common mode level when the
comparator is not working, so as to eliminate the influence of inconsistent
voltage changes of two input ends of the comparator caused by incomplete matching of a
layout wiring of the comparator input end on the circuit, and improve the overall
signal-to-
noise ratio of the circuit. By using the
hybrid structure analog-to-
digital converter provided by the application, the signal-to-
noise ratio and the conversion speed are improved, and the conversion time is reduced without adding additional circuits.