120 results about "Fpga acceleration" patented technology

The invention discloses a firmware updating method, device and medium of an FPGA accelerator card. The method comprises the steps that a configuration list is read in a script execution mode so that adevice address where the FPGA accelerator card to be updated is located can be acquired; updating firmware of the FPGA accelerator card is acquired, and the FPGA accelerator card is found through thedevice address so that the updating firmware can be burnt into the FPGA accelerator card; the updating firmware is loaded so that the FPGA accelerator card can be updated. Compared with an artificialmode that the updating firmware is burnt to the FPDG accelerator card one by one, the firmware updating method achieves automatic corresponding updating of the FPGA accelerator card by a system through script running, so that the problem of relatively low artificial updating efficiency due to a large quantity of FPGA accelerator cards in a complex network device environment is solved, the error probability due to difference among updating firmware of numerous FPGA accelerator cards in artificial updating is lowered, and high availability of the FPGA accelerator cards is guaranteed. Furthermore, the invention further provides the firmware updating device and medium of the FPGA accelerator card. The firmware updating device and medium of the FPGA accelerator card also have the advantages.

The invention discloses a CNN acceleration method and system based on OPU, and relates to the field of CNN acceleration methods based on FPGA. The method includes that an OPU instruction set is defined; the compiler converts the CNN definition files of different target networks, selects an optimal accelerator to configure mapping according to the defined OPU instruction set, and generates instructions of different target networks to complete mapping; the OPU reads the compiled instruction, operates the instruction according to a parallel computing mode defined by the OPU instruction set, and completes acceleration of different target networks. According to the method, the instruction type is defined, the instruction granularity is set, network recombination optimization is carried out, a mapping mode for guaranteeing the maximum throughput is obtained by searching a solution space, and hardware adopts a parallel computing mode; the problem that an existing FPGA acceleration work aims at generating specific independent accelerators for different CNNs is solved, and the effects that the FPGA accelerator is not reconstructed, and acceleration of different network configurations is rapidly achieved through instructions are achieved.

The invention discloses a Hadoop heterogeneity method and system based on storage and acceleration optimization, and belongs to the field of distributed calculation. According to the technical scheme, aiming at data processing requirements, a storage medium is divided into three types, including a solid storage medium, a common storage medium and a high-density storage medium, and the most appropriate storage mode is found for data of different types; meanwhile, an acceleration application of which calculation performance needs to be improved is positioned to an FPGA accelerator with a specific algorithm or a GPU accelerator to complete calculation so as to improve processing performance of the application, and algorithm functions and layouts of the FPGA and GPU accelerator can be statically switched. The invention further discloses the Hadoop heterogeneity system based on the storage and acceleration optimization. According to the Hadoop heterogeneity method and system based on the storage and acceleration optimization, reading and writing performance of a whole cluster and execution performance of an application task and the resource utilization rate of an acceleration device are improved.

Computing systems with conventional CPUs coupled to co-processors or accelerators implemented in FPGAs (Field Programmable Gate Arrays). One embodiment of the systems and methods according to the invention includes a FPGA accelerator implemented in a computer system by providing an adapter board configured to be used in a standard CPU socket.

The invention discloses an intrusion prevention system and method. The intrusion prevention system comprises a data packet capture module, a data pack analysis module, a matching filter module, an FPGA (field programmable gate array) acceleration platform and a feature learning module; the data packet capture module is responsible for capturing and storing data packets entering a host; the data packet analysis module is used for analyzing and reorganizing the data packets captured by the data packet capture module; the matching filter module is used for matching and filtering the data packetscaptured in a matching filter through a matching filter algorithm; the FPGA acceleration platform is used for accelerating data by the aid of an FPGA calculation system and execution speed in algorithm of a packet classification module, the matching filter module and a neural training module; the feature learning module is used for performing neutral training on the data subjected to matching filter by the aid of a neutral network algorithm embedded in the FPGA acceleration platform. By the above principle, high calculation capability is achieved, intrusion behaviors can be detected in time before occurrence of the intrusion behaviors, misinformation and false report cannot happen, prevention effect is good, and the intrusion prevention system and method is quite suitable for intrusion prevention of big data.

The invention discloses a whole genome sequencing data calculation interpretation method, which comprises the following implementation steps that: inputting reference whole genome data used for whole genome sequencing and organic sequencing sample data, and carrying out preprocessing; calling an FPGA (Field Programmable Gate Array) by a CPU (Central Processing Unit) to be accelerated to compare sequencing sample reliable data with the reference whole genome data with an index to obtain a comparison result with a repeated sign and the index; calling the FPGA and a GPU (Graphics Processing Unit) by the CPU to be accelerated to carry out genome reassembling on the sequencing sample reliable data, and carrying out variant identification recognition on the comparison result with the repeated label and the index; and calling the GPU and a DSP (Digital Signal Processor) by the CPU to be accelerated to carry out visual processing, and calling a deep learning model realized by hardware on the FPGA by the CPU to carry out the analysis and the mining of the whole genome and a variant function on the basis of a visual processing result. By use of the method, the GPU, DSP and FPGA processors can be comprehensively utilized for acceleration, and the method has the advantages of being quick, real-time, accurate in penetration, popular and easy in understanding and varied in forms.

The invention provides an FPGA cloud platform acceleration resource allocation method and system. According to the invention, accelerator card resources are allocated and coordinated according to thetime delay between a user host and a FPGA accelerator card deployed in each network segment; when the user applies for using the FPGA, the FPGA acceleration card with the minimum delay with the host in the FPGA resource pool is allocated to the user, thereby realizing allocation of acceleration resources of the FPGA cloud platform; a cloud monitoring management platform can obtain the transmissiondelay with a virtual machine network according to different geographic positions of the FPGA board cards in the FPGA resource pool, , and can allocate the board card with the minimum delay to each user for use; in addition, unauthorized users can be effectively prevented from randomly accessing the acceleration resources in the resource pool, and the effective rights and interests of a resource pool owner are protected. According to the method and the device, the FPGA acceleration card which is not authorized to be used by the user is effectively protected, the network delay of the board cardallocated to the user can be ensured to be minimum, the optimal acceleration effect is achieved, and the user experience is improved.

The invention discloses a data acceleration operation processing method and device and a computer readable storage medium. The method comprises the following steps that: a storage server applies for an input cache space and an output cache space in advance by utilizing a memory management module, and meanwhile, transmits the initial address of each memory page of the input cache space and the output cache space to a direct memory access descriptor table, wherein the input cache space stores IO original data corresponding to a user data request , and the output cache space stores a data processing result obtained after the IO original data is subjected to accelerated operation; an FPGA acceleration card receives a data acceleration operation request and transfers the IO original data to thelocal from the input cache space through the direct memory access descriptor table to subject the IO original data to accelerated operation processing, and transfers a data processing result to the output cache space through the direct memory access descriptor table; and therefore, memory copying can be avoided while the FPGA acceleration card is used for carrying out data processing on the storage server, and the performance loss of the storage server in the acceleration process is effectively reduced.

The invention discloses a method and a device for power supply control of a FPGA accelerator card auxiliary power supply, and a medium. The steps of the method comprises: establishing a first power supply access between an auxiliary power interface and a FPGA, and a second power supply access between an auxiliary power interface and a preset component; obtaining current operation power consumptionof the FPGA, and using a preset control standard as basis, obtaining a power supply group state which meets the operation power consumption; according to the power supply group state, controlling on-off of each power supply in the power supply group, to supply power for the FPGA using the auxiliary power interface; determining whether the state of the main power interface supplying power to the preset component is a preset state, if yes, using the auxiliary power interface to supply power for the preset component. An auxiliary power supply is relatively reasonably and flexibly used, and safety operation of each component and integrated working efficiency are guaranteed. In addition, the invention also provides a device for power supply control of a FPGA accelerator card auxiliary power supply, and a medium, and beneficial effects are as described above.