57 results about "Fpga acceleration" patented technology

The invention relates to the technical field of electrical equipment analysis, and particularly discloses an electrical equipment operation state monitoring system and method, and the method comprises the steps: the system is deployed at an electrical equipment site, integrates a low-power-consumption processor and an FPGA acceleration module, and is used for collecting multi-source data in real time, and executing lightweight model calculation and local early warning; and storing full data and operating a global analysis model, and communicating with the edge computing node to realize data collaborative analysis. According to the electrical equipment operation state monitoring system and method provided by the embodiment of the invention, through edge computing lightweight deployment, data preprocessing and local early warning are completed on the equipment site, and high efficiency of monitoring response and low-power-consumption hardware adaptation are realized; by means of an electromagnetic interference dynamic evaluation module, an acquisition strategy is intelligently adjusted, noise is suppressed, the reliability of multi-source data is guaranteed, the efficiency, precision and intelligent capability of electrical equipment state monitoring are remarkably improved, and technical support is provided for reliable operation of power system equipment.

The invention relates to the technical field of pipeline safety monitoring, in particular to a pipeline water leakage detection platform and method.The pipeline water leakage detection platform comprises a sensor layer, an edge calculation module and a pipeline water leakage detection system of a cloud analysis platform, the sensor layer comprises a pressure sensor, a sonic sensor, a flow sensor and an environment sensor, and a distributed installation structure is adopted; the edge calculation module is used for collecting pipeline state data in real time, the edge calculation module comprises an equipment box, a built-in power supply module, a data processor (ARM Cortex-M series + FPGA acceleration unit) and a communication module (NB-IoT or LoRa), and sensor data is subjected to localization preprocessing and then uploaded to a cloud analysis platform. A cascade neural network model (CNN + LSTM) and a leakage positioning engine are deployed on the cloud platform, leakage judgment and accurate positioning are achieved through multi-source data fusion and a deep learning algorithm, and efficient and accurate pipeline leakage detection and positioning are achieved through data collection of a sensor layer, preprocessing of an edge calculation module and intelligent analysis of the cloud platform.

The invention provides an AI reasoning optimization method and system for a dynamic model switching framework for edge equipment, and relates to the technical field of AI optimization, and the method comprises the steps: training a quantization compensation model through federated learning to correct a quantization error; constructing a hierarchical heterogeneous resource management system to realize multi-core collaborative scheduling; the compensation parameters are integrated to an FPGA acceleration circuit, and an intelligent power consumption equalization technology is adopted; and constructing a dynamic decision engine by using the graph neural network to trigger model switching. According to the invention, the balance between high-precision AI reasoning and low-power consumption requirements on the edge equipment is realized, the utilization efficiency of computing resources is improved, and the energy consumption is reduced.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention relates to the field of artificial intelligence cross-modal retrieval, and provides a video text cross-modal retrieval method and system based on spatio-temporal feature fusion. The method comprises the following steps: carrying out key frame sampling and time sequence partitioning on an input video, extracting static visual features through a spatial feature network, and extracting motion features through a time dynamic network; a self-adaptive gating fusion module is adopted to dynamically calculate spatial-temporal feature weights and perform weighted fusion; extracting text semantic features by using a pre-training language model; constructing a double-flow projection network to map video fusion features and text features to a unified measurement space, and optimizing a feature distance by adopting a contrast loss function containing difficult negative sample mining and intra-modal constraint; and outputting a retrieval result according to the cosine similarity sequence. The system comprises four units, wherein the gating fusion module is integrated with an FPGA acceleration circuit. According to the method, mAP (at) 10 is equal to 0.78 in a UCF-101 data set, the time sequence action retrieval accuracy rate is 92.8%, and the single video retrieval delay is 23 milliseconds.

Disclosed in the present invention are an FPGA acceleration-based graph neural network explanation method and device, which use FPGA hardware to perform parallel acceleration on the explanation process of a node classification-oriented graph neural network and improve the node traversing and shortest path searching process of BFS, thereby optimizing the requirements of algorithm calculation and storage and accelerating the generation of an explanation result. According to the present invention, in the HN value calculation process, matrix characteristics are used to perform optimization processing on multiplication operation to convert dense matrix multiplication into sparse-dense matrix multiplication, and multi-PE parallel processing is used to optimize resource occupation, thereby greatly improving the performance of graph neural network explanation acceleration. In addition, an overall architecture that calculates and distributes tasks on the basis of FIFO storage is designed to reduce calculation differences between nodes, solving the problem of high time complexity of a node classification-based graph neural network explanation method in actual data application, and improving the time efficiency of explanations.

The invention discloses an internal combustion engine in-cylinder transient self-adaptive exposure control method based on FPGA acceleration, and belongs to the technical field of internal combustion engine endoscopic visualization. In order to solve the technical problem of image overexposure or underexposure caused by violent illumination change in the combustion process in an internal combustion engine cylinder, a real-time exposure detection unit is fused with a camera built-in sensor and an endoscope added sensor to monitor light intensity data; the adaptive exposure control unit accelerated by the FPGA adopts adaptive PID control and fuzzy logic control to generate a parameter adjustment direction, the adaptive PID dynamically adjusts gain based on a machine learning model, and the fuzzy logic outputs a decision according to a fuzzy rule base of brightness, light intensity and errors; the parameter adjusting unit adjusts the aperture size, the shutter speed and the light sensitivity in a linkage mode according to the target and actual gray scale difference value, and millisecond-level multi-parameter exposure control is achieved. Overexposure of a highlight area and loss of details of a low-light area are effectively avoided, and stable and clear images are obtained in the whole combustion process.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The application discloses a kind of parallel computing methods of FPGA acceleration for Key-Value storage system, method includes: triggering compaction operation, the SSTable of key range repetition is transferred to FPGA memory;Using FPGA parallel decoding and sorting these SSTable, obtain ordered and non-repeated key-value pair set;Using FPGA parallel coding this set, form new SSTable, and these SSTable are directly written from FPGA memory to SSD, bypass CPU, and the invalid key-value pair in log file is recycled by parallel garbage collection operation.The application parallel computing method of FPGA acceleration for Key-Value storage system, using key-value separation method reduces the write amplification problem of key-value storage, and provides comprehensive optimization for the calculation load and data transmission delay in key-value storage, reduces the pressure of CPU.

The invention provides a low-coupling Transform target detection method and system based on FPGA (Field Programmable Gate Array) acceleration. The method comprises the following steps: constructing a Transform target detection network model based on a low-coupling optimization method; and constructing a multi-framework universal FPGA accelerator based on a Winograd fast algorithm, wherein the multi-framework universal FPGA accelerator is used for simultaneously supporting a convolutional neural network used for feature extraction and a Transform codec based on a multi-head attention mechanism in the Transform target detection network model. According to the method, an efficient memory access transformation scheme is provided for the special type of operators, so that the accelerator obtains higher convolution operation performance while having high calculation efficiency for all the operators; a high-precision approximation scheme and corresponding data flow optimization are provided for various special functions contained in an attention mechanism, a difference fitting method is provided for GELU, approximation precision is improved, attention scaling operation and Softmax operator are fused, and scaling operation overhead during operation is saved.

The present invention relates to a high-quality HDR image generation system, which includes an image input module, an FPGA acceleration module, and an optimized segmentation edge module; the image input module inputs an image into the FPGA acceleration module for acceleration processing to obtain an HDR image; the HDR image is passed through the optimized segmentation edge module to remove the edge distortion effect, and the final high-quality HDR image is obtained. The present invention solves the problem that local saturation is too high while local saturation is insufficient when the whole picture is processed.

The invention relates to a YOLOv10 in-orbit remote sensing image target detection network optimization method and an FPGA acceleration system, and belongs to the technical field of neural network acceleration. According to the optimization method, a C2f-Faster network module is used for replacing a C2f module to reduce the calculation amount, a Leaky ReLU activation function is used for optimizing the network efficiency, rapid normalization fusion is used for improving the small target detection precision, a convolution layer and a BN layer are fused for weight square quantization, and the hardware acceleration efficiency is further improved. The acceleration system comprises an AXI Bus module, an Initializer module, a Merger module, a YOLO Subsystem module, a Fetcher module and the like which are realized on a single-chip FPGA (Field Programmable Gate Array), and an external DDR3 (Double Data Rate 3) memory. Through network optimization and FPGA acceleration, YOLOv10 in-orbit remote sensing image target detection precision and speed are effectively improved, power consumption is reduced, and the method is suitable for deployment of embedded and low-power-consumption equipment.

A data processing method, a data processing apparatus, a distributed data flow programming framework, an electronic device, and a storage medium. The data processing method includes: dividing a data processing task into a plurality of data processing subtasks (S101); determining, in a Field Programmable Gate Array (FPGA) accelerator side, a target FPGA acceleration board corresponding to each of the data processing subtasks (S102); and sending data to be computed to the target FPGA acceleration board, and executing the corresponding data processing subtask by use of each of the target FPGA acceleration boards to obtain a data processing result (S103). According to the method, a physical limitation of host interfaces on the number of FPGA acceleration boards in an FPGA accelerator side may be avoided, thereby improving the data processing efficiency.

The invention discloses a distributed node collaborative elastic scheduling and cloud rendering splicing method and system. The method comprises the following steps: constructing a distributed node cluster supporting FPGA acceleration; node resources and network states are monitored and predicted in real time; rendering tasks are flexibly scheduled and migrated based on a prediction result; signal preprocessing is completed at an edge node, and rendering and splicing are completed at a cloud node; and finally outputting to a control system. The system comprises a node cluster used for executing the steps, a scheduling engine and a splicing assembly line. Through distributed cooperation and intelligent elastic scheduling, efficient and low-delay cloud rendering and splicing processing is realized, and the resource utilization rate and the system reliability are effectively improved.

A method and device for interpreting a graph neural network based on FPGA acceleration propose to use FPGA hardware to accelerate interpretation process of the graph neural network oriented to node classification in parallel, and improve node traversal and shortest path search of BFS, thereby optimizing requirements of algorithm calculation and storage, and accelerating generation of interpretation results. During calculating HN values, the present disclosure optimizes multiplication operation using the matrix characteristics, transforms the dense matrix multiplication into sparse-dense matrix multiplication, and optimizes the resource occupation using multi-PE parallel processing, greatly improving performance of graph neural network interpretation acceleration. Moreover, an overall architecture based on FIFO storage calculation task distribution is designed to reduce calculation difference between nodes, solving the difficulty of high time complexity of the graph neural network interpretation method based on node classification in actual data applications and improving the time efficiency of interpretation.

The application discloses a quantum computing data processing method and device and a storage medium, comprising: collecting real-time data of an application scene by a terminal device, and transmitting the real-time data to an edge processing node cluster; using an FPGA acceleration module integrated in the edge processing node cluster to perform a processing operation on the real-time data to generate a quantum data packet, wherein the processing operation comprises preprocessing, quantumization coding and data routing, and the edge processing node cluster sends the quantum data packet and a corresponding task request to a quantum computing center; constructing a quantum service blockchain network for analyzing and identifying the task request, and dynamically calling, combining and deploying the corresponding quantum service; constructing a quantum computing model, using the quantum service to realize optimized calculation on the task request; and transmitting the optimized calculation result generated by the quantum computing center to the edge processing node cluster through a quantum encryption transmission channel, and driving the terminal device to execute by the edge processing node cluster.

The application provides a PCIe link monitoring and self-repair system for an FPGA acceleration card, and the system comprises: a signal acquisition module having a main sampler anchored at a central sampling point and an offset sampler capable of biased sampling; a monitoring point calibration module for controlling the offset sampler to scan along a voltage axis and a time axis after the link is ready, determining an eye diagram boundary and calculating a monitoring sampling point; an online monitoring module for polling each monitoring point and interrupting when an error code exceeds a limit, and outputting a repair trigger signal; a repair decision module for determining a distortion type according to an abnormal point position and outputting a coding signal; and a parameter adjustment module for selecting a target equalizer according to the coding signal, and performing adaptive iterative adjustment with the monitoring result as feedback until the link returns to normal. The application realizes real-time monitoring, rapid diagnosis and closed-loop self-repair of the PCIe link signal under the premise of uninterrupted service, and significantly improves the stability and reliability of the system.

This invention proposes a visual Transformer neural network acceleration system and method based on CPU and FPGA. The method's implementation steps are as follows: an embedding module constructs a feature matrix; a preprocessing module preprocesses the feature matrix and weight matrix; the preprocessed feature matrix and weight matrix are moved and cached; an acceleration unit constructs a self-attention matrix; the self-attention matrix is ​​cached and moved; a post-processing unit constructs a global feature matrix; and an MLP Head module obtains the classification result. The preprocessing module in the CPU reduces the additional data processing time of the FPGA acceleration unit by preprocessing the feature matrix and weight matrix, effectively improving the neural network's computation speed. Simultaneously, the normalization operation module in the acceleration unit utilizes exponential and logarithmic approximation results during approximation calculations, eliminating floating-point exponentiation and division operations, effectively reducing hardware resource consumption.

The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, which relates to the technical field of FPGA acceleration methods. The method includes adopting a dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bits are stored in a two's complement format; the mantissa bit represents the valid floating-point data, hiding the high-order bit 1; and the bit widths of the exponent and mantissa bits can be customized. The exponent and mantissa bit widths of the dspfloat provided by the present invention can be customized, avoiding the defects of insufficient precision of the float data type and excessive bit width of the double data type. While ensuring the precision required by the application, the method achieves a higher frequency, reduces computing resource usage, and improves computing speed.

The invention belongs to the technical field of industrial data security and trusted computing, and particularly relates to an industrial data trusted computing-oriented verifiable security co-processing method and system, which comprises the following steps of: acquiring industrial data at an edge end, generating a data consanguinity map and adding a semantic tag; performing calculation task splitting on the industrial data based on a verifiable calculation mechanism to generate a calculation proof; writing the calculation proof and the data abstract into a block chain through a lightweight consensus mechanism; verifying the validity of the calculation proof at the cloud end or the chain end, and returning a verification result; and triggering a subsequent industrial control behavior or a data transaction behavior based on the verification result. According to the method, data consanguinity, zero knowledge proof and on-chain tampering prevention are achieved, data sources can be traced, the calculation process can be verified, and operation behaviors cannot be repudiated. Meanwhile, PBFT consensus and FPGA acceleration are adopted, so that the whole link of collection, proving, consensus, verification and control is lt; and the real-time requirements of motion control and quality closed loop are met.

The invention discloses a multi-device cooperation system for a conference system, and relates to the technical field of comprehensive communication, the multi-device cooperation system comprises an application layer, a core abstraction layer, a driving layer, a kernel layer and a hardware layer, the application layer operates conference application software, the core abstraction layer is a unified hardware abstraction interface layer, and provides a standardized device interface for the application layer; the driving layer and the kernel layer provide hardware driving, a dynamic priority allocation algorithm, an interrupt response and memory sharing mechanism and CPU / co-processing resource scheduling, and the hardware layer comprises a camera, a microphone, a sound box and an FPGA acceleration chip; the method has the advantages that multi-thread communication delay is effectively reduced, system fluency is guaranteed, multi-device cooperation efficiency of the conference machine in a real-time video cooperation scene is improved, high-resolution video streams and low-delay audio transmission are supported, and audio and picture synchronization errors are reduced.

The application discloses a kind of FPGA acceleration card power consumption test method, device and electronic equipment, the method includes: based on CPLD receiving the first instruction sent by BMC, first instruction at least includes modification instruction and target voltage value;According to modification instruction and target voltage value, modify the on-board voltage value of FPGA acceleration card;Based on the second instruction sent by BMC, second instruction at least includes save effective instruction;According to second instruction, save current on-board voltage value and make it effective;Based on current on-board voltage value, upgrade the firmware of FPGA acceleration card and execute power consumption stress test;By BMC and the CPLD of FPGA acceleration card are interacted to realize the modification on-board voltage value of FPGA acceleration card, then high-power consumption version of FW corresponding voltage value is burned again to carry out high-power consumption test, and the test scene of FPGA acceleration card is enriched, and the stability of FPGA acceleration card is ensured.

This invention provides a dynamic model switching framework for AI inference optimization methods and systems on edge devices, relating to the field of AI optimization technology. The methods include: correcting quantization errors by training a quantization compensation model through federated learning; constructing a hierarchical heterogeneous resource management system to achieve multi-core collaborative scheduling; integrating compensation parameters into FPGA acceleration circuits and employing intelligent power balancing technology; and utilizing graph neural networks to construct a dynamic decision engine to trigger model switching. This invention achieves a balance between high-precision AI inference and low-power consumption requirements on edge devices, improving computing resource utilization efficiency and reducing energy consumption.

The invention provides an FPGA (Field Programmable Gate Array) cluster acceleration system and a reconfiguration method. The system comprises a control terminal, an Ethernet switch and a plurality of FPGA acceleration cards under a server node, the control terminal is in communication connection with the server node based on the Ethernet switch; each FPGA acceleration card is in communication connection with the server node based on an Ethernet interface; the control terminal is used for generating a reconfiguration data packet and sending the reconfiguration data packet to each FPGA acceleration card under the server node based on the Ethernet switch; and each FPGA accelerator card is reconfigured based on the reconfiguration data packet. According to the system provided by the invention, the control terminal and the FPGA acceleration cards are connected through the Ethernet, so that when batch FPGA acceleration cards need to be reconfigured, the reconfiguration data packets are simultaneously sent to the FPGA acceleration cards through the Ethernet switch, the batch FPGA acceleration cards can be reconfigured at the same time, the reconfiguration time is greatly shortened, and the reconfiguration efficiency is improved. The method is suitable for scenes requiring high flexibility and low delay, such as cloud computing and edge computing.

The invention discloses a high-precision real-time Stewart platform forward kinematics solving method based on FPGA acceleration, which mainly solves the problems of high forward kinematics calculation complexity, low real-time performance, low precision and the like of the existing Stewart platform, and comprises the following implementation steps of: establishing a Stewart platform model and determining a working space; selecting a data set according to the truncated Gaussian distribution, and performing neural network fitting; quantifying and deploying the neural network; realizing a CORDIC sine and cosine solution, pre-calculating a Jacobian matrix, and storing the pre-calculated Jacobian matrix in an FPGA; the neural network output serves as an iteration initial value, and a positive solution pose is obtained through iteration; and carrying out positive solution acceleration through array segmentation, loop expansion and an assembly line. By introducing a low hardware resource consumption strategy, a positive solution module is deployed into the FPGA, the time consumed by one-time positive solution is less than 250 microseconds, and the positive solution pose error is less than 0.01 cm and 0.01 degree.

The invention provides an ST2110 transmission protocol processing method, device and system based on an FPGA (Field Programmable Gate Array), and solves the technical contradictions of high delay of an existing CPU (Central Processing Unit) scheme and poor flexibility of an ASIC (Application Specific Integrated Circuit) scheme. The method comprises the following steps: constructing an information classification module to distinguish a video / audio stream from an SDP / PTP message; media parameters specified by RFC 4566 are extracted through an SDP analysis module; an RTP module is adopted to execute RFC 3550 protocol packaging; iEEE 1588v2 clock synchronization is realized on the basis of double clock sources; a token bucket traffic shaping module is utilized to meet the ST2110-21 standard and compensate for clock drift. The device is realized on a Xilinx XC7K325T FPGA platform, and comprises a reconfigurable assembly line dynamic configuration RTP packaging module, a PTP synchronizing module and a shaping module; the hardware state machine drives SDP parameter analysis; and the 10G Ethernet module is integrated with ST 2110-22 VLAN (Virtual Local Area Network) priority mapping. According to the design, the FPGA is adopted for acceleration, the problem that performance and cost performance cannot be well compatible at present is solved to a certain extent, and the strict requirement for 4K ultra-high-definition video transmission is met.

The invention discloses a quantum computing data processing method and device and a storage medium, and the method comprises the steps: collecting real-time data of an application scene through terminal equipment, and transmitting the real-time data to an edge processing node cluster; an FPGA acceleration module integrated in the edge processing node cluster is utilized to carry out processing operation on the real-time data to generate a quantum data packet, the processing operation comprises preprocessing, quantization coding and data routing, and the edge processing node cluster sends the quantum data packet and a corresponding task request to a quantum computing center; constructing a quantum service block chain network for analyzing and identifying the task request, and dynamically calling, combining and deploying corresponding quantum services; constructing a quantum calculation model, and performing optimization calculation on the task request by using quantum service; and issuing an optimization calculation result generated by the quantum calculation center to the edge processing node cluster through the quantum encryption transmission channel, and driving the terminal equipment to execute by the edge processing node cluster.

The application discloses a kind of inner and outer network communication methods of PCIE link based on FPGA, comprising (1) inner network receives the communication request and configuration management information sent by external terminal and handles and forwards to inner network VPP passage node;(2) inner network VPP passage node according to protocol processing network topology, control management service and communication information and send to FPGA acceleration card with acceleration data by PCIE;(3) PCIE acceleration card based on FPGA receives and processes the communication data to be accelerated and sends to outer network VPP passage node;(4) outer network VPP passage node receives the communication data that has been accelerated and forwards to black area communication terminal.The application is in the background of red and black isolation, through PCIE high-speed equipment interconnect inner and outer network, combine the high-speed performance of VPP and DPDK, use virtual network interface TUN equipment and VETH equipment to simultaneously open the passage of inner and outer network system local, to guarantee the communication of red area and black area external terminal.In the high-speed performance of maintaining network transmission, realize the architecture communication of inner and outer network service plane and control plane.

The application provides a CPU and FPGA virtual-real combination simulation verification method and system, comprising: creating a CPU simulation model and loading a CPU-side binary executable file; deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain a test result. Through software and hardware collaborative adjustment and data caching technology, the application ensures the relative uniformity of the simulation timing, improves the reliability and correctness of the joint verification, and effectively supports the simulation deduction of the system.

The application discloses a processing method and device of pooling resources, electronic equipment and medium. The method is applied to an FPGA cloud platform. The FPGA cloud platform comprises an FPGA acceleration card, a switch, a bottom plate and a host. The bottom plate comprises a card slot, is used for inserting the FPGA acceleration card, and supplies power for the FPGA acceleration card. The switch is connected with a fiber network port of the FPGA acceleration card, is used for realizing data interaction between the FPGA acceleration cards. The host is connected with the switch, is used for sending a UDP message to the FPGA acceleration card through the switch. The FPGA acceleration card is used for receiving the UDP message sent by the switch, then analyzing the UDP message to obtain QP field information, and then inputting data to a Kernel end corresponding to the QP field information for processing. It can be seen that the method disclosed by the application realizes multiple Kernel acceleration operations on the same FPGA acceleration card, and can efficiently utilize the pooling resources.