39 results about "Fpga acceleration" patented technology

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

The invention relates to the field of artificial intelligence cross-modal retrieval, and provides a video text cross-modal retrieval method and system based on spatio-temporal feature fusion. The method comprises the following steps: carrying out key frame sampling and time sequence partitioning on an input video, extracting static visual features through a spatial feature network, and extracting motion features through a time dynamic network; a self-adaptive gating fusion module is adopted to dynamically calculate spatial-temporal feature weights and perform weighted fusion; extracting text semantic features by using a pre-training language model; constructing a double-flow projection network to map video fusion features and text features to a unified measurement space, and optimizing a feature distance by adopting a contrast loss function containing difficult negative sample mining and intra-modal constraint; and outputting a retrieval result according to the cosine similarity sequence. The system comprises four units, wherein the gating fusion module is integrated with an FPGA acceleration circuit. According to the method, mAP (at) 10 is equal to 0.78 in a UCF-101 data set, the time sequence action retrieval accuracy rate is 92.8%, and the single video retrieval delay is 23 milliseconds.

The invention discloses an internal combustion engine in-cylinder transient self-adaptive exposure control method based on FPGA acceleration, and belongs to the technical field of internal combustion engine endoscopic visualization. In order to solve the technical problem of image overexposure or underexposure caused by violent illumination change in the combustion process in an internal combustion engine cylinder, a real-time exposure detection unit is fused with a camera built-in sensor and an endoscope added sensor to monitor light intensity data; the adaptive exposure control unit accelerated by the FPGA adopts adaptive PID control and fuzzy logic control to generate a parameter adjustment direction, the adaptive PID dynamically adjusts gain based on a machine learning model, and the fuzzy logic outputs a decision according to a fuzzy rule base of brightness, light intensity and errors; the parameter adjusting unit adjusts the aperture size, the shutter speed and the light sensitivity in a linkage mode according to the target and actual gray scale difference value, and millisecond-level multi-parameter exposure control is achieved. Overexposure of a highlight area and loss of details of a low-light area are effectively avoided, and stable and clear images are obtained in the whole combustion process.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The application discloses a kind of parallel computing methods of FPGA acceleration for Key-Value storage system, method includes: triggering compaction operation, the SSTable of key range repetition is transferred to FPGA memory;Using FPGA parallel decoding and sorting these SSTable, obtain ordered and non-repeated key-value pair set;Using FPGA parallel coding this set, form new SSTable, and these SSTable are directly written from FPGA memory to SSD, bypass CPU, and the invalid key-value pair in log file is recycled by parallel garbage collection operation.The application parallel computing method of FPGA acceleration for Key-Value storage system, using key-value separation method reduces the write amplification problem of key-value storage, and provides comprehensive optimization for the calculation load and data transmission delay in key-value storage, reduces the pressure of CPU.

The invention provides a low-coupling Transform target detection method and system based on FPGA (Field Programmable Gate Array) acceleration. The method comprises the following steps: constructing a Transform target detection network model based on a low-coupling optimization method; and constructing a multi-framework universal FPGA accelerator based on a Winograd fast algorithm, wherein the multi-framework universal FPGA accelerator is used for simultaneously supporting a convolutional neural network used for feature extraction and a Transform codec based on a multi-head attention mechanism in the Transform target detection network model. According to the method, an efficient memory access transformation scheme is provided for the special type of operators, so that the accelerator obtains higher convolution operation performance while having high calculation efficiency for all the operators; a high-precision approximation scheme and corresponding data flow optimization are provided for various special functions contained in an attention mechanism, a difference fitting method is provided for GELU, approximation precision is improved, attention scaling operation and Softmax operator are fused, and scaling operation overhead during operation is saved.

The invention discloses a distributed node collaborative elastic scheduling and cloud rendering splicing method and system. The method comprises the following steps: constructing a distributed node cluster supporting FPGA acceleration; node resources and network states are monitored and predicted in real time; rendering tasks are flexibly scheduled and migrated based on a prediction result; signal preprocessing is completed at an edge node, and rendering and splicing are completed at a cloud node; and finally outputting to a control system. The system comprises a node cluster used for executing the steps, a scheduling engine and a splicing assembly line. Through distributed cooperation and intelligent elastic scheduling, efficient and low-delay cloud rendering and splicing processing is realized, and the resource utilization rate and the system reliability are effectively improved.

A method and device for interpreting a graph neural network based on FPGA acceleration propose to use FPGA hardware to accelerate interpretation process of the graph neural network oriented to node classification in parallel, and improve node traversal and shortest path search of BFS, thereby optimizing requirements of algorithm calculation and storage, and accelerating generation of interpretation results. During calculating HN values, the present disclosure optimizes multiplication operation using the matrix characteristics, transforms the dense matrix multiplication into sparse-dense matrix multiplication, and optimizes the resource occupation using multi-PE parallel processing, greatly improving performance of graph neural network interpretation acceleration. Moreover, an overall architecture based on FIFO storage calculation task distribution is designed to reduce calculation difference between nodes, solving the difficulty of high time complexity of the graph neural network interpretation method based on node classification in actual data applications and improving the time efficiency of interpretation.

The application discloses a quantum computing data processing method and device and a storage medium, comprising: collecting real-time data of an application scene by a terminal device, and transmitting the real-time data to an edge processing node cluster; using an FPGA acceleration module integrated in the edge processing node cluster to perform a processing operation on the real-time data to generate a quantum data packet, wherein the processing operation comprises preprocessing, quantumization coding and data routing, and the edge processing node cluster sends the quantum data packet and a corresponding task request to a quantum computing center; constructing a quantum service blockchain network for analyzing and identifying the task request, and dynamically calling, combining and deploying the corresponding quantum service; constructing a quantum computing model, using the quantum service to realize optimized calculation on the task request; and transmitting the optimized calculation result generated by the quantum computing center to the edge processing node cluster through a quantum encryption transmission channel, and driving the terminal device to execute by the edge processing node cluster.

The application provides a PCIe link monitoring and self-repair system for an FPGA acceleration card, and the system comprises: a signal acquisition module having a main sampler anchored at a central sampling point and an offset sampler capable of biased sampling; a monitoring point calibration module for controlling the offset sampler to scan along a voltage axis and a time axis after the link is ready, determining an eye diagram boundary and calculating a monitoring sampling point; an online monitoring module for polling each monitoring point and interrupting when an error code exceeds a limit, and outputting a repair trigger signal; a repair decision module for determining a distortion type according to an abnormal point position and outputting a coding signal; and a parameter adjustment module for selecting a target equalizer according to the coding signal, and performing adaptive iterative adjustment with the monitoring result as feedback until the link returns to normal. The application realizes real-time monitoring, rapid diagnosis and closed-loop self-repair of the PCIe link signal under the premise of uninterrupted service, and significantly improves the stability and reliability of the system.

This invention proposes a visual Transformer neural network acceleration system and method based on CPU and FPGA. The method's implementation steps are as follows: an embedding module constructs a feature matrix; a preprocessing module preprocesses the feature matrix and weight matrix; the preprocessed feature matrix and weight matrix are moved and cached; an acceleration unit constructs a self-attention matrix; the self-attention matrix is ​​cached and moved; a post-processing unit constructs a global feature matrix; and an MLP Head module obtains the classification result. The preprocessing module in the CPU reduces the additional data processing time of the FPGA acceleration unit by preprocessing the feature matrix and weight matrix, effectively improving the neural network's computation speed. Simultaneously, the normalization operation module in the acceleration unit utilizes exponential and logarithmic approximation results during approximation calculations, eliminating floating-point exponentiation and division operations, effectively reducing hardware resource consumption.

The invention belongs to the technical field of industrial data security and trusted computing, and particularly relates to an industrial data trusted computing-oriented verifiable security co-processing method and system, which comprises the following steps of: acquiring industrial data at an edge end, generating a data consanguinity map and adding a semantic tag; performing calculation task splitting on the industrial data based on a verifiable calculation mechanism to generate a calculation proof; writing the calculation proof and the data abstract into a block chain through a lightweight consensus mechanism; verifying the validity of the calculation proof at the cloud end or the chain end, and returning a verification result; and triggering a subsequent industrial control behavior or a data transaction behavior based on the verification result. According to the method, data consanguinity, zero knowledge proof and on-chain tampering prevention are achieved, data sources can be traced, the calculation process can be verified, and operation behaviors cannot be repudiated. Meanwhile, PBFT consensus and FPGA acceleration are adopted, so that the whole link of collection, proving, consensus, verification and control is lt; and the real-time requirements of motion control and quality closed loop are met.

The invention discloses a multi-device cooperation system for a conference system, and relates to the technical field of comprehensive communication, the multi-device cooperation system comprises an application layer, a core abstraction layer, a driving layer, a kernel layer and a hardware layer, the application layer operates conference application software, the core abstraction layer is a unified hardware abstraction interface layer, and provides a standardized device interface for the application layer; the driving layer and the kernel layer provide hardware driving, a dynamic priority allocation algorithm, an interrupt response and memory sharing mechanism and CPU / co-processing resource scheduling, and the hardware layer comprises a camera, a microphone, a sound box and an FPGA acceleration chip; the method has the advantages that multi-thread communication delay is effectively reduced, system fluency is guaranteed, multi-device cooperation efficiency of the conference machine in a real-time video cooperation scene is improved, high-resolution video streams and low-delay audio transmission are supported, and audio and picture synchronization errors are reduced.

The application discloses a kind of FPGA acceleration card power consumption test method, device and electronic equipment, the method includes: based on CPLD receiving the first instruction sent by BMC, first instruction at least includes modification instruction and target voltage value;According to modification instruction and target voltage value, modify the on-board voltage value of FPGA acceleration card;Based on the second instruction sent by BMC, second instruction at least includes save effective instruction;According to second instruction, save current on-board voltage value and make it effective;Based on current on-board voltage value, upgrade the firmware of FPGA acceleration card and execute power consumption stress test;By BMC and the CPLD of FPGA acceleration card are interacted to realize the modification on-board voltage value of FPGA acceleration card, then high-power consumption version of FW corresponding voltage value is burned again to carry out high-power consumption test, and the test scene of FPGA acceleration card is enriched, and the stability of FPGA acceleration card is ensured.

This invention provides a dynamic model switching framework for AI inference optimization methods and systems on edge devices, relating to the field of AI optimization technology. The methods include: correcting quantization errors by training a quantization compensation model through federated learning; constructing a hierarchical heterogeneous resource management system to achieve multi-core collaborative scheduling; integrating compensation parameters into FPGA acceleration circuits and employing intelligent power balancing technology; and utilizing graph neural networks to construct a dynamic decision engine to trigger model switching. This invention achieves a balance between high-precision AI inference and low-power consumption requirements on edge devices, improving computing resource utilization efficiency and reducing energy consumption.

The invention provides an FPGA (Field Programmable Gate Array) cluster acceleration system and a reconfiguration method. The system comprises a control terminal, an Ethernet switch and a plurality of FPGA acceleration cards under a server node, the control terminal is in communication connection with the server node based on the Ethernet switch; each FPGA acceleration card is in communication connection with the server node based on an Ethernet interface; the control terminal is used for generating a reconfiguration data packet and sending the reconfiguration data packet to each FPGA acceleration card under the server node based on the Ethernet switch; and each FPGA accelerator card is reconfigured based on the reconfiguration data packet. According to the system provided by the invention, the control terminal and the FPGA acceleration cards are connected through the Ethernet, so that when batch FPGA acceleration cards need to be reconfigured, the reconfiguration data packets are simultaneously sent to the FPGA acceleration cards through the Ethernet switch, the batch FPGA acceleration cards can be reconfigured at the same time, the reconfiguration time is greatly shortened, and the reconfiguration efficiency is improved. The method is suitable for scenes requiring high flexibility and low delay, such as cloud computing and edge computing.

The invention discloses a quantum computing data processing method and device and a storage medium, and the method comprises the steps: collecting real-time data of an application scene through terminal equipment, and transmitting the real-time data to an edge processing node cluster; an FPGA acceleration module integrated in the edge processing node cluster is utilized to carry out processing operation on the real-time data to generate a quantum data packet, the processing operation comprises preprocessing, quantization coding and data routing, and the edge processing node cluster sends the quantum data packet and a corresponding task request to a quantum computing center; constructing a quantum service block chain network for analyzing and identifying the task request, and dynamically calling, combining and deploying corresponding quantum services; constructing a quantum calculation model, and performing optimization calculation on the task request by using quantum service; and issuing an optimization calculation result generated by the quantum calculation center to the edge processing node cluster through the quantum encryption transmission channel, and driving the terminal equipment to execute by the edge processing node cluster.

The application discloses a kind of inner and outer network communication methods of PCIE link based on FPGA, comprising (1) inner network receives the communication request and configuration management information sent by external terminal and handles and forwards to inner network VPP passage node;(2) inner network VPP passage node according to protocol processing network topology, control management service and communication information and send to FPGA acceleration card with acceleration data by PCIE;(3) PCIE acceleration card based on FPGA receives and processes the communication data to be accelerated and sends to outer network VPP passage node;(4) outer network VPP passage node receives the communication data that has been accelerated and forwards to black area communication terminal.The application is in the background of red and black isolation, through PCIE high-speed equipment interconnect inner and outer network, combine the high-speed performance of VPP and DPDK, use virtual network interface TUN equipment and VETH equipment to simultaneously open the passage of inner and outer network system local, to guarantee the communication of red area and black area external terminal.In the high-speed performance of maintaining network transmission, realize the architecture communication of inner and outer network service plane and control plane.

The application provides a CPU and FPGA virtual-real combination simulation verification method and system, comprising: creating a CPU simulation model and loading a CPU-side binary executable file; deploying FPGA code through FPGA acceleration hardware based on the CPU simulation model; dynamically configuring the connection relationship and connection interface of the CPU simulation model and the FPGA hardware, and converting the calling interface of the FPGA code into a network interface transceiver; matching the running speed of the CPU simulation model and the FPGA acceleration hardware, and then running an external test device to obtain a test result. Through software and hardware collaborative adjustment and data caching technology, the application ensures the relative uniformity of the simulation timing, improves the reliability and correctness of the joint verification, and effectively supports the simulation deduction of the system.

The application discloses a processing method and device of pooling resources, electronic equipment and medium. The method is applied to an FPGA cloud platform. The FPGA cloud platform comprises an FPGA acceleration card, a switch, a bottom plate and a host. The bottom plate comprises a card slot, is used for inserting the FPGA acceleration card, and supplies power for the FPGA acceleration card. The switch is connected with a fiber network port of the FPGA acceleration card, is used for realizing data interaction between the FPGA acceleration cards. The host is connected with the switch, is used for sending a UDP message to the FPGA acceleration card through the switch. The FPGA acceleration card is used for receiving the UDP message sent by the switch, then analyzing the UDP message to obtain QP field information, and then inputting data to a Kernel end corresponding to the QP field information for processing. It can be seen that the method disclosed by the application realizes multiple Kernel acceleration operations on the same FPGA acceleration card, and can efficiently utilize the pooling resources.

The invention relates to a convolutional neural network FPGA acceleration system and method based on a configurable IP core, belongs to the technical field of artificial intelligence hardware acceleration, and aims to solve the problems of insufficient flexibility, low resource utilization rate, off-chip storage bandwidth bottleneck and the like in an existing CNN acceleration scheme. According to the system, an SoC framework is adopted, a configurable convolution batch normalization activation IP core and a pooling IP core are integrated in an FPGA programmable logic part, parameters are dynamically configured by a processing system according to a network layer sequence, and time division multiplexing of hardware resources is achieved. The convolution and pooling modules are directly connected through AXI4-Stream, intermediate data write-back and rereading are reduced, and delay and bandwidth pressure are reduced. According to the method, by means of software and hardware cooperative scheduling, universality and expansibility are taken into account while the calculation throughput rate is increased, and the method is suitable for efficient reasoning acceleration of various CNN models.

The application discloses an improved Yolov8 pedestrian detection system based on FPGA deployment, which comprises a dense pedestrian dataset module, an improved Yolov8 algorithm module and an FPGA deployment module; the dense pedestrian dataset module comprises a data acquisition module, a data labeling module and a data enhancement module; the improved Yolov8 algorithm module comprises a depth separable convolution module, a double-path attention gate module and a feature enhancement module; and the FPGA deployment module comprises a neural network compression module and a software and hardware design module. The application relates to the technical field of FPGA acceleration target detection algorithms, in particular to an improved Yolov8 pedestrian detection system based on FPGA deployment.

This invention provides a hardware accelerator architecture suitable for deep neural network models, comprising: a CPU and an FPGA wirelessly connected to each other; the CPU is used for normalizing and adaptively adjusting the size of the feature maps input to the neural network model, processing the inference results of the network model to determine the final calculation result, and logically controlling the core computing unit of the FPGA acceleration module; the FPGA is used for accelerated computation and data transmission of data from different network layers; the FPGA includes: a data loading module, a write-back module, and a computation module; the data loading module is used to load data from off-chip into an on-chip buffer, the computation module is used to perform calculations based on the data in the on-chip buffer to obtain the calculation result, and the write-back module is used to write the calculation result back to off-chip DDR. This invention solves the problems of insufficient acceleration performance and high power consumption of existing hardware accelerators for deep neural network models.

The invention discloses an entity library table generation method and system based on a dynamic data model, and the system comprises a dynamic materialization engine module which configures a server cluster, deploys a three-node ZooKeeper cluster for a metadata server, and is responsible for storing model version metadata; a difference calculation module of an FPGA acceleration card is configured for a calculation node, and the Levenshtein editing distance is calculated; the elastic storage distribution module is used for setting a storage distribution strategy of a mixed layout of column storage and row storage and recombining a data space; and the model storage consistency guarantee module is used for setting a transaction log capture layer at a cloud end to monitor a change event of the model definition library, generating a CDC change data capture log with a timestamp, and configuring a two-stage materialization protocol at the same time. According to the scheme, the problem of service interruption caused by the fact that a traditional relational database needs to be shut down to execute DDL operation is solved, and real-time synchronization from model change to table structure adjustment is achieved.

The application discloses an MTLA-Transformer hardware accelerator based on FPGA and relates to the technical field of FPGA acceleration and deep learning inference optimization. The accelerator comprises a controller module, an attention calculation module and a feedforward network module. The controller module is used for completing data scheduling of on-chip cache and off-chip memory and KV cache update management. The attention calculation module comprises a reusable matrix multiplication and addition calculation array, a position coding submodule, a HyperNet calculation submodule, a KV cache management submodule, a Softmax submodule and a residual normalization submodule. Projection calculation, fractional calculation and output projection and other matrix multiplication and addition operation multiplexing are realized through a systolic array. Position coding rotation factor precalculation lookup table, HyperNet position correlation result offline precalculation and Softmax scaling coefficient fusion are adopted to reduce online calculation amount and memory access overhead. The feedforward network module completes two-layer linear transformation and activation operation and realizes residual connection normalization processing. The application can improve incremental inference throughput and reduce hardware resource overhead under the premise of ensuring inference correctness and is suitable for edge end low-power real-time inference scenarios.

This invention discloses an alarm and handling system for the effluent outlet of an industrial wastewater treatment plant, belonging to the field of industrial wastewater treatment technology. It includes: an online water quality monitoring device integrating multiple sensors with an adaptive calibration algorithm; a PLC control box with a built-in embedded computer supporting the execution of mathematical models and machine learning algorithms to predict water quality change trends; edge computing technology combined with an FPGA acceleration card; and a decentralized data recording mechanism built using blockchain technology. When water quality exceeds standards, an intelligent decision-making module automatically selects an emergency plan based on a preset rule base and dynamic adjustment strategies, and continuously improves the response strategy using a Bayesian optimization algorithm to achieve emergency handling. This invention can promptly alert on-duty personnel to abnormal water discharge and can automatically and promptly address drainage issues, preventing the continued discharge of wastewater exceeding standards.

The application relates to the computer technical field and discloses a memory system, a control method and a server, the system comprising: a CPU and an FPGA acceleration card, the CPU and the FPGA acceleration card both supporting a CXL protocol; the CPU and the FPGA acceleration card being connected through a PCIe interface supporting the CXL protocol; the CPU being configured with a plurality of local memory strips through a memory strip slot; the FPGA acceleration card being configured with a plurality of extended memory strips through a memory connection component or a memory connector; and the FPGA acceleration card being used for receiving memory data sent by the CPU, and performing logical calculation on the memory data according to the attribute characteristics of the memory data based on the extended memory strips to obtain target memory data. The system provided by the above scheme realizes expansion of the memory capacity of the server by additionally arranging the FPGA acceleration card, reduces the difficulty of expansion of the memory capacity of the server, and improves the overall performance and response speed of the server.

The invention provides a system and a method for unpacking a data stream accelerated by using an FPGA (Field Programmable Gate Array), and the system comprises a data receiving module which uses a UDP (User Datagram Protocol), configures an IP (Internet Protocol) core, and receives the data stream from external equipment; the data stream caching module is used for caching the received data stream into an RAM (Random Access Memory) and is used for an unpacking process of the data stream; the data stream unpacking module is used for unpacking the data stream in the cache region in real time to obtain a complete data stream; the data stream unpacking module is used for unpacking the data stream in real time according to the packet format information to obtain an unpacking result of each field in the packet format; and the data sending module is used for sending the unpacked data stream to target equipment. The invention provides an innovative method, a large amount of data can be received in real time by utilizing the high-speed processing capability of the FPGA, and pipelined processing is carried out, so that the unpacking requirement of satellite data under high speed and large data volume is met.

The invention relates to the technical field of data processing, and discloses an FPGA (Field Programmable Gate Array) heterogeneous data processing method based on a digital-intelligent integrated platform, which comprises the following steps that: a platform management layer responds to a data processing task request, schedules an acceleration node from an FPGA resource pool, and issues a pre-compilation hardware acceleration bit stream and configuration parameters; loading the hardware acceleration bit stream by an FPGA acceleration node, and dynamically configuring to form a hardware processing pipeline matched with the data processing task request; the method comprises the following steps: receiving an original data stream input by an external data source through a high-speed network interface, and writing the original data stream into an onboard memory of the high-speed network interface; the hardware processing pipeline carries out real-time processing on the original data stream in the onboard memory; and writing the processed result data into a storage device for persistence, and sending the generated metadata and event data to the platform management layer. High-speed processing of data streams is realized in a mode of reconstructing an FPGA hardware processing assembly line.

The invention discloses an FPGA (Field Programmable Gate Array) accelerated intelligent matching technology based on dynamic weight of an AI (Artificial Intelligence) large model. The method comprises the following steps: receiving user demand data; calling an AI large model to carry out deep semantic understanding and feature extraction; carrying out weighted calculation on the feature vectors by adopting a dynamic weight ratio to obtain a matching degree; and outputting a matching result. Wherein the dynamic weight factor is generated in real time by the AI large model according to the context of the current scene. According to the invention, by introducing a dynamic weight mechanism and logic auditing, accurate, efficient and credible intelligent matching is realized, and the technical problems of information asymmetry, low matching precision and high fraud risk in traditional intermediary services are effectively solved.