Data processing method, device and system and FPGA acceleration card

Abstract

The invention discloses a data processing method, which comprises the following steps that: when a data acceleration instruction is received, an FPGA acceleration card reads to-be-accelerated data opposite to the data acceleration instruction in an HBM2 and sends the to-be-accelerated data into a PR region for data acceleration operation; wherein the to-be-accelerated data is the data directly stored in the HBM2 by the host; if the execution of the data acceleration operation is completed, storing the data subjected to acceleration processing into an HBM2; according to the method, a host directly stores data into HBM2 particles in an FPGA acceleration card; the FPGA acceleration card can directly read out data in the HBM2 and send the data into a PR area for data acceleration, and after acceleration is completed, the data is fed back to HBM2 particles; therefore, the data transmission time and the data migration frequency between the host and the FPGA acceleration card are greatly reduced, and the deployment is more convenient; the invention also discloses a data processing device, a data processing system and an FPGA accelerator card, which have the above beneficial effects.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a data processing method, device, system and FPGA accelerator card. Background technique [0002] At present, under the host + FPGA accelerator card structure, the data on the host side needs to be processed by the FPGA accelerator card (Field Programmable Gate Array, Field Programmable Gate Array). Then notify the FPGA accelerator card to move the data to be accelerated to the DDR (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory, a memory specification) (such as DDR4) on the FPGA accelerator card through the PCIE interface ; After the move is completed, the FPGA accelerator card starts to process the data to be accelerated, and it is necessary to read the data to be accelerated in the DDR and send it to the PR (Partial Reconfiguration, partial reconfiguration) area; In the DDR on the FPGA accelerator card, and then notify the host to move th...

AI Technical Summary

Problems solved by technology

It can be seen that in the whole process of data acceleration, the data to be accelerated needs to be moved four times, which greatly wastes precious processing time

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