Data processing method and device of heterogeneous computing platform and readable storage medium

Abstract

The invention discloses a data processing method and device of a heterogeneous computing platform and a computer readable storage medium. The method comprises the steps that a data storage area and adata processing result storage area are opened up in a host memory space in advance, and a to-be-processed data storage area and a calculation result storage area are opened up in an FPGA accelerationboard card memory space; after the host stores the to-be-calculated data in the data storage area, a data processing request is issued to the FPGA acceleration board card, and the FPGA acceleration board card actively reads the to-be-calculated data from the data storage area and stores the to-be-calculated data in the to-be-processed data storage area of the FPGA acceleration board card; a corresponding data processing algorithm is called to perform data calculation on the to-be-calculated data in the to-be-processed data storage area to obtain a data calculation result, and the data calculation result is stored in a calculation result storage area; and finally, the data calculation result back is actively writted to the data processing result storage area of the host. The data transmission efficiency of the heterogeneous computing platform is improved, and the computing performance of the FPGA acceleration board card is improved.

Description

technical field [0001] The present application relates to the technical field of heterogeneous computing, and in particular to a data processing method, device and computer-readable storage medium of a heterogeneous computing platform. Background technique [0002] With the rapid development of machine learning technology, deep learning, as a method based on representation learning of data in machine learning, has been widely used. In order to improve the data processing capability in the process of deep learning, related technologies are adopted on a heterogeneous computing platform composed of a host and an FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array) acceleration board. The room is a PCIE interface, through which signal interaction and data transmission are completed. The host is responsible for overall scheduling, and the FPGA accelerator board is responsible for parallel processing of data, which not only relieves the computing pressure on the ho...

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Problems solved by technology

[0004] Since the process of sending control commands, receiving interrupt responses, and starting data transmission by the host software requires more clock cycles, and there may be other software processes on the host side that occupy system resources, the data transmission efficiency is not high, which affects the performance of the FPGA accelerator board. Computational performance. For applications such as convolution accelerators in deep learning inference computing, which are extremely time-sensitive and pursue extreme performance, how to eliminate the waste of these clock cycles and further improve computing efficiency is a technical problem that those skilled in the art need to solve

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