17 results about "Sparse matrix-vector multiplication" patented technology

The invention provides an acceleration processing method and device for sparse matrix vector multiplication. The method comprises the following steps: acquiring a sparse matrix; dividing the sparse matrix into segments, and distributing threads for the segments; a matrix multiplication-accumulation instruction in a preset instruction set architecture is called, a tensor calculation core Tensor Core is used for carrying out matrix multiplication calculation of small blocks on the fragments, result data are obtained, and the result data are used for representing vector data objects of the linear equation set solution vectors. According to the method, the obtained sparse matrix is divided into the fragments and the threads are distributed, so that Tensor Core concurrent calculation is realized, the calculation efficiency is greatly improved, and the calculation time is remarkably shortened especially for solving a large-scale linear equation set.

The invention relates to a CPU-DSP (central processing unit-digital signal processor)-based sparse matrix vector multiplication heterogeneous parallel computing method, which specifically comprises the following steps of: for each row in a sparse matrix, removing zero elements in the row, and dividing non-zero elements in the row into slices with the same length; storing each slice according to the target storage format; the target storage format corresponds to a first array, a second array and a third array, the first array is used for sequentially storing each element in the slice according to rows, and the second array is used for storing a column index corresponding to each element in the first array; the third array is used for storing the global index of the first slice in each row of the sparse matrix. And after the line-by-line compression storage, distributing subtasks of sparse matrix vector multiplication calculation to each process, and merging results after the processes execute the subtasks in parallel to obtain a target result of sparse matrix vector multiplication. The method can improve the calculation efficiency.

The application provides a hash-based sparse matrix vector multiplication optimization method, which is characterized by the following steps: dividing a sparse matrix to be multiplied into a plurality of sparse matrix blocks according to the hardware structure of a neural network hardware accelerator, performing linear hash mapping on the plurality of sparse matrix blocks to obtain a to-be-divided matrix; dividing the to-be-divided matrix into a plurality of sub-matrix blocks according to the size of the to-be-divided matrix and the hardware structure, and dividing parallel execution parts and competitive execution parts in the sub-matrix blocks; the neural network hardware accelerator performs competitive execution of a calculation task between the sub-matrix blocks and parallel execution of the calculation task in the sub-matrix blocks to obtain a plurality of sub-matrix calculation results, and restores the original order of writing through a hash table; and the plurality of sub-matrix calculation results are combined according to the original order to obtain a final result of matrix vector multiplication.

The invention discloses a sparse matrix vector multiplication-oriented hardware accelerator, sparse matrix vector multiplication-oriented hardware accelerator equipment and an application method, and the hardware accelerator comprises an off-chip storage system, an on-chip network used for carrying out data exchange routing, and an on-chip processing system used for executing access and multiplication calculation and matrix in-row element merging, the off-chip storage system comprises HBM channels used for storing five types of data of a column index, a row index, a vector value, a matrix value and a result vector, each HBM channel comprises an HBM stack and a memory controller, and the HBM channels used for storing the vector values are connected with an on-chip network through second-level caches. And the other HBM channels are directly connected with the on-chip processing system. The method aims at improving on-chip data reuse of the hardware accelerator for sparse matrix vector multiplication, reducing off-chip memory access times and improving performance and energy efficiency performance of the hardware accelerator.

This invention discloses a hardware accelerator, device, and application method for sparse matrix-vector multiplication. The hardware accelerator includes an off-chip storage system, an on-chip network for data exchange routing, and an on-chip processing system for performing data fetching, multiplication calculations, and matrix row element merging. The off-chip storage system includes HBM channels for storing five types of data: column indices, row indices, vector values, matrix values, and result vectors. Each HBM channel includes an HBM stack and a memory controller. The HBM channels for storing vector values ​​are connected to the on-chip network via a L2 cache, while the remaining HBM channels are directly connected to the on-chip processing system. This invention aims to improve on-chip data reuse in hardware accelerators for sparse matrix-vector multiplication, reduce off-chip memory accesses, and improve the performance and energy efficiency of the hardware accelerator.

The invention provides a modeling optimization method and system for GPU heterogeneous accelerator card performance based on sparse matrix vector multiplication. The modeling optimization method comprises the steps that data features of an input sparse matrix and hardware parameters of a GPU heterogeneous accelerator card are determined; the data features and the hardware parameters are associated and serve as a data set, and the data set is divided into a training set and a test set; constructing a performance evaluation model based on the hierarchical decision tree, and training and testing the performance evaluation model by using the training set and the test set to obtain an optimal performance evaluation model; optimizing the acceleration card to be tested by using the optimal performance evaluation model; according to the method, sparse matrix structure features, candidate kernel features of priori knowledge and accelerator card hardware configuration features are analyzed, calculation kernel selection and parameter configuration selection are effectively guided based on an interpretable adaptive model of a hierarchical decision tree, and performance improvement is achieved on both a GPU accelerator card platform and an NVIDIA GPU accelerator card platform in a domestic C86 environment.

The application discloses a special accelerator for a hierarchical greedy decoding algorithm, and belongs to the technical field of quantum computation, and comprises a transformation unit, a decoding core and a permutation unit; the transformation unit is used for receiving original error symptoms, and multiplying the original error symptoms with a transformation matrix through sparse matrix vector multiplication to generate transformed error symptoms; the decoding core is used for executing a hierarchical greedy decoding algorithm, dividing error patterns into left errors and right errors, and performing calculation including guessing right errors and decoding left errors in parallel based on the transformed error symptoms to obtain new values of the error patterns; and the permutation unit is used for receiving the new values of the error patterns, multiplying the new values of the error patterns with a permutation matrix through sparse matrix vector multiplication to calculate final error patterns. The application can realize real-time qLDPC decoding and significantly reduce decoding delay.

The application relates to a matrix data architecture, comprising a matrix head and a matrix block; the matrix head comprises a matrix row, a column number, a non-zero element number, a matrix block number and a vectorization length S VVec ; the matrix block comprises a matrix block element; the length of an x vector pixel geometry block corresponding to each of the matrix blocks is S ImgB ; the structure of the matrix block is at least two, which are a fixed-length dense VxG block and a fixed-length sparse VxG block. A method for accelerating sparse matrix vector multiplication (SPMV) based on compressed sparse columns is used to convert the matrix format of an input sparse matrix A into the above-mentioned matrix data architecture, which is a sparse matrix storage format; the SPMV calculation is performed on a local temporary y vector reordering and full vectorization. The data architecture has the characteristics of small space occupation. In combination with the method for accelerating SPMV based on compressed sparse columns, hardware vectorization calculation instructions and memory bandwidth can be efficiently utilized, so that the SPMV can run at a faster speed, and the purpose of acceleration is achieved.

The invention discloses a load balancing and memory access optimization method for an SpMV algorithm on a multi-GPU platform. The method comprises the following steps: determining the dimensionality, sparseness and GPU number G of an SpMV data set; calculating the number gropNum of the working groups, dividing original CSR format data sets according to the number of the working groups, and sending the original CSR format data sets into shared memories of the corresponding working groups; determining the thread number group Size of each working group, and calculating the cycle step length of each thread; spMV calculation is realized, and a calculation result of each working group is stored in a global memory to obtain a final result. The invention aims to provide a load balancing and memory access merging optimization method for a sparse matrix vector multiplication (SpMV) algorithm on a multi-GPU platform by utilizing more computing resources and storage capacity of a multi-GPU structure aiming at the current situation that the number of memory access optimization methods for a CSR format of the SpMV algorithm on a CPU and a single GPU platform is small.

The invention relates to a method and device for processing sparse matrix vector multiplication based on RISC-V. The method comprises the following steps: dividing an N: M sparse weight matrix into P * Q N: M weight matrix blocks, wherein the dimension of each weight matrix block is V * V; dividing the input feature vector into Q feature vector segments with the length of V; extracting all non-zero weight elements in each weight matrix block in a row-first order to generate a dense weight vector of the weight matrix block, and generating an index vector corresponding to each weight matrix block, the index vector is used for indicating a column offset position of each non-zero weight element in the corresponding weight matrix block in a row to which the non-zero weight element belongs in the weight matrix block; matrix vector multiplication of the at least one weight matrix block and the corresponding feature vector segment is processed in parallel in a vector execution unit of the RISC-V processor; and obtaining the output vector by accumulating all the parts related to the same output row of the output vector and the vector.

The invention discloses an electromagnetic simulation method based on a CPU (Central Processing Unit) and a DSP (Digital Signal Processor), which comprises the following steps of: firstly, redesigning a parallel computing framework and constructing an efficient cooperative computing and data communication mechanism between a main processor and a coprocessor aiming at a heterogeneous framework of the domestic CPU and the DSP, and solving the fundamental problem that the original isomorphic framework is difficult to deploy and operate on a domestic platform; secondly, specific hardware-oriented reconstruction and optimization are carried out on the data structure, the data scheduling process and the calculation core of the calculation hotspot so as to match the hardware characteristics of the domestic accelerator and overcome the performance bottleneck. Through the software and hardware collaborative special optimization method, the problem of adaptation and application of the time domain discontinuous Galerkin method on accelerator platforms such as domestic Maiku and the like is successfully solved, and on the premise that the calculation precision is guaranteed, the calculation efficiency is remarkably improved, and the method is suitable for popularization and application. Wherein the sparse matrix vector multiplier obtains an acceleration effect which is not less than 1.6 times under a certain scale. According to the method, the practical value of a domestic autonomous platform is effectively improved, and the method has important significance for promoting localization substitution and technical autonomous controllability of high-end electromagnetic simulation software.

The invention discloses a heterogeneous medical system data interaction method and system based on a unified standard interface, and decoupling of a core business system and an external heterogeneous system is realized by introducing a standard interface operation and maintenance platform as a middle layer. The modular design in the platform comprises a unified access module, an interface configuration and management module, a data conversion module, a protocol adaptation module, an order and state management center and the like, and a flexible, extensible and manageable data interaction system is formed by the unified access module, the interface configuration and management module, the data conversion module, the protocol adaptation module, the order and state management center and the like. Particularly, through application of innovative technologies such as dynamic interface priority scheduling and sparse matrix-vector multiplication, the performance and efficiency of the system are further improved.

The invention discloses a sparse matrix-vector multiplication acceleration method for a dawn-bathing GPU, and belongs to the field of high-performance calculation. The method comprises the following steps: acquiring a sparse matrix A and a vector x in a CSR format; dividing A into 16 * 16 sub-blocks Tile according to the width of an operand of a Xichen GPU matrix multiplied instruction, and making a proportion eta < lt > for non-zero elements; a CSR sub-matrix rowbase list is generated by 10% of Tiles, and a Tile-Dense sub-matrix block base list is generated by the rest of the Tiles; rows of the CSR sub-matrix are divided into light rows, medium rows and weight rows according to the number of non-zero elements, three-level protocols are completed in the same GPU kernel through Thread Block Tile, on-chip shared memory and global memory atomic operation, and ycsr is obtained; an mfma instruction is called for the Tile-Dense sub-matrix, and accumulation is carried out to obtain ytile; and finally, accumulating the ycsr and the ytile according to rows to output a result y. According to the method, an mcSPARSI interface can be replaced in a binary level, and load unbalance is relieved and the matrix multiplication instruction utilization rate is improved on the premise that an upper frame is not changed.

The application provides a high-bandwidth utilization rate sparse matrix vector multiplication acceleration device, which comprises a decoder, a read conflict-free input vector buffer, a calculation unit array, a write conflict-free adder tree, a ping-pong supporting accumulator group, a storage part and a result vector buffer; the decoder is used for decoding a preprocessed matrix; the decoder transmits vector elements in the matrix into the read conflict-free input vector buffer after decoding; non-zero elements in a target matrix are decoded and transmitted into the calculation unit array; the calculation unit array is used for reading corresponding vector elements from the read conflict-free input vector buffer according to column numbers of the non-zero elements, multiplying the vector elements with the non-zero data, and transmitting the multiplication results and row numbers of the non-zero elements into the write conflict-free adder tree; the write conflict-free adder tree is used for adding multiplication results with the same row numbers, and transmitting the addition results into accumulators; and the ping-pong supporting accumulator group is used for accumulating the addition results.

The invention discloses a special accelerator for a hierarchical greedy decoding algorithm, which belongs to the technical field of quantum computing and comprises a transformation unit, a decoding core and a replacement unit. The transformation unit is used for receiving the original error symptom and generating a transformed error symptom through sparse matrix vector multiplication and transformation matrix multiplication; the decoding core is used for executing a hierarchical greedy decoding algorithm, dividing an error mode into a left error and a right error, and executing calculation including guessing the right error and decoding the left error in parallel based on a transformed error symptom to obtain a new value of the error mode; and the permutation unit is used for receiving the new value of the error pattern, and calculating to obtain a final error pattern through sparse matrix vector multiplication and permutation matrix multiplication. According to the invention, real-time qLDPC decoding can be realized, and the decoding delay can be obviously reduced.

This application provides a GPU-based sparse matrix-vector multiplication optimization method and apparatus for large-scale computing. The method includes rearranging and reorganizing the sparse matrix to make the distribution of non-zero elements in adjacent columns of the rearranged sparse matrix more similar; dividing the non-zero elements in each row of the sorted sparse matrix into several slices, placing the slices into containers that satisfy constraints, namely, the starting column index of the newly added slice is consecutive to the column indices of other existing slices; each container corresponds to a synchronous execution unit, and several synchronous threads perform the multiplication and accumulation of non-zero elements with the corresponding components of the input vector. Thus, matrix rearrangement makes it more likely that a synchronous execution unit will process data from the same row; by dividing non-zero elements with the same row index and consecutive column indices into slices and placing them into containers, the continuity of data processed by the synchronous execution unit in the column direction reduces non-merged memory accesses and enhances data reuse capabilities.

An optimization method for sparse matrix-vector multiplication of multiple matrices with the same structure is applied to the iterative solution process of harmonic balance methods in radio frequency circuit simulation. The method includes: obtaining a first sparse matrix and a second sparse matrix of the circuit, wherein the first and second sparse matrices have the same structure and are used to characterize the nonlinear conductance and nonlinear capacitance characteristics of the circuit, respectively; in response to performing matrix-vector multiplication, in one traversal, simultaneously accessing the non-zero elements located at the same position in both the first and second sparse matrices, and performing multiplication and accumulation operations with the corresponding input vector elements to obtain the output vectors of the corresponding first and second sparse matrices; wherein the input vector is the harmonic component vector of the circuit node voltage. This invention, based on the combined access of multiple matrices with the same sparse structure, significantly reduces loop control overhead, thereby improving the overall efficiency of matrix-vector multiplication.