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FPGA-based expandable sparse matrix vector multiplication processor

A sparse matrix and processor technology, which is used in electrical digital data processing, instruments, machine execution devices, etc., to achieve the effects of high-efficiency computing, good computing efficiency, and high data throughput

Pending Publication Date: 2018-10-26
NANJING UNIV
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Problems solved by technology

[0003] At present, sparse matrix-vector multiplication operations are mostly performed by CPU, GPU, or CPU-GPU collaborative operations. However, the compression format required to efficiently store sparse matric

Method used

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  • FPGA-based expandable sparse matrix vector multiplication processor
  • FPGA-based expandable sparse matrix vector multiplication processor
  • FPGA-based expandable sparse matrix vector multiplication processor

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Embodiment Construction

[0022] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] In this embodiment, the sparse matrix in the scalable sparse matrix-vector multiplication processor adopts the CSC compressed storage format, that is, three different arrays are used to describe the positions of non-zero elements in the sparse matrix. The three arrays are: the data array that stores all non-zero element values ​​in order from top left to bottom right, the row array that records the row number corresponding to each non-zero element, and records the first non-zero element in each column in the data array The ptr array of serial numbers. figure 1 Represents a sparse matrix of size 4*5 stored in a compressed storage format. In this embodiment, the sparse matrix in the scalable sparse matrix-vector multiplication processor adopts the CSC compression storage format as follows:

[0024]

[0025] Such as figure 1 , the scalable sparse matrix-vec...

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Abstract

The invention provides an FPGA-based sparse matrix vector multiplication processor. The processor comprises a preprocessing controller module, an operation module and a storage controller module, wherein the preprocessing controller module is used for performing scheduling and hazard detection and enabling a storage unit to keep continuous data flow for an operation unit array; the operation unitarray is composed of a plurality of operation units; single-precision floating-point sparse matrix vector multiplication operation is realized through single-precision floating-point multiplier and adder; and the storage controller module is used for controlling reading and writing of data in an off-chip DRAM. The beneficial effects are that the processor can expand the storage bandwidth and the operation resources, and the operation efficiency and universality of the processor are effectively improved.

Description

technical field [0001] The invention belongs to the field of FPGA technology and high-performance computing, in particular to an FPGA-based sparse matrix-vector multiplication hardware accelerator. Background technique [0002] Operations on sparse matrices appear in a wide variety of computational disciplines, including image reconstruction, circuit and financial modeling, industrial engineering, compressed sensing, and in recent years, very popular neural networks. Among many operations involving sparse matrices, the multiplication operation between sparse matrices and vectors is the most frequently used in the above fields, and its efficiency directly determines the operational efficiency of the entire processor. [0003] At present, sparse matrix-vector multiplication operations are mostly performed by CPU, GPU, or CPU-GPU collaborative operations. However, the compression format required to efficiently store sparse matrices does not match the traditional computing struc...

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30036
Inventor 潘红兵朱棣秦子迪李丽李伟何书专
Owner NANJING UNIV
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