34results about How to "Improve data throughput" patented technology

The application belongs to the chip packaging technical field, and particularly relates to a running control method based on a heterogeneous optoelectronic chip, steps of which are as follows: S101, obtaining a task quantity of a to-be-calculated task; and judging whether the task quantity is greater than a set first calculation threshold; when the judgment result of step S101 is yes, then step S102 is executed, that is, a type one photonic chip is recommended for the to-be-calculated task to execute calculation; when the judgment result of step S101 is no, then step S103 is executed, that is, a recommended calculation time consumption of the to-be-calculated task is obtained, and whether the recommended calculation time consumption of the to-be-calculated task is less than a set time length is judged; when the judgment result of step S103 is yes, then step S104 is executed, that is, a type two photonic chip is recommended for the to-be-calculated task to execute calculation; when the judgment result of step S103 is no, then step S102 is executed. The control method can realize flexible switching and stable high-speed running of the optoelectronic chip in an extreme environment.

This invention discloses a heterogeneous acceleration system and method for analog modulation recognition of large-scale multi-channel signals, comprising: a CPU host processing end and a GPU device computing end; the CPU host processing end is used for asynchronous pipelined processing of data reading, task scheduling, and result distribution, realizing parallel execution of data reading, GPU computing, and result distribution on the time axis; the GPU device computing end completes the entire process of signal preprocessing and deep learning model inference within the GPU memory after the original signal is transmitted to the video memory via the PCIe bus, and does not exchange data with the CPU host processing end until the recognition result is generated. This invention eliminates data transport and I / O blocking through a three-stage asynchronous pipeline architecture and a closed-loop processing link in the entire video memory, and combines parallel preprocessing operators, inference acceleration engines, multi-stream scheduling mechanisms, and dynamic video memory pools to achieve high throughput and low latency recognition of large-scale multi-channel analog modulation signals.

The application relates to the technical field of power system communication, and discloses an energy storage system communication protocol optimization method based on IEC61850, which comprises the following steps: embedding an extensible mask field in a message of an MMS confirmation type protocol data unit, preset bit positions of the extensible mask field one-to-one correspond to each interactive variable in the message, and the state of each bit position is used for representing the confirmation receiving state of the corresponding interactive variable; dividing each interactive variable into a key variable and a non-key variable according to the importance level of interactive data; and analyzing the extensible mask field at a receiving end. The key variable is instantaneously confirmed and the non-key variable is aggregated and replied through the extensible mask field, redundancy interaction is eliminated, batch control instruction response delay is reduced to the millisecond level, and thus the control communication delay is reduced; and the traditional fixed window limit is broken through, the MMS-TPO sending window scale is dynamically self-adaptively adjusted through real-time monitoring of link round trip time, the transmission stability is ensured, and the cluster total calling efficiency is greatly improved.

The application relates to the field of backscatter technology and discloses a single-receiver WiFi backscatter communication method and system, which comprises the following steps: a tag receives OFDM symbols from ambient WiFi signals, a linear phase factor corresponding to a tag-related cyclic shift value is applied to only the middle part of a data load, and the OFDM symbols of a reflection signal are reconstructed based on the middle part of the modulated data load; a receiver extracts the modulated part from the received OFDM symbols of the reflection signal, performs frequency domain inverse shift compensation on each candidate cyclic shift value, obtains a reconstructed data load based on the obtained compensated spectrum, calculates the correlation score between the power spectrum of the reconstructed data load each time and a binary template predefined based on the position of the empty subcarrier, decodes the cyclic shift value, and recovers the corresponding tag data. The application can realize a high data throughput without sacrificing OFDM compatibility.

A low-complexity 1-bit signal decoder and a design method thereof, the decoder includes a counter module, a fixed subtraction module, M decoder submodules and an output control signal generating module; the counter module inputs a reset signal and a clock signal, the M decoder submodules form a parallel operation processing unit, M-1 fixed subtraction modules are arranged one-to-one between the counter module and the decoder submodule, and the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable ends are all connected to the output control signal generating module, and the outputs are all N-bit digital signal streams. The present invention also provides a design method for a low-complexity 1-bit signal decoder. The present invention has extremely low complexity and power consumption, is suitable for high-speed data processing, can be implemented in the form of an integrated circuit, and is suitable for high-bandwidth signal processing.

This disclosure relates to the field of computer and graphics processor technology, and discloses a register data transfer system, method, electronic device, storage medium, and computer program product. The system includes: an instruction issuing module for sending N data transfer instructions, the BL of each data transfer instruction, and the IA of each thread included in each instruction to an instruction control module in parallel; the instruction control module for determining the execution order of the N data transfer instructions, and sending the BL of the currently to-be-executed data transfer instruction and the IA of each thread included in each instruction to a register read / write module according to the execution order; and the register read / write module for executing the data transfer instruction according to its BL and the IA of each thread included in each instruction. This disclosure can realize register data transfer based on indirect addressing, improve the overall timing performance of the register data transfer system, reduce data transfer latency, and increase the flexibility of data transfer.

The present invention provides a user-mode stack architecture system supporting TSN protocol under Tianmai operating system and its implementation method, the protocol stack system includes an API module, a management module for deployment management of the protocol stack, an FD module for socket management, a TSN scheduling module, a data cache module, a packet receiving and sending module, a table entry management module and an OPS interface module. The user-mode protocol stack architecture supporting TSN protocol under Tianmai operating system proposed by the present invention greatly improves data forwarding performance by reducing memory copying, and expands the support of TSN services to meet the differentiated QoS requirements of users, so as to better support the requirements of TSN services on the software system side; at the same time, in order to maximize the efficiency of resource utilization, the user-mode protocol stack and the kernel protocol stack share resources such as ARP table items and routing table items, and complete the shaping and sending and receiving of TSN key data streams on the software side through the TSN scheduling module, thereby reducing the delay and jitter on the software side.

The invention relates to a programmable optical computing chip, comprising: an input layer comprising an on-chip light source module, a wavelength division multiplexer and an optical modulator group; the input end of the linear layer is connected with the output end of the input layer so as to perform matrix-vector multiplication operation on the plurality of input light splitting signals input by the input layer to obtain a plurality of output light signals; the output layer is connected with the output end of the linear layer, and the output layer detects the optical signal intensity of a plurality of output optical signals and determines a matrix-vector multiplication operation result according to the optical signal intensity of each output optical signal; and the control module is respectively connected with the input layer, the linear layer and the output layer. The method at least can realize large-scale parallel data operation, has polarization insensitivity, can process a plurality of signals in different polarization states at the same time, and improves data throughput and calculation efficiency.

A baseband signal encoding method based on LDPC code relates to the technical field of baseband signal encoding. According to preset LDPC encoding parameters of a communication link, an original baseband signal is encoded to generate an encoded signal and transmit it; a receiving end decodes the received codeword to obtain an estimated bit sequence of the original baseband data and a bit error rate of a current feedback sliding window of each communication link; the receiving end obtains the signal-to-noise ratio level of each communication link according to the bit error rate of each communication link and a lookup table, and generates an optimal LDPC encoding parameter according to the lookup table, a bit error rate threshold, an occupied bandwidth corresponding to a codeword generated by different LDPC encoding parameters, a remaining bandwidth of each communication link and a signal-to-noise ratio level, and feeds back the optimal LDPC encoding parameter to a transmitting end; a transmitting end updates the preset LDPC encoding parameters of the communication link for the fedback encoding result, and meets the higher requirements of future wireless communications on speed, reliability and delay.

The invention relates to an AUV (Autonomous Underwater Vehicle) cluster sensing communication integrated data collection and path planning method, which is applied to an underwater sensing communication integrated system, the system comprises a data center, a plurality of underwater control nodes, an AUV cluster and a plurality of sensor nodes, and the method comprises the following steps: the data center allocates a working area for each underwater control node; each control node divides the sensor nodes in the working area of the control node into a plurality of sensor node clusters and calculates the overlapping communication area of each sensor node cluster, and then plans a path for the AUV cluster to which the control node belongs, so that the energy efficiency is maximized when the AUV cluster cooperatively traverses the overlapping communication area of each sensor node cluster in the working area to complete data collection. According to the invention, the energy efficiency of the AUV underwater wireless sensor network can be improved.

The invention discloses a broadband dual-channel magnetic coupling wireless power and data transmission slip ring, which adopts a non-contact magnetic coupling mode and solves the problems of short service life, unstable transmission, frequent maintenance and the like caused by mechanical wear of a traditional contact slip ring. Through the bipolar structure of the data coupling antenna, the magnetic flux sum of an inner ring and an outer ring is zero, and complete decoupling of power and data airspace is realized; the bandwidth of a data channel is expanded by adopting multi-stage L-shaped impedance matching, and mutual inductance of power and data coupling parts is stable in the 360-degree rotation process. The slip ring improves the transmission reliability, the rotation adaptability and the data throughput capacity, and is suitable for rotary connection systems in the fields of petroleum drilling, aerospace equipment and the like.

According to the high-speed non-2-power point FFT device based on the small SPRAM, only the word SPRAM is used as a data buffer area, and consumption of storage resources is low. According to the method, a mapping mode of conflict-free access to the SPRAM is designed, three block mapping modes are given, and the data throughput rate is increased; according to the method, the calculation sequence of butterfly operation of each dimension and each level is optimized, high-order base butterfly operation is adopted, low-order base butterfly operation is processed in parallel, and the calculation time is shortened. The method is compatible with various points, and can be applied to LTE communication and broadcasting systems.

The invention provides a signal processing device of a digital coherent optical transceiver module, comprising: a clock synchronization module for outputting a reference clock signal; the high-speed acquisition module comprises a plurality of high-speed analog-to-digital converters, and the high-speed analog-to-digital converters are respectively used for receiving the reference clock signal and the optical signal sent by the digital coherent optical transceiver module and sampling the received electric signal based on the received reference clock signal to obtain a sampling signal; the signal processing module is used for receiving the reference clock signal and each sampling signal, and processing each received sampling signal according to a preset processing mode based on the reference clock signal to obtain a target signal corresponding to each sampling signal; and the signal forwarding module is used for receiving the target signals, sending the received target signals to external equipment and efficiently processing the data signals sent by the digital coherent optical transceiver module.

The invention relates to the technical field of data recording, and discloses a high-speed data recording method and system based on multi-bus heterogeneous fusion, and the high-speed data recording method based on multi-bus heterogeneous fusion comprises the steps: collecting real-time data characteristic parameters of each heterogeneous bus, and constructing a characteristic vector; extracting a time sequence mode of each bus feature vector; dynamically adjusting a cache resource allocation proportion of each bus based on a reinforcement learning technology; constructing a bus data feature knowledge graph by pre-training a basic strategy model under a plurality of working conditions; recognizing system working condition changes and triggering strategy switching; a two-stage cache architecture is realized, and the cache size of each bus is dynamically adjusted according to the cache resource allocation proportion; according to the method and the device, the technical problems that cache resource distribution is fixed in heterogeneous bus data recording, the adaptability to burst data streams is insufficient, and the performance is temporarily reduced during working condition switching are solved, and efficient cache resource utilization and stable data recording are realized.

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

This invention provides a method for transmitting railway Building Information Modeling (BIM) model files based on distributed storage. The method includes: lightweight decomposing the railway BIM model file into multiple sub-files; distributing these sub-files across edge server nodes using a cloud server; transmitting the sub-file list to a gateway; constructing a BIMdex index model; training the BIMdex index model using a training dataset; deploying the trained BIMdex index model locally on the gateway; and when an end device sends a file request carrying a file identifier to the gateway, the BIMdex index model in the gateway queries the sub-file list based on the file identifier, obtains the corresponding BIMdex address index, and returns it to the end device. This invention significantly improves data transmission efficiency by distributing sub-files of the same railway BIM model across multiple physical nodes and combining this with load balancing technology.

The invention provides a carrier communication method for a laser energy transmission system with a dispersed structure, which is characterized in that a semiconductor laser is adopted as an electro-optical conversion device, a power controller and a signal modulator are combined at a transmitting end, and a modulation signal is superposed on a laser beam while energy transmission is realized, so that the laser energy transmission system with the dispersed structure is realized. Energy and information superposition is realized; at a receiving end, a photovoltaic array is adopted to convert received laser beam energy into electric energy, modulation information is extracted at the same time, and energy and information separation is achieved; a plurality of independent energy transmission links are arranged, each link independently transmits energy and information, and each link is connected to a photovoltaic array to realize energy conversion and information demodulation. The system is particularly suitable for high-power energy transfer occasions, synchronous transmission of energy and information is achieved, the overall transmission rate and data throughput of the system are greatly improved, the requirement for high-frequency modulation equipment is reduced, the requirement for hardware is low, and good system compatibility and expandability are achieved.

This application provides a point cloud processing system and method. The system includes: a PL (Plug-in) terminal and a PS (Power Supply) terminal. The PS terminal sends point cloud data calculation commands to the PL terminal. A hash filtering module generates point cloud data read commands based on the point cloud data calculation commands, sends the point cloud data read commands to a data transfer module, and processes the initial point cloud data in real time using a pipeline to obtain processed point cloud data. A gradient calculation module performs gradient calculations on the processed point cloud data in parallel using a data stream through multiple calculation sub-modules connected by FIFO or ping-pong buffers to obtain multiple gradient vectors. An application processor on the PS terminal calculates the descent direction of the multiple gradient vectors and determines whether the descent direction converges. If the descent direction converges, the point cloud computing is terminated. Thus, the provided point cloud processing scheme can improve the throughput of point cloud data processing and reduce latency.

This invention belongs to the field of chip packaging technology and relates to an enhanced non-planar packaging system with heat dissipation function. It includes a substrate, a non-planar reconstruction layer, and at least one photonic chip. The non-planar reconstruction layer is disposed above the substrate and includes: at least one silicon bridge, at least one electronic chip, and molding compound. The silicon bridge is disposed on the side of the electronic chip. The molding compound wraps around the silicon bridge and the electronic chip to form a molding area. A first wiring area is provided between the silicon bridge and the inner surface of the molding area. Multiple first-type heat dissipation parts are spaced apart within the first wiring area to form a heat dissipation area. The first-type heat dissipation parts have a first insulating part near the inner surface of the molding area. A second-type heat dissipation part is disposed on the silicon bridge. The photonic chip is disposed on the outer surface of the heat dissipation area. This system vertically stacks multiple electronic chips through the non-planar reconstruction layer, resulting in a small volume and the ability to lay out various linewidths and spacings of wiring, greatly improving the performance, heat dissipation, and strength of the electronic chips.

The invention discloses a multi-mode intelligent analyzer based on an FPGA, and the analyzer comprises a signal input unit which is used for carrying out the filtering processing of two paths of inputted analog signals; the analog-to-digital conversion unit is used for performing analog-to-digital conversion processing on each path of filtered analog signal to obtain a corresponding time domain signal; the wireless communication module is used for receiving a preset parameter threshold value set by a user; the FPGA main control unit comprises two parallel signal processing assembly lines which are used for carrying out frequency domain transformation on the received two paths of time domain signals in parallel to obtain frequency domain signals; the intelligent judgment module is used for performing parameter analysis on the frequency domain signal to obtain parameter characteristic data, and judging a preset parameter threshold value and the parameter characteristic data to obtain a judgment result; the display information fusion module is used for fusing the time domain signal, the frequency domain signal, the parameter characteristic data and the discrimination result to obtain a fused video data stream; and the display unit is used for displaying the fused video data stream and realizing multi-modal data display on the same screen.

The invention provides a DPU-based model reasoning acceleration method, device and equipment and a medium, and the method comprises the steps: carrying out the color separation of a to-be-reasoned data image, and obtaining at least two single-channel images; synchronously performing feature extraction on each single-channel image based on the dual-shrinkage array and the at least two convolution kernels to obtain a feature map; the feature map is used for model reasoning; the dual-shrinkage array is used for matrix multiplication required by feature extraction and realizing parallel computing; the dual-shrinkage array is realized by the DPU through a hardware description language. According to the invention, through the DPU dual-shrinkage array and at least two convolution kernels, feature extraction is carried out on a plurality of single-channel images and parallel calculation is carried out on a large-scale matrix, so that the system throughput is improved, and large-model reasoning acceleration is realized.

The embodiment of the invention provides a GIS-based marine spatial data analysis method and system, and relates to the technical field of marine spatial data analysis, and the method comprises the steps: continuously receiving a real-time dynamic information flow, and evaluating the inrush state of the real-time dynamic information flow and the load condition of a core processing unit, obtaining an information flow state evaluation result and a system load condition; and analyzing the error and noise level of the real-time dynamic information flow and endowing the real-time dynamic information flow with a confidence score and a preset prediction model to obtain an information quality evaluation result and the confidence score so as to determine an information processing mode and adjust information processing parameters of the information processing mode. According to the invention, the efficiency, precision and decision support capability of ocean spatial data analysis can be improved.

The invention provides a network flow data packet balanced loading method and device and a medium, and relates to the technical field of network flow data packet balanced loading, and the method comprises the steps: determining a pressure index used for representing the overall balanced state of a system; judging whether the system is in an equilibrium state or not according to the numerical range of the pressure index; if the system is not in the equilibrium state, adjusting the transfer rate through a preset feedback control algorithm; the control quantity of the feedback control algorithm is comprehensively determined according to the pressure index, the network card cache area occupancy rate relative to a target value and the error of the disk falling cache area occupancy rate relative to the target value; transferring the network flow data packet temporarily stored in the network card cache region to a disk falling cache region according to the adjusted transfer rate; distributing corresponding hard disk identifiers for the network flow data packets in the disk-falling cache region, and writing the network flow data packets into corresponding hard disks in batches; according to the invention, the operation stability and reliability in a high-load or performance heterogeneous environment can be enhanced.

This invention discloses a collaborative method for logic structure partitioning and netlist optimization in multi-core FPGAs, belonging to the fields of electronic design automation and integrated circuits. This invention introduces physical partitioning constraints during the logic synthesis stage, establishing an interconnect-aware synthesis cost function that integrates area, timing, and cross-core interconnect costs. The method includes: pre-partitioning the netlist and anchoring its locations using a hypergraph partitioning algorithm; real-time selection and optimization operators based on dynamically adjusted interconnect penalty coefficients during logic transformation; implementation of suppression mechanisms for high interconnect cost operations; and active logic cloning and topology reconstruction for long-distance cross-core paths. This invention breaks the traditional boundaries between logic synthesis and physical partitioning, effectively reducing the number of cross-core interconnects at the source through closed-loop iteration of micro-optimization and macro-constraints, significantly reducing the risk of wiring congestion, and improving the operating frequency and performance of multi-core FPGA systems.

This invention relates to the field of data processing technology, and more particularly to a BOP (Browser-Operated Programming) click sending method. This method is used in a BOP system and employs a network load balancer as the data interface. Upon receiving a user click request, the method first sends the user click request to a preset service cluster. Then, in response to the triggering of a preset channel click script, it writes the user click requests from the corresponding service cluster into a distributed stream processing platform for data grouping. Finally, it sends the grouped user click requests to their respective databases for storage. Compared to existing technologies, this invention overcomes the problem of difficulty in integrating and storing click data with a BOP system.

According to the computing chip, the data transmission method and the related equipment provided by the embodiment of the invention, the computing chip comprises a tensor computing unit and a plurality of execution units, and a hardware direct connection path independent of a shared memory is configured between the tensor computing unit and a storage unit of each execution unit. The hardware direct connection path is used for carrying out data transmission between the tensor calculation unit and the corresponding execution unit, hardware-level direct transmission of data between heterogeneous calculation units is achieved, and therefore the process that data must be transferred through a shared memory in a traditional hybrid architecture is effectively avoided. According to the method and the device, the additional memory access delay and explicit synchronization overhead generated by the write-back-synchronization-add process are eliminated, so that the data transmission path is remarkably shortened while the instruction sending process is simplified, and then the pipeline parallel execution efficiency and the overall data throughput performance of a computing chip are improved when the computing chip executes a large-scale hybrid computing task.

This invention discloses a 3D stacked memory and a high-bandwidth architecture. It includes a logic control chip and a DRAM chip. The logic control chip is equipped with a command decoding unit, a row-column decoding unit, and a mode register unit. The DRAM chip is equipped with memory cells. A vertical interconnect structure is formed between the DRAM chip and the logic control chip. The control and configuration system transmits data to the memory cells through this vertical interconnect structure. In other words, this technical solution simplifies the DRAM chip structure by centralizing the command decoding unit, row-column decoding unit, and mode register unit within the logic control chip, thereby freeing up more space for memory cell layout and effectively increasing the storage capacity of the DRAM chip. Simultaneously, the vertical interconnect structure between the logic control chip and the DRAM chip enables high-speed, stable data transmission and a three-dimensional stacking structure, thus meeting the demands of high-performance computing, artificial intelligence, and other applications for large-capacity, high-bandwidth, and low-latency memory devices.

The present invention relates to a multi-step recursive encoder logic circuit design method and device, characterized in that the logic circuit of the multi-step recursive RS encoder is used to implement a k-step parallel encoding method, and the design method comprises the steps of: using a first formula to express the nth check element register R n The value R after the kth clock cycle n (k); The first formula is: R n (k) = R n‑1 (k‑1)+[R 2t‑1 (k‑1)+d k‑1 ]·g n (n≥1), where n=0, 1, …2t-1, t is the maximum number of error correction code elements, k is the number of recursive steps, d k represents the kth data input into the multi-step recursive RS encoder, g n is the constant coefficient of the nth multiplier; according to the first formula, the g n The k×k constant matrix is ​​constructed, and the logic circuit of the multi-step recursive RS encoder is determined by the matrix. The invention is used to reduce the iteration cycle required for encoding and improve the encoding speed.

The utility model relates to the technical field of underwater detection, and discloses a wireless transmission underwater acoustic signal acquisition simple buoy device which comprises a floating platform floating on the water surface, and a solar panel supported by a fixing support is arranged on the floating platform; a waterproof box is arranged on the top surface of the floating platform, a signal acquisition module and a power supply module are arranged in the waterproof box, the signal acquisition module is electrically connected with the hydrophone sinking underwater, and a plumb bob used for stabilizing the floating platform is arranged below the floating platform; the signal acquisition module is used for wirelessly transmitting the underwater sound data acquired by the hydrophone to a far end after storing the underwater sound data; the solar panel charges the power supply module, and the power supply module supplies power to the signal acquisition module. According to the utility model, the FPGA and ADC architecture is adopted, and the ADC is driven in parallel to optimize the sampling rate, so that the data throughput can be improved, and multi-channel acquisition can be realized.

The invention discloses a DNA data storage efficient coding circuit, comprising: an enable signal output by a control module connected to a base conversion module, a rotation coding module and a linear cyclic code coding module, for controlling the sending of data input and output requests and the current status display of the remaining modules. The 32-bit 15-decimal number output by the base conversion module is connected to the rotation coding module, for converting 31-bit binary data into 32-bit 15-decimal numbers. The 32-bit 15-decimal number output by the rotation coding module is connected to the rotation coding module, for converting the 32-bit 15-decimal data into binary data suitable for DNA base synthesis through cyclic shift and accumulation operations. The linear cyclic code coding module is used to input the continuously input 32-bit data into a linear cyclic code coding unit through serial-to-parallel conversion, merging, etc. to obtain a coding codeword with a certain error correction capability. The DNA storage-specific coding algorithm hardware circuit proposed by the invention can achieve high data throughput while occupying less hardware logic resources.