1172 results about "Data path" patented technology

The invention discloses a processor and electronic equipment. The processor includes a computing unit including a tensor core configured to perform a matrix multiplication operation using a scaling factor, and a memory, the computing unit further including a scaling factor processing module configured to determine and cache a scaling factor for each tensor associated with the matrix multiplication operation, the computing unit further comprises at least one storage module arranged on a data path between the tensor core and the memory, and the at least one storage module is exclusively occupied by the tensor core when the tensor core executes tensor related operation. And the scaling factor processing module is arranged on the at least one storage module. At present, scaling factors and floating-point number quantization are completed by a vector calculation core, so that performance is reduced, and delay becomes high, and a scaling factor processing module arranged on a storage module in a calculation unit can improve the overall execution efficiency of low-precision matrix multiplication using the scaling factors.

The invention relates to the technical field of low-power-consumption AI processors, and discloses a novel real-time data processing method and chip for calculating a low-power-consumption AI processor, and the method comprises the steps: carrying out the neural mimicry classification processing of a calculation task inputted by the low-power-consumption AI processor, and obtaining a calculation task feature matrix; performing multi-dimensional mapping operation on the calculation task feature matrix to obtain a heterogeneous calculation space vector; performing core resource allocation based on the heterogeneous calculation space vector to obtain a dual-mode processing unit configuration matrix; constructing a storage and calculation integrated data path based on the dual-mode processing unit configuration matrix to obtain a parallel calculation data flow diagram; executing dynamic voltage frequency mapping on the parallel computing data flow diagram to obtain a power consumption optimization control vector; and inputting the power consumption optimization control vector into the trained pulse neural network model to carry out computing power load balancing calculation and generate computing power load balancing parameters, and the method improves the real-time data processing capability of the low-power AI processor.

A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.

The invention discloses a computing platform management system based on artificial intelligence, particularly relates to the technical field of distributed storage resource dynamic allocation, and is used for solving the problem of resource allocation oscillation caused by hardware performance difference and dynamic attenuation in the prior art. Acquiring the hardware performance, the load state and the data path of the storage node through a real-time acquisition module; the entropy judgment module calculates a path topology entropy and triggers a reconstruction instruction; the resonance analysis module analyzes the group association strength of hardware performance degradation and marks a resonance node group; the weight generation module fuses the parameters to generate a dynamic allocation weight; the error compensation module optimizes a weight coefficient in combination with historical error data; the migration execution module executes migration according to the weight and limits the load of the resonance node; through cooperative regulation and control of topological entropy monitoring and hardware resonance analysis, local oscillation diffusion is inhibited, unnecessary migration operation is reduced, system stability is improved, and the service life of hardware is prolonged.

The invention discloses a full-stack NPU system supporting a multistage fault mitigation mechanism, and the system comprises a plurality of NPU functional blocks which are used for executing a neural network calculation task; the plurality of hardware protection modules are used for providing error detection and correction capabilities for at least one NPU functional block in the NPU or a data path in the NPU; and a control mechanism for coordinating operation of the plurality of hardware protection modules. By means of the scheme, NPU functional block calculation errors or data path transmission errors caused by hardware faults and the like can be detected and corrected in time, wrong calculation results are prevented from being continuously used or output, and the accuracy of final results is guaranteed. Meanwhile, even if part of hardware breaks down, an error correction mechanism can also cover errors to a large extent, normal operation of the system is maintained, the overall availability and task success rate of the system are improved, and therefore the reliability and robustness of the NPU are remarkably improved.

The invention relates to the technical field of digital marketing, and discloses an omni-channel marketing funnel intelligent attribution model and an automatic budget distribution system, and the model comprises a data collection module which is used for collecting data through a contact recording device and a user identification device which are disposed at a marketing terminal, and a behavior tracking device and a channel classification device which are disposed at a user side. Acquiring information such as multi-channel marketing contact interaction data, user behavior data and channel types; the path analysis module realizes data path analysis through time sequence synchronization of a time alignment unit, feature matching of a path association unit and dynamic adjustment of a computing power scheduling unit; the attribution calculation module generates the conversion attribution weight of each channel based on the matching data; and the budget mapping module establishes a dynamic mapping relationship between the weight and the budget and updates the dynamic mapping relationship. The system outputs the attribution result through the model application module, and the budget execution module distributes the budget according to the dynamic mapping, so that the channel contribution can be accurately evaluated, the scientific distribution of the marketing budget is realized, and the marketing efficiency and the rate of return on investment are improved.

Methods, systems, and devices for data management are described. A data management system (DMS) may obtain metadata associated with a snapshot stored by the DMS and including information associated with data paths in the snapshot. The DMS may scan an index registry for identifiers of the data paths to determine whether the index registry includes namespace and hierarchical index information that map the data paths to path identifiers and to descendent data paths within the snapshot, respectively. The DMS may generate term and count index information based on the metadata. The term and count index information may map terms to data paths that include the terms and numerical values associated with the terms, respectively. The DMS may store, in the index registry, the term and count index information with an identifier of a corresponding index group. The namespace and hierarchical index information may be common to multiple index groups.

The invention belongs to the field of eye movement data tracking, particularly relates to a pilot eye movement tracking method, system and equipment based on multi-camera fusion and a storage medium, and aims to solve the problems that in the prior art, the visual angle of a traditional eye tracker is limited, and sight estimation errors are caused by head movement. The method comprises the following steps of: constructing a multi-view visual perception network by deploying multiple cameras and eye trackers in a cockpit; multi-source data space-time alignment is achieved through space coordinate system mapping and time synchronization, and head motion errors are compensated by combining dynamic cutting of eye interested areas and three-dimensional head posture estimation. The geometric path generates a physical driving vector based on iris fitting and an eyeball model, and the data path regresses the vector through a deep learning model; and converting to a world coordinate system through a head posture after fusion. High-precision data of the eye tracker is preferentially adopted in the central area, and field-of-view data of the system is expanded in the edge area. According to the invention, the tracking precision under field angle coverage and motion interference is obviously improved.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, provided is a method for operating a network node such as an application function (AF) node in a wireless communication system, the method comprising the steps of: generating an AF request including information related to one or more data path latencies; and transmitting the information related to the one or more data path latencies to a session management function (SMF) node through a network exposure function (NEF) node.

Disclosed are systems, apparatuses, methods, and computer-readable media for machine learning of data path rules for gateway services. A method includes: receiving a command related to a configuration of a firewall of a gateway; obtaining a subset of rules from a collection of rules to apply to a second instance of the firewall that replaces a first instance of the firewall, wherein the collection of rules are expressly associated with the firewall of the gateway; loading the subset of rules and the second instance of the firewall; and when the first instance is available after loading the subset of rules, processing network traffic of the gateway based on the subset of rules

Disclosed herein are methods and systems to generate code for a workflow. A non-limiting example of a method comprises executing, by a processor, a large language model, which receives an input of an intent associated with a workflow and provides a machine-readable description by: identifying, by searching a hierarchical data structure using a vector embedding associated with the intent, an object corresponding to the intent; identifying a set of data paths within the hierarchical data structure to retrieve the identified object; and generating the machine-readable description, the machine-readable description describing the object and at least one data path within the set of data paths; and generating, by the processor, code for the workflow using the machine-readable description.

Embodiments of the invention provide a tree form data processing method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of determining selected information corresponding to a selected instruction; monitoring a dragging action of a mouse cursor, predicting a real-time terminal point position of the model through a dragging terminal point, and dynamically rendering a visual prompt layer at the same time; when monitoring that the dragging action is a stop action, determining the placed data and obtaining a data path, and when the data type of the to-be-dragged data is a combination type, obtaining a data set of a to-be-dragged combination where the to-be-dragged data is located and an index position where first data in the to-be-dragged combination is located, assigning the index position to a tail end index in a data path of the data to be dragged; and traversing data elements adjacent to the placed data in the data path of the placed data to update the key value distribution. According to the method, the defect of performance optimization in the process of executing the dragging action by the preset tree form is effectively solved, and the experience feeling in the process of operating the preset tree form by a user is remarkably improved.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

A method and system to provide secure fine-tune training and inferences for large language models using a Fully Homomorphic Encryption (FHE) process is disclosed. A trained public large language model with a matrix of public weights is stored in plaintext. A private training set of proprietary data is stored as a set of encrypted weights. An encrypted query is received. The encrypted query is processed via an encrypted data path with the set of encrypted weights for trained large language model. The encrypted query is processed via a plaintext data path with the set of public weights in plaintext for the trained large language model. A low rank adaptation (LoRA) approach may be used in fine-tuning the model to reduce computational complexity and memory access. Encrypted results are obtained from the processing via the encrypted data path and the plaintext weight path.

An example method for verifying data integrity in a storage system includes detecting a data access operation that processes data via a data path between a client and a storage device of the storage system, the data path including at least a first and a second processing stage; generating, based on the data access operation, a first instance of a first checksum at a first time based on a first intermediate representation of the data; generating, a second instance of the first checksum at a second time; modifying, based on the second checksum being different from the first checksum, the first intermediate representation to generate a corrected first intermediate representation; generating, based on the corrected first intermediate representation, a third checksum; and directing, based on verifying that the third checksum matches the first checksum, the second processing stage to generate the second intermediate representation.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

Disclosed are systems, apparatuses, methods, and computer-readable media for asynchronous execution of data path service using network fibers. A method includes: based on receiving a first packet within a service for transmitting the first packet to a destination location, processing a first portion of the first packet in a processor based on execution of a first fiber until a first hardware call is reached; sending the first packet to a first circuit for processing the first packet based on the first hardware call; and processing a portion of a second packet associated with a second fiber while the first packet is processing in the first circuit. The systems and apparatuses prevent heavy processing of content from blocking other content.

The invention discloses a body intelligent controller architecture based on an end side intelligent model and an operation method, and belongs to the technical field of industrial body intelligence. According to the architecture, a CPU, a GPU and an FPGA are integrated by adopting a heterogeneous multi-core processor, and high-speed interconnection is realized through a star-type + NoC hybrid topology; a multi-level task scheduling mechanism is constructed based on a real-time operating system, and it is ensured that control tasks are executed preferentially. End-side visual model lightweight (YOLOv5s model parameters are reduced to 3.5 M) and FPGA hardware acceleration (control instruction time delay is 10ns) are innovatively realized on an algorithm framework layer, and a transmission bottleneck is eliminated through a zero-copy data path. The system supports model hot switching less than or equal to 10ms and FPGA bit stream online updating less than or equal to 50ms, and has MD5 check and an automatic rollback mechanism. Compared with a traditional separation type scheme, the processing time delay is reduced by 25 times, the hardware cost is reduced, the size is reduced, and the real-time performance, reliability and deployment flexibility of the industrial robot and other intelligent agents with the body are remarkably improved.

An embodiment selects, using performance data of a plurality of paths, a first path, each path comprising a data communication path from a first network endpoint through a subset of a plurality of network elements in a data communication network to a second network endpoint. An embodiment adjusts a packet header of a data packet, wherein a parameter setting in the adjusted data packet header causes a first network element in the data communication network to forward the adjusted data packet to a next network element in the data communication network along the first path. An embodiment sends the adjusted data packet, wherein the adjusted data packet causes a first subset of the plurality of network elements in the data communication network to forward the adjusted data packet to the second network endpoint along the first path.

The invention relates to the field of multi-agent control, and provides an unmanned aerial vehicle patrol flight obstacle avoidance method based on deep reinforcement learning. Aiming at the problems of large work amount, incomplete coverage and poor dynamic obstacle response caused by manual route configuration due to dependence on point cloud data path planning in the prior art, the scheme fuses target detection and radar ranging to obtain obstacle types, positions and distance information; constructing a local obstacle avoidance potential field based on an artificial potential field method, calculating an obstacle avoidance direction through a gravitational repulsion gradient, and introducing a dynamic adjustment mechanism to avoid a local minimum value; designing a local dynamic reward function in combination with the target equipment position, and generating a path adjustment signal by integrating the target approaching progress of the unmanned aerial vehicle and the obstacle avoidance demand; a global reward function is constructed to evaluate the task completion degree, the path efficiency and the obstacle avoidance safety, and a macroscopic strategy optimization basis is formed; a deep neural network architecture is adopted to train an autonomous obstacle avoidance strategy, and an autonomous decision in a dynamic environment is realized through experience playback and an attention mechanism optimization model.

The invention is applicable to the technical field of integrated circuit design, and provides a method for repairing crosstalk noise violation on a data path, which comprises the following steps of: reading a crosstalk noise violation report of a static time sequence analysis STA tool; finding an interconnection line corresponding to each violation in the report from a layout wiring tool, and finding adjacent interconnection line position information and connected logic unit information of the current interconnection line; selecting a corresponding repairing scheme according to the specific conditions of the interconnection lines and the connected logic units, and executing and adjusting the repairing scheme so as to repair crosstalk noise on a data path; and after a round of repair is completed, if crosstalk noise violation is also detected in the STA tool, the steps need to be executed again until all crosstalk noise problems are solved. According to the method provided by the invention, the crosstalk problem is efficiently identified and solved through an automatic process, the signal integrity and the function correctness of circuit design are ensured, and compared with a traditional scheme, the method is more targeted, and the gain brought by single change is favorably improved.

The subject application relates to separate command address (SCA) protocol-based memory controllers. For instance, a method may include receiving, by a separate command address (SCA)-based memory controller, a plurality of commands, scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues, converting the scheduled plurality of commands into SCA-based commands, selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution, and executing in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.

Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic while applying injection limits to different traffic classes at an ingress edge port. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. Furthermore, an edge switch can dynamically allocate the ingress port bandwidth among the traffic classes that are active at a given moment.

In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

The embodiment of the invention provides a core grain verification method and related equipment. The core grain verification method comprises the following steps: acquiring data path modules of a plurality of core grains in a to-be-tested design and module verification environments corresponding to the data path modules; the data path modules of the plurality of core particles are in heterogeneous design; the module verification environment is used for indicating a verification environment corresponding to the data path module; compiling the obtained data path module of each core particle into different file libraries and connecting the file libraries to a top layer module of the to-be-tested design; combining the obtained module verification environments corresponding to the data path modules of the core particles into a top layer verification environment; and based on the top layer verification excitation of the top layer verification environment, executing verification of data path modules of a plurality of core particles in a to-be-tested design. According to the scheme, the test accuracy of the test scene of the cross-heterogeneous data path module can be ensured.

The embodiment of the invention provides a cross-clock domain data transmission method and device. The method comprises the following steps: sampling a first clock of a first clock domain by using a second clock of a second clock domain and outputting a sampling signal; moving a second clock edge of the second clock according to the sampling signal to enable the second clock edge to move from one side of a first clock edge of the first clock to the other side of the first clock edge of the first clock; repeatedly executing the step of sampling the first clock by the second clock and outputting the sampling signal and the step of moving the second clock edge of the second clock according to the sampling signal, so that the second clock edge reciprocates on the two sides of the first clock edge; judging whether a clock locking signal is generated or not; after the clock lock signal is generated, data transmission in a data path between the first clock domain and the second clock domain is enabled. The method and the device do not depend on a traditional asynchronous handshake mode or buffer mechanisms such as FIFO, delay needed by synchronous logic is avoided, and the method and the device are suitable for the requirement of high-speed communication.

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.