447 results about "Data path" patented technology

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

A method for managing data includes: receiving a file analysis request from a user, in which the request includes merging criteria, a first data path to access a first file, a second data path to access a second file, and a third data path to access a third file; obtaining the first file using the first data path, the second file using the second data path, and the third file using the third data path; analyzing the merging criteria; inferring, based on a determination, that the second file is suitable to be merged with the first file and the third file is not suitable to be merged with the first file; merging, based on the merging criteria, the first file and the second file to generate an output file; and initiating, via a graphical user interface (GUI), displaying of the output file to the user.

The invention provides a large model training system based on CPU-GPU double optimizers and SSD unloading, and belongs to the technical field of computers. The system comprises a parameter division manager, a CPU optimizer state exchanger, a CPU optimizer, a GPU optimizer state exchanger and a GPU optimizer, large model parameters are divided into a plurality of subgroups through the parameter division manager, and the subgroups are further divided into a CPU updating part and a GPU updating part; a CPU and GPU double optimizer structure is introduced, a double-SSD architecture is adopted to design an independent data path, GPU-CPU collaborative updating is achieved, optimizer state transition between a GPU or a CPU and an SSD is managed, I / O conflicts are eliminated, the GPU idle time is shortened, the influence of SSD read-write high delay is relieved, load balancing is guaranteed, and the training throughput is improved.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention discloses a multichannel ultrasonic transducer phased array driving method based on direct memory access. The method comprises a waveform data buffer length determination step, a data path construction step, a phase parameter calculation step, a waveform data synthesis step and a DMA driving step. An independent DMA channel is configured for each GPIO port or each group of GPIO ports corresponding to the transducer array by utilizing the DMA characteristic of a universal microcontroller, and buffer data is transmitted to the output data registers of the GPIO ports automatically and periodically by DMA hardware, so that multi-channel driving signals with accurate frequency and controllable phases are generated in parallel under the condition that CPU (Central Processing Unit) intervention is not needed. According to the invention, high-precision time sequence control comparable with an FPGA (Field Programmable Gate Array) scheme is realized with extremely low hardware cost and CPU (Central Processing Unit) resource occupation, the problem of time sequence jitter of an existing MCU (Microprogrammed Control Unit) scheme is solved, and the method has high stability, high efficiency and excellent expandability.

The invention relates to a data loading method and device, a storage medium and equipment, the method is used in an intelligent calculation data processing system comprising a host, a CSD and a SmartNIC, and a PCIe P2P data path is established between the CSD and the SmartNIC; the method comprises the steps that a host generates collaborative descriptors and respectively issues the collaborative descriptors to a CSD and a SmartNIC; the CSD reads source data from a storage medium according to source address information in the collaborative descriptor, executes a processing operation corresponding to the first operator identifier to obtain intermediate data, and directly transmits the intermediate data to a storage area of the SmartNIC through a PCIe P2P data path; and the SmartNIC executes a processing operation corresponding to the second operator identifier on the intermediate data to obtain target data, and transmits the target data to the computing device according to the target address information in the collaborative descriptor.

The invention relates to the technical field of equipment operation monitoring and management, in particular to an Internet of Things equipment intelligent energy consumption management method and system based on artificial intelligence. Comprising the following steps: S1, constructing and training an energy consumption prediction network for predicting an energy consumption condition in a future preset time period, judging a condition that a difference between a predicted value and a real monitoring value exceeds a preset threshold value as an energy consumption abnormal condition, and entering S2 when the energy consumption abnormal condition exists; and S2, constructing a wireless communication networking diagram of the Internet of Things equipment and the base station, taking the base station and the Internet of Things equipment as nodes, and taking a data path between the equipment as an edge to simulate a real communication environment of the Internet of Things equipment. According to the method, the communication networking diagram where the Internet of Things equipment is located is constructed, the common characteristics of the sub-diagrams in the same scene are extracted and applied, the cause of energy consumption abnormity is further mined, the abnormity detection accuracy is improved, and the beneficial effects are provided for subsequent energy consumption management of the Internet of Things equipment.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

The present application relates to a data replay method, a data processing unit, a network interface card, a device, and a storage medium. The method comprises: when a storage stack is restarted, acquiring a replay-pending request queue from a persistent memory, the replay-pending request queue being a queue obtained by mapping a transmission buffer area into the persistent memory, and the transmission buffer area being used for receiving a request from a host side; on the basis of the replay-pending request queue, acquiring a replay-pending request from the persistent memory; and resending the replay-pending request to a target acceleration component directed to a storage device, so as to instruct the storage device to store target data which resides in the persistent memory and corresponds to the replay-pending request. In the method, a request queue, a request, and data corresponding to the request are stored in the persistent memory in advance, and if the storage stack is restarted, the replay-pending request is recovered from the persistent memory, eliminating the need for DMA and encryption / decryption techniques, and shortening an interruption duration of a storage data path, thereby improving data storage efficiency on the host side.

A compute tile is described. The compute tile includes compute engines and a general-purpose (GP processor coupled with the compute engines. Each of the compute engines includes a compute-in-memory (CIM) hardware module. The CIM hardware module is configured to store weights corresponding to a matrix and to perform a vector-matrix multiplication (VMM) for the matrix. The GP processor is configured to control the compute engines, to receive output of the VMM for the matrix from the compute engines, and to perform a nonlinear operation on the output. The compute engines are addressable by data movement initiators. Data may be moved to and / or from the compute engines in data paths that bypass the GP processor.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention discloses a data path structure suitable for cross-domain interaction of high-performance PCIe non-transparent bridge equipment. The data path structure comprises external equipment, an upstream endpoint, a downstream endpoint, a network interface controller connection network, a first bypass module group and a second bypass module group, the external equipment, the upstream endpoint, the network interface controller connection network and the downstream endpoint are sequentially in communication connection, the upstream endpoint and the downstream endpoint are the same in structure, the upstream endpoint is in communication connection with the first bypass module group, and the downstream endpoint is in communication connection with the second bypass module group; and the first bypass module group and the second bypass module group have the same structure. According to the data path structure provided by the invention, through mutual cooperation of the new path and the old path, the overall performance of the non-transparent bridge can be improved, and then the data path structure adapts to high-performance PCIe cross-domain transmission under high load and large flow.

The invention discloses a data-intensive workflow dynamic task allocation method and system oriented to cloud-edge cooperative computing, and relates to the technical field of cloud computing and edge computing collaboration.The method comprises the steps that workflow and cloud-edge resources are modeled in a unified mode, and a comprehensive cost function containing time, economy and energy consumption is defined; analyzing the workflow to obtain a conflict task set and a maximum data path set; in combination with resources and network states monitored in real time, candidate nodes are filtered according to data privacy constraints, edges or cloud nodes with the minimum comprehensive cost are selected for tasks for allocation, and sorting is performed according to priorities during multiple tasks; the system comprises a resource monitoring module, a workflow analysis and preprocessing module, a cost evaluation module and a dynamic scheduler module, the modules cooperate to realize dynamic allocation, the problems of resource heterogeneity, network dynamic and the like under cloud edge cooperation are solved, multi-objective optimization and privacy protection are balanced, and the workflow execution efficiency is improved.

The invention relates to the technical field of satellite navigation and time synchronization, in particular to a satellite clock error time sequence prediction method and system based on deep reinforcement learning. According to the method, a noise gating convolution module is adopted to extract features, and the features comprise a data path, a gating path and a noise sensing path; the noise sensing path is used for extracting local frequency jitter of the historical clock error sequence and performing weighted statistics to obtain background noise intensity; generating a self-adaptive gating coefficient by combining the gating path with the background noise intensity; and the data path is used for performing expansion convolution processing on the historical clock error sequence to obtain convolution features, and multiplying the convolution features by the adaptive gating coefficient to obtain effective features as output of the noise gating convolution module. According to the invention, the background noise intensity of satellite clock error data can be sensed in real time; by dynamically adjusting the gating threshold, false features can be filtered in a strong noise environment, tiny clock difference features can be reserved in a low noise environment, and the anti-noise capability in a non-stationary environment is improved.

To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input / output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process. To more quickly train the memory dies and determine the timing offset for an unmatched data output architecture, replica circuits for the data path and the clock path can be introduced on to the memory dies.

This application discloses a method, apparatus, electronic device, and storage medium for splitting a storage cluster, relating to the field of computer technology, particularly to artificial intelligence fields such as cloud computing, distributed storage, and big data processing. The specific implementation scheme is as follows: The data path of the target resource in the original storage cluster is adjusted so that requests to access the target resource are sent to the target node in the original storage cluster; the target node is network isolated; the target node is restarted, and in response to the target node's target startup parameter being set to the target value, the target node is split from the original storage cluster as a new storage cluster; wherein, the target startup parameter is a parameter used to force a node to start as a new single-node cluster; the target node is removed from the original storage cluster, and the network isolation of the target node is lifted.

A method (300) of storing semi-structured data (12U) includes receiving user data (12) comprising semi-structured user data from a user (10) of a query system (150). The method includes receiving an indication (14) that the semi-structured user data fails to include a fixed schema. In response, the method further includes parsing the semi-structured user data into a plurality of data paths (210) and extracting a data type (220) associated with each respective data path of the plurality of data paths. The method additionally includes storing the semi-structured user data as a row entry in a table (204) of a database in communication with the query system, wherein each column value associated with the row entry corresponds to a respective one of the plurality of data paths and the data type associated with the respective data path.

This invention discloses a bypass transmission architecture for encrypted network interface cards (NICs) based on parallel feature extraction. The architecture includes: a packet stream input interface, a control path unit, a data path unit, a decision window merging unit, a fragmentation-aware incremental checksum correction engine unit, and a security control unit. This invention can reduce forwarding latency, improve transmission determinism and resource utilization, and enhance packet forwarding efficiency in high-speed network scenarios. By using a deterministic delay storage module that matches worst-case latency, timing synchronization between control flow and data flow is achieved, reducing the risk of timing races and rule misjudgments. Simultaneously, the fragmentation-aware incremental checksum correction engine reduces the risks of insufficient fragmentation packet compatibility, checksum miscalculations, and resulting packet loss in traditional solutions.

The invention provides a 24-bit intermediate accumulation processing method and device for NPU convolution operation and a server, and relates to the technical field of neural networks, and the method comprises the steps: determining data path information of original data according to a multiplication and addition calculation result between a preset weight and an activation value corresponding to the input original data when a neural network processor NPU carries out convolution operation, the preset accumulation frequency corresponds to the data path information; the data path information is compared with a preset data path threshold value, a target processing strategy of the original data is determined according to a comparison result, and the target processing strategy comprises a low input bit width processing strategy and a high input bit width processing strategy; and performing segmented accumulation processing on the original data according to a preset accumulation frequency, and executing 24-bit intermediate value read-back, addition and write-back processing corresponding to the target processing strategy to obtain a target convolution operation output result. According to the method, the operation cost can be reduced while the error is reduced.

An apparatus, system, and method are provided that improve communication between a memory device and a controller. A data communication apparatus includes a transceiver coupled to a data path and configured to send or receive data over the data path, and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether any device is allowed to occupy the data path. The interrupt circuit generates an interrupt signal to prevent another device from accessing the data path in response to an activation signal to send or receive data by the transceiver.

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A memory device, a memory system, and a method for data computation using the memory device are provided. The memory device includes an array of memory cells, and peripheral circuits coupled to the memory cells are provided. The peripheral circuits include a page buffer configured to store first data transmitted from the data interface of the memory device and to sense second data from the array of memory cells. The peripheral circuits further include at least one processing unit coupled to the page buffer via the peripheral circuits' data path bus and configured to perform computations based on the first and second data. The peripheral circuits further include control logic configured to program the second data into the array of memory cells.

The present disclosure relates to the field of semiconductor, and provides a memory for reducing power consumption of the memory without increasing memory area. The memory comprises a memory array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the memory array and the peripheral circuit for data transmission between the memory array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in a data transmission direction; a power supply end of the first data path is electrically connected to a first transmission line, and a ground end is electrically connected to a second transmission line; a power supply end of the second data path is electrically connected to the second transmission line, and a ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

Methods, systems, and devices for transfer command power gating within a memory system are described. A memory device may dynamically activate data path circuitry within the memory device according to an operation to be performed at the memory device. In response to receiving signaling that indicates a transfer of data stored in the memory device, the memory device may generate a power gating signal associated with activation of the data path circuitry. The signaling may include a command from a controller before a data transfer, a preamble associated with the data transfer, or both. The memory device may transfer the data via the data path using the activated data path circuitry in response to the signaling. The memory device may receive second signaling to deactivate the data path circuitry after the data transfer is complete to reduce power consumption and improve performance.

The invention discloses a trusted start control method for a modular separation design embedded system, the embedded system comprises a core board and a special bottom board, the core board is integrated with a processor and a first BIOS, and the special bottom board is integrated with a trusted computing module, a second BIOS, an analog switch and a chip selection controller; the method comprises the following steps that after the embedded system is powered on, the trusted computing module prevents the processor from being started through a control signal, and the analog switch is controlled to switch a data path of the second BIOS to the trusted computing module; the trusted computing module reads the boot firmware in the second BIOS for trusted measurement, if measurement succeeds, the analog switch is controlled to switch a data path of the second BIOS to the processor, and the processor is allowed to be started; if the measurement fails, the processor is continuously prevented from being started. According to the method provided by the embodiment of the invention, the trusted root is preferentially started and actively measures the boot firmware, the code executed by the processor is ensured to be trusted, and a trust chain is established from the source.

The invention discloses a distributed data processing method in a local area network based on a UDP (User Datagram Protocol), which comprises the following steps: a distributed monitoring node sends a broadcast to the local area network, and a computing node in the local area network reports own identity information to the distributed monitoring node after receiving the broadcast; after a user initiates a data processing task, the task is sent to a target computing node in a structured instruction form through a UDP, the structured instruction comprises a task ID input data path algorithm type parameter set and priority, and a distributed monitoring node dynamically allocates the task according to the comprehensive load score of each node; the computing node sends a heartbeat message to the distributed monitoring node according to a heartbeat cycle, wherein the heartbeat message comprises a node identifier, a current running state, a current task execution identifier and node resource occupation summary information; according to the method, lightweight and low-delay distributed task scheduling can be realized. And meanwhile, node fault detection and task automatic recovery are realized, manual intervention is avoided, and safe and reliable execution of the task is guaranteed.