1518 results about "Data path" patented technology

The invention discloses a processor and electronic equipment. The processor includes a computing unit including a tensor core configured to perform a matrix multiplication operation using a scaling factor, and a memory, the computing unit further including a scaling factor processing module configured to determine and cache a scaling factor for each tensor associated with the matrix multiplication operation, the computing unit further comprises at least one storage module arranged on a data path between the tensor core and the memory, and the at least one storage module is exclusively occupied by the tensor core when the tensor core executes tensor related operation. And the scaling factor processing module is arranged on the at least one storage module. At present, scaling factors and floating-point number quantization are completed by a vector calculation core, so that performance is reduced, and delay becomes high, and a scaling factor processing module arranged on a storage module in a calculation unit can improve the overall execution efficiency of low-precision matrix multiplication using the scaling factors.

A method for performing an application migration operation includes initiating the application migration operation to migrate an application from a source device to a target device, where the source device includes a source data migration agent and the target device comprises a target data migration agent. The method also includes initiating an active scan of network traffic at a transmission control protocol layer. The method further includes establishing a secure data path between the source device and the target device. In addition, the method includes beginning migration of the application from the source device to the target device using the secure data path. Moreover, the method includes making a first determination, using the active scan, that a data packet is associated with suspicious activity and rejecting the data packet based on the first determination.

The invention relates to the technical field of low-power-consumption AI processors, and discloses a novel real-time data processing method and chip for calculating a low-power-consumption AI processor, and the method comprises the steps: carrying out the neural mimicry classification processing of a calculation task inputted by the low-power-consumption AI processor, and obtaining a calculation task feature matrix; performing multi-dimensional mapping operation on the calculation task feature matrix to obtain a heterogeneous calculation space vector; performing core resource allocation based on the heterogeneous calculation space vector to obtain a dual-mode processing unit configuration matrix; constructing a storage and calculation integrated data path based on the dual-mode processing unit configuration matrix to obtain a parallel calculation data flow diagram; executing dynamic voltage frequency mapping on the parallel computing data flow diagram to obtain a power consumption optimization control vector; and inputting the power consumption optimization control vector into the trained pulse neural network model to carry out computing power load balancing calculation and generate computing power load balancing parameters, and the method improves the real-time data processing capability of the low-power AI processor.

A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.

A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).

A fabric control protocol (FCP) is a data transmission protocol that enables spraying of individual packets for a given packet flow across a data center from an ingress interface of the source data processing unit (DPU) across a plurality of parallel data paths of a logical tunnel in the network fabric to the egress interface of the destination DPU. The FCP has congestion control mechanisms used to determine a degree of congestion at the egress interface of the destination DPU and to modify a send window size at the source DPU based on the degree of congestion. Reliable FCP (rFCP) extensions provide reliability enhancements and improved failure resilience within the data center. The rFCP extensions provide an unsolicited mode for low latency operation with enhanced reliability mechanisms. The rFCP extensions provide failure resilience mechanisms to identify and avoid failed paths among multiple parallel data paths within the logical tunnel.

The invention discloses a computing platform management system based on artificial intelligence, particularly relates to the technical field of distributed storage resource dynamic allocation, and is used for solving the problem of resource allocation oscillation caused by hardware performance difference and dynamic attenuation in the prior art. Acquiring the hardware performance, the load state and the data path of the storage node through a real-time acquisition module; the entropy judgment module calculates a path topology entropy and triggers a reconstruction instruction; the resonance analysis module analyzes the group association strength of hardware performance degradation and marks a resonance node group; the weight generation module fuses the parameters to generate a dynamic allocation weight; the error compensation module optimizes a weight coefficient in combination with historical error data; the migration execution module executes migration according to the weight and limits the load of the resonance node; through cooperative regulation and control of topological entropy monitoring and hardware resonance analysis, local oscillation diffusion is inhibited, unnecessary migration operation is reduced, system stability is improved, and the service life of hardware is prolonged.

The invention discloses mixed precision multiply-add operation hardware, which comprises an input processing unit used for obtaining standard symbols, standard indexes and standard mantissas according to a pre-configured input format and unpacked input multiply-add operation factors, and obtaining input and output special value detection results; the floating point multiplier-adder is used for calculating an operation result after the operand multiplies the scaling factor and the offset is accumulated according to the symbol, the exponent and the mantissa of each multiplication-addition operation factor; and the output processing unit is used for obtaining a target format result according to a pre-configured output format, a rounding type and a normalization and rounding operation result, packaging the target format result according to a detection result and outputting the target format result, and by multiplexing a data path of the floating-point multiplier-adder, the chip area is saved, format conversion is integrated, a data stream is simplified, and the data processing efficiency is improved. The requirements for automatic reconstruction of the multiply-add operation unit according to input and output formats and quantization and inverse quantization of floating points and integers are met, and the reuse rate of computing resources is increased.

The invention discloses a full-stack NPU system supporting a multistage fault mitigation mechanism, and the system comprises a plurality of NPU functional blocks which are used for executing a neural network calculation task; the plurality of hardware protection modules are used for providing error detection and correction capabilities for at least one NPU functional block in the NPU or a data path in the NPU; and a control mechanism for coordinating operation of the plurality of hardware protection modules. By means of the scheme, NPU functional block calculation errors or data path transmission errors caused by hardware faults and the like can be detected and corrected in time, wrong calculation results are prevented from being continuously used or output, and the accuracy of final results is guaranteed. Meanwhile, even if part of hardware breaks down, an error correction mechanism can also cover errors to a large extent, normal operation of the system is maintained, the overall availability and task success rate of the system are improved, and therefore the reliability and robustness of the NPU are remarkably improved.

The invention relates to the technical field of digital marketing, and discloses an omni-channel marketing funnel intelligent attribution model and an automatic budget distribution system, and the model comprises a data collection module which is used for collecting data through a contact recording device and a user identification device which are disposed at a marketing terminal, and a behavior tracking device and a channel classification device which are disposed at a user side. Acquiring information such as multi-channel marketing contact interaction data, user behavior data and channel types; the path analysis module realizes data path analysis through time sequence synchronization of a time alignment unit, feature matching of a path association unit and dynamic adjustment of a computing power scheduling unit; the attribution calculation module generates the conversion attribution weight of each channel based on the matching data; and the budget mapping module establishes a dynamic mapping relationship between the weight and the budget and updates the dynamic mapping relationship. The system outputs the attribution result through the model application module, and the budget execution module distributes the budget according to the dynamic mapping, so that the channel contribution can be accurately evaluated, the scientific distribution of the marketing budget is realized, and the marketing efficiency and the rate of return on investment are improved.

Methods, systems, and devices for data management are described. A data management system (DMS) may obtain metadata associated with a snapshot stored by the DMS and including information associated with data paths in the snapshot. The DMS may scan an index registry for identifiers of the data paths to determine whether the index registry includes namespace and hierarchical index information that map the data paths to path identifiers and to descendent data paths within the snapshot, respectively. The DMS may generate term and count index information based on the metadata. The term and count index information may map terms to data paths that include the terms and numerical values associated with the terms, respectively. The DMS may store, in the index registry, the term and count index information with an identifier of a corresponding index group. The namespace and hierarchical index information may be common to multiple index groups.

The invention belongs to the field of eye movement data tracking, particularly relates to a pilot eye movement tracking method, system and equipment based on multi-camera fusion and a storage medium, and aims to solve the problems that in the prior art, the visual angle of a traditional eye tracker is limited, and sight estimation errors are caused by head movement. The method comprises the following steps of: constructing a multi-view visual perception network by deploying multiple cameras and eye trackers in a cockpit; multi-source data space-time alignment is achieved through space coordinate system mapping and time synchronization, and head motion errors are compensated by combining dynamic cutting of eye interested areas and three-dimensional head posture estimation. The geometric path generates a physical driving vector based on iris fitting and an eyeball model, and the data path regresses the vector through a deep learning model; and converting to a world coordinate system through a head posture after fusion. High-precision data of the eye tracker is preferentially adopted in the central area, and field-of-view data of the system is expanded in the edge area. According to the invention, the tracking precision under field angle coverage and motion interference is obviously improved.

A method for performing an application migration operation, the method includes initiating the application migration operation to migrate an application from a source device to a target device, where the source device includes a source data migration agent and the target device includes a target data migration agent. The method also includes initiating an active scan. Further, the method includes establishing a secure data path between the source device and the target device. Moreover, the method includes making a first determination, using the active scan, that the network traffic or the source performance metrics are indicative of suspicious activity and logging information about the suspicious activity. The method also includes making a second determination that the application migration operation is complete and terminating the active scan and the secure data path based on the second determination.

The invention provides a data consanguinity traceability analysis method based on a power grid data center. The method comprises the steps that an execution log is generated and collected based on Hive and YARN, a plurality of SQL statements are obtained based on the execution log, AST trees are constructed based on the SQL statements respectively, and a data consanguinity mapping relation and data node information are obtained based on the AST trees; and combining the same data nodes in the plurality of SQL statements based on an information entropy data alignment method, converting the data consanguinity mapping relation and the data nodes into a data consanguinity map based on Neo4j, and performing data path tracing on the data consanguinity map based on breadth-first search and an A * algorithm. Through the technical scheme of the invention, the occurrence position of problem data can be quickly and accurately positioned, the whole process of power grid data from acquisition, transmission, storage to analysis is transparent and traceable, and the requirements of enterprises for timeliness and reliability of data service in data are met.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, provided is a method for operating a network node such as an application function (AF) node in a wireless communication system, the method comprising the steps of: generating an AF request including information related to one or more data path latencies; and transmitting the information related to the one or more data path latencies to a session management function (SMF) node through a network exposure function (NEF) node.

An optical measurement system may improve the accuracy with which it estimates distances to surrounding objects by upgrading various aspects of its data path. Spatial resolution may be increased by subdividing histogram buckets or integration registers based on spatial location. Saturation at any point in the data path can be detected and used to stop counting photons in individual pixels, which can then be normalized after a measurement is over. Multiple peaks can be detected using recursive or iterative techniques to identify a largest remaining peak at each stage. Instead of iterating through the histogram memory multiple times, a threshold can be pre-calculated based on an estimated ambient noise level, and peaks can be detected in a single pass.

The invention relates to the technical field of processor design and test, and discloses an instruction sequence generation method for verifying floating point operation of a processor, which comprises the following steps: constructing a floating point test coverage model, generating a floating point test database, and constructing a basic RISC-V instruction sequence generator; adding a register updating mechanism bound with a memory on the basis of the basic instruction RISC-V sequence generator, and generating initialized data of the memory; and injecting the generated instruction machine code and the memory initialization data into the memory of the processor to be verified for simulation, and comparing the execution track obtained by simulation with the execution track of the instruction set simulator to find potential errors in the processor. According to the method, an efficient coverage model is constructed to generate representative floating point test data, a floating point data path of the processor can be verified more comprehensively, the defects of an existing method in the aspect of floating points in the RISC-V instruction generation process are overcome, and potential design defects in the processor are found.

The invention provides a distributed data path combination equivalence verification method and a distributed server, and the method comprises the steps: carrying out the rewriting of two to-be-verified data path circuits, and obtaining two circuit description files with similar circuit structures; constructing a Miter circuit according to the circuit description file; random logic simulation is carried out on the Miter circuit to obtain internal potential equivalent nodes, and the internal potential equivalent nodes are stored in an equivalent node queue; selecting potential equivalent node pairs from the equivalent node queue, extracting fan-in cones of the potential equivalent node pairs, and constructing a sub miter circuit according to two groups of fan-in cones; selecting a verification mode according to the density degree of the XOR block in the sub-miter circuit, and verifying the sub-miter circuit; if verification succeeds, the corresponding potential equivalent nodes and the corresponding fan-in cones are combined, otherwise, other potential equivalent node pairs continue to be verified until verification of all potential equivalent nodes is completed; and the SAT solver is used for executing final equivalence verification and returning a verification result, so that the equivalence verification of the data path combination is efficiently realized.

Disclosed are systems, apparatuses, methods, and computer-readable media for machine learning of data path rules for gateway services. A method includes: receiving a command related to a configuration of a firewall of a gateway; obtaining a subset of rules from a collection of rules to apply to a second instance of the firewall that replaces a first instance of the firewall, wherein the collection of rules are expressly associated with the firewall of the gateway; loading the subset of rules and the second instance of the firewall; and when the first instance is available after loading the subset of rules, processing network traffic of the gateway based on the subset of rules

Disclosed herein are methods and systems to generate code for a workflow. A non-limiting example of a method comprises executing, by a processor, a large language model, which receives an input of an intent associated with a workflow and provides a machine-readable description by: identifying, by searching a hierarchical data structure using a vector embedding associated with the intent, an object corresponding to the intent; identifying a set of data paths within the hierarchical data structure to retrieve the identified object; and generating the machine-readable description, the machine-readable description describing the object and at least one data path within the set of data paths; and generating, by the processor, code for the workflow using the machine-readable description.

Embodiments of the invention provide a tree form data processing method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of determining selected information corresponding to a selected instruction; monitoring a dragging action of a mouse cursor, predicting a real-time terminal point position of the model through a dragging terminal point, and dynamically rendering a visual prompt layer at the same time; when monitoring that the dragging action is a stop action, determining the placed data and obtaining a data path, and when the data type of the to-be-dragged data is a combination type, obtaining a data set of a to-be-dragged combination where the to-be-dragged data is located and an index position where first data in the to-be-dragged combination is located, assigning the index position to a tail end index in a data path of the data to be dragged; and traversing data elements adjacent to the placed data in the data path of the placed data to update the key value distribution. According to the method, the defect of performance optimization in the process of executing the dragging action by the preset tree form is effectively solved, and the experience feeling in the process of operating the preset tree form by a user is remarkably improved.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

A method and system to provide secure fine-tune training and inferences for large language models using a Fully Homomorphic Encryption (FHE) process is disclosed. A trained public large language model with a matrix of public weights is stored in plaintext. A private training set of proprietary data is stored as a set of encrypted weights. An encrypted query is received. The encrypted query is processed via an encrypted data path with the set of encrypted weights for trained large language model. The encrypted query is processed via a plaintext data path with the set of public weights in plaintext for the trained large language model. A low rank adaptation (LoRA) approach may be used in fine-tuning the model to reduce computational complexity and memory access. Encrypted results are obtained from the processing via the encrypted data path and the plaintext weight path.

An example method for verifying data integrity in a storage system includes detecting a data access operation that processes data via a data path between a client and a storage device of the storage system, the data path including at least a first and a second processing stage; generating, based on the data access operation, a first instance of a first checksum at a first time based on a first intermediate representation of the data; generating, a second instance of the first checksum at a second time; modifying, based on the second checksum being different from the first checksum, the first intermediate representation to generate a corrected first intermediate representation; generating, based on the corrected first intermediate representation, a third checksum; and directing, based on verifying that the third checksum matches the first checksum, the second processing stage to generate the second intermediate representation.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

Disclosed are systems, apparatuses, methods, and computer-readable media for asynchronous execution of data path service using network fibers. A method includes: based on receiving a first packet within a service for transmitting the first packet to a destination location, processing a first portion of the first packet in a processor based on execution of a first fiber until a first hardware call is reached; sending the first packet to a first circuit for processing the first packet based on the first hardware call; and processing a portion of a second packet associated with a second fiber while the first packet is processing in the first circuit. The systems and apparatuses prevent heavy processing of content from blocking other content.

The invention discloses a body intelligent controller architecture based on an end side intelligent model and an operation method, and belongs to the technical field of industrial body intelligence. According to the architecture, a CPU, a GPU and an FPGA are integrated by adopting a heterogeneous multi-core processor, and high-speed interconnection is realized through a star-type + NoC hybrid topology; a multi-level task scheduling mechanism is constructed based on a real-time operating system, and it is ensured that control tasks are executed preferentially. End-side visual model lightweight (YOLOv5s model parameters are reduced to 3.5 M) and FPGA hardware acceleration (control instruction time delay is 10ns) are innovatively realized on an algorithm framework layer, and a transmission bottleneck is eliminated through a zero-copy data path. The system supports model hot switching less than or equal to 10ms and FPGA bit stream online updating less than or equal to 50ms, and has MD5 check and an automatic rollback mechanism. Compared with a traditional separation type scheme, the processing time delay is reduced by 25 times, the hardware cost is reduced, the size is reduced, and the real-time performance, reliability and deployment flexibility of the industrial robot and other intelligent agents with the body are remarkably improved.