611 results about "Data path" patented technology

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

The invention relates to the field of multi-agent control, and provides an unmanned aerial vehicle patrol flight obstacle avoidance method based on deep reinforcement learning. Aiming at the problems of large work amount, incomplete coverage and poor dynamic obstacle response caused by manual route configuration due to dependence on point cloud data path planning in the prior art, the scheme fuses target detection and radar ranging to obtain obstacle types, positions and distance information; constructing a local obstacle avoidance potential field based on an artificial potential field method, calculating an obstacle avoidance direction through a gravitational repulsion gradient, and introducing a dynamic adjustment mechanism to avoid a local minimum value; designing a local dynamic reward function in combination with the target equipment position, and generating a path adjustment signal by integrating the target approaching progress of the unmanned aerial vehicle and the obstacle avoidance demand; a global reward function is constructed to evaluate the task completion degree, the path efficiency and the obstacle avoidance safety, and a macroscopic strategy optimization basis is formed; a deep neural network architecture is adopted to train an autonomous obstacle avoidance strategy, and an autonomous decision in a dynamic environment is realized through experience playback and an attention mechanism optimization model.

The invention relates to the technical field of information retrieval, in particular to a digitized visitor recording system for a cultural relic museum, which comprises a visitor identity splitting module, a certificate field verification module, a path buffer continuing module, a time field splitting module and a passage information retrieval module. According to the method, a calling priority rule is established according to the difference between field sources and character formats, multi-source data are sequentially split and orderly called, certificate affiliation content is divided according to the corresponding relation between birth time and administrative setting time, so that the regional association relation has a distinguishable boundary, and by setting a field state monitoring and delayed write-in mode, the certificate affiliation content can be obtained. And keeping the continuity of a data path transmission process, matching exhibition hall numbers and corresponding open time periods in combination with a sequence of time fields, so that a visitor staying process has a continuous time positioning basis, matching identity numbers and passing records through an entrance and exit sequence, and communicating passing tracks of visitors in each node in an exhibition area.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

A method for managing data includes: receiving a file analysis request from a user, in which the request includes merging criteria, a first data path to access a first file, a second data path to access a second file, and a third data path to access a third file; obtaining the first file using the first data path, the second file using the second data path, and the third file using the third data path; analyzing the merging criteria; inferring, based on a determination, that the second file is suitable to be merged with the first file and the third file is not suitable to be merged with the first file; merging, based on the merging criteria, the first file and the second file to generate an output file; and initiating, via a graphical user interface (GUI), displaying of the output file to the user.

The invention provides a large model training system based on CPU-GPU double optimizers and SSD unloading, and belongs to the technical field of computers. The system comprises a parameter division manager, a CPU optimizer state exchanger, a CPU optimizer, a GPU optimizer state exchanger and a GPU optimizer, large model parameters are divided into a plurality of subgroups through the parameter division manager, and the subgroups are further divided into a CPU updating part and a GPU updating part; a CPU and GPU double optimizer structure is introduced, a double-SSD architecture is adopted to design an independent data path, GPU-CPU collaborative updating is achieved, optimizer state transition between a GPU or a CPU and an SSD is managed, I / O conflicts are eliminated, the GPU idle time is shortened, the influence of SSD read-write high delay is relieved, load balancing is guaranteed, and the training throughput is improved.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention relates to a discrete distributed load driving system and method, computer equipment and a storage medium. The method comprises the steps that S1, a master control module generates an ordered 0th data packet according to a physical connection sequence of driving modules; s2, the main control module sends the 0th data packet to a first driving module of a one-way data path; s3, the mth driving module receives and analyzes the (m-1) th data packet sent by the upstream to obtain the mth control instruction; s4, the mth driving module drives a load connected with the mth driving module according to the mth control instruction; and S5, the mth driving module cuts off the first sub-data frame from the (m-1) th data packet and repacks the (m-1) th data packet to generate an mth data packet, and sends the mth data packet to a downstream (m + 1) th driving module. The method and the device have the effect of reducing deployment and maintenance cost during large-scale load control.

A request-response based paravirtualized I / O system and method relating to the fields of virtualization and cloud computing includes a request-response application, a front-end drive module and a back-end drive module. The front-end drive module and the back-end drive module interact by means of a transmit queue and a receive queue. The request-response application generates an I / O request, and the front-end drive module writes the I / O request into the transmit queue. The system has two operating modes: a notification mode and a polling mode. The system operates by default in the notification mode. When the request-response application issues a connection establishment or service request, the system switches to the polling mode. This system and method introduce an optimistic polling mechanism, combine the advantages of the notification mode and the polling mode, reduce the number of VM exits and decrease wasting of computing resources, thus improving data path performance.

The invention discloses a multichannel ultrasonic transducer phased array driving method based on direct memory access. The method comprises a waveform data buffer length determination step, a data path construction step, a phase parameter calculation step, a waveform data synthesis step and a DMA driving step. An independent DMA channel is configured for each GPIO port or each group of GPIO ports corresponding to the transducer array by utilizing the DMA characteristic of a universal microcontroller, and buffer data is transmitted to the output data registers of the GPIO ports automatically and periodically by DMA hardware, so that multi-channel driving signals with accurate frequency and controllable phases are generated in parallel under the condition that CPU (Central Processing Unit) intervention is not needed. According to the invention, high-precision time sequence control comparable with an FPGA (Field Programmable Gate Array) scheme is realized with extremely low hardware cost and CPU (Central Processing Unit) resource occupation, the problem of time sequence jitter of an existing MCU (Microprogrammed Control Unit) scheme is solved, and the method has high stability, high efficiency and excellent expandability.

The invention relates to a data loading method and device, a storage medium and equipment, the method is used in an intelligent calculation data processing system comprising a host, a CSD and a SmartNIC, and a PCIe P2P data path is established between the CSD and the SmartNIC; the method comprises the steps that a host generates collaborative descriptors and respectively issues the collaborative descriptors to a CSD and a SmartNIC; the CSD reads source data from a storage medium according to source address information in the collaborative descriptor, executes a processing operation corresponding to the first operator identifier to obtain intermediate data, and directly transmits the intermediate data to a storage area of the SmartNIC through a PCIe P2P data path; and the SmartNIC executes a processing operation corresponding to the second operator identifier on the intermediate data to obtain target data, and transmits the target data to the computing device according to the target address information in the collaborative descriptor.

The invention relates to the technical field of equipment operation monitoring and management, in particular to an Internet of Things equipment intelligent energy consumption management method and system based on artificial intelligence. Comprising the following steps: S1, constructing and training an energy consumption prediction network for predicting an energy consumption condition in a future preset time period, judging a condition that a difference between a predicted value and a real monitoring value exceeds a preset threshold value as an energy consumption abnormal condition, and entering S2 when the energy consumption abnormal condition exists; and S2, constructing a wireless communication networking diagram of the Internet of Things equipment and the base station, taking the base station and the Internet of Things equipment as nodes, and taking a data path between the equipment as an edge to simulate a real communication environment of the Internet of Things equipment. According to the method, the communication networking diagram where the Internet of Things equipment is located is constructed, the common characteristics of the sub-diagrams in the same scene are extracted and applied, the cause of energy consumption abnormity is further mined, the abnormity detection accuracy is improved, and the beneficial effects are provided for subsequent energy consumption management of the Internet of Things equipment.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

The present application relates to a data replay method, a data processing unit, a network interface card, a device, and a storage medium. The method comprises: when a storage stack is restarted, acquiring a replay-pending request queue from a persistent memory, the replay-pending request queue being a queue obtained by mapping a transmission buffer area into the persistent memory, and the transmission buffer area being used for receiving a request from a host side; on the basis of the replay-pending request queue, acquiring a replay-pending request from the persistent memory; and resending the replay-pending request to a target acceleration component directed to a storage device, so as to instruct the storage device to store target data which resides in the persistent memory and corresponds to the replay-pending request. In the method, a request queue, a request, and data corresponding to the request are stored in the persistent memory in advance, and if the storage stack is restarted, the replay-pending request is recovered from the persistent memory, eliminating the need for DMA and encryption / decryption techniques, and shortening an interruption duration of a storage data path, thereby improving data storage efficiency on the host side.

The embodiment of the invention discloses a data processing system and a data processing method based on RISC-V. The data processing system comprises an instruction coding space and a reconfigurable execution unit, the instruction coding space comprises an operation code area, a reserved area and an expansion area; the instruction coding space is used for defining a basic operation to be executed by an instruction in the operation code area, defining an extended operation to be executed by the instruction in the reserved area and defining the length of the instruction in the extended area so as to configure different types of instructions; the reconfigurable execution unit is used for constructing a data path matrix of the instruction based on the configuration information of the instruction; transmitting data required when the instruction is executed based on the data path matrix; and executing an operation corresponding to the instruction based on the data of the instruction.

The invention belongs to the technical field of time sequence calibration, and relates to a core particle parallel interface time sequence calibration method, which comprises the following steps of: introducing a phase interpolator with 180-degree phase deviation in a clock path of a receiving end, and positioning a sampling clock at the center of a data eye diagram; in a data path of a receiving end, a coarse adjustment delay calibration unit is firstly adopted to carry out periodic delay compensation, and the coarse adjustment delay calibration unit adopts a numerical control delay line structure to carry out delay adjustment; and then, a fine adjustment delay calibration unit is adopted to further realize sub-period-level delay adjustment, the fine adjustment delay calibration unit adopts a phase interpolator structure and a dynamic fine adjustment calibration mechanism, and finally, the delayed data signal and the clock signal are aligned at a receiving end. According to the invention, the binary search method is introduced, the positioning speed of the optimal delay configuration is obviously improved, delay drift is fully considered, a dynamic calibration mechanism is added, a sampling window is constructed based on a phase interpolator, and a high-precision and dynamic calibration effect is realized.

A compute tile is described. The compute tile includes compute engines and a general-purpose (GP processor coupled with the compute engines. Each of the compute engines includes a compute-in-memory (CIM) hardware module. The CIM hardware module is configured to store weights corresponding to a matrix and to perform a vector-matrix multiplication (VMM) for the matrix. The GP processor is configured to control the compute engines, to receive output of the VMM for the matrix from the compute engines, and to perform a nonlinear operation on the output. The compute engines are addressable by data movement initiators. Data may be moved to and / or from the compute engines in data paths that bypass the GP processor.

In general, this disclosure describes a network device comprising a physical interface comprising a port and a data path component; a storage device configured to store a power save profile for the network device, wherein the power save profile specifies one or more link down triggers each associated with a power saving action; and processing circuitry having access to the storage device. The processing circuitry may be configured to determine, based on a link fault associated with the port, a link down trigger of the one or more link down triggers specified in the power save profile. The processing circuitry may further be configured to execute the power saving action associated with the link down trigger to reduce power consumed by the data path component.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

The invention relates to an intelligent study and judgment method for abnormal behaviors based on a data flow scene, and aims to solve the technical problem that the data flow scene of data security of an existing digital power grid lacks artificial intelligence technology deep fusion management for physical natural problems under the large background of multi-source heterogeneous energy fusion. The method is characterized in that a unified operation interface of the method is provided with an abnormal state model, and rapid fault diagnosis, data credibility evaluation and automatic data path reconstruction are realized through the abnormal state model so as to store and recover power grid security data; the model covers links of data acquisition, analysis decision, execution recovery and closed-loop feedback, realizes data fusion, anomaly detection and repair by means of digital twinning, edge intelligence and an LSTM neural network, forms a trusted data sequence, supports research and judgment and outputs a recovery instruction; and the decision instruction is issued to the SDN / NFV controller, the data toughness is improved through path switching, and normal operation of the power grid is quickly recovered.

The invention discloses an abnormal traffic detection and response method and system based on a honey hole. The method comprises the following steps: respectively deploying a first type of monitoring nodes to collect camouflage service traffic and a second type of monitoring nodes to collect real-time service traffic at two sides of a target network core data path; preprocessing the two types of traffic to generate a first traffic feature set and a second traffic feature set with a unified structure; performing reliability detection on the feature set through a decision tree model, and screening reliable traffic feature data; predicting a traffic anomaly probability and an attack type by using a specifically trained neural network model, and generating a threat score and a real-time detection result; and when high-confidence abnormal traffic is detected, triggering automatic defense measures, and feeding back abnormal features and response results to the decision tree and the neural network model for iterative optimization. According to the method, through double-path flow collaborative analysis and model dynamic optimization, the false alarm rate is remarkably reduced, and the real-time detection and response capability to hidden attacks is improved.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention discloses a data path structure suitable for cross-domain interaction of high-performance PCIe non-transparent bridge equipment. The data path structure comprises external equipment, an upstream endpoint, a downstream endpoint, a network interface controller connection network, a first bypass module group and a second bypass module group, the external equipment, the upstream endpoint, the network interface controller connection network and the downstream endpoint are sequentially in communication connection, the upstream endpoint and the downstream endpoint are the same in structure, the upstream endpoint is in communication connection with the first bypass module group, and the downstream endpoint is in communication connection with the second bypass module group; and the first bypass module group and the second bypass module group have the same structure. According to the data path structure provided by the invention, through mutual cooperation of the new path and the old path, the overall performance of the non-transparent bridge can be improved, and then the data path structure adapts to high-performance PCIe cross-domain transmission under high load and large flow.