935 results about "Data path" patented technology

The invention discloses a processor and electronic equipment. The processor includes a computing unit including a tensor core configured to perform a matrix multiplication operation using a scaling factor, and a memory, the computing unit further including a scaling factor processing module configured to determine and cache a scaling factor for each tensor associated with the matrix multiplication operation, the computing unit further comprises at least one storage module arranged on a data path between the tensor core and the memory, and the at least one storage module is exclusively occupied by the tensor core when the tensor core executes tensor related operation. And the scaling factor processing module is arranged on the at least one storage module. At present, scaling factors and floating-point number quantization are completed by a vector calculation core, so that performance is reduced, and delay becomes high, and a scaling factor processing module arranged on a storage module in a calculation unit can improve the overall execution efficiency of low-precision matrix multiplication using the scaling factors.

The invention relates to the field of electronic communication, and provides a multi-protocol dynamic switching method and system based on an FPGA. The method comprises the following steps: carrying out regional division on an FPGA chip through a layout planning tool to obtain a static logic region and a plurality of reconfigurable logic partitions; performing hanging processing on the current protocol module based on the protocol switching trigger signal, and writing running state data of the current protocol module into a state cache unit to obtain protocol context snapshot data; according to the target protocol type, bit stream loading is carried out on the corresponding reconfigurable logic partition through configuration of an access port, and a reconfiguration protocol module is obtained; and reading protocol context snapshot data, and performing state recovery on the reconstruction protocol module to obtain a target protocol data path. According to the invention, rapid protocol switching is realized, the utilization rate of hardware resources is improved, and the system deployment cost is reduced.

The invention discloses a computing platform management system based on artificial intelligence, particularly relates to the technical field of distributed storage resource dynamic allocation, and is used for solving the problem of resource allocation oscillation caused by hardware performance difference and dynamic attenuation in the prior art. Acquiring the hardware performance, the load state and the data path of the storage node through a real-time acquisition module; the entropy judgment module calculates a path topology entropy and triggers a reconstruction instruction; the resonance analysis module analyzes the group association strength of hardware performance degradation and marks a resonance node group; the weight generation module fuses the parameters to generate a dynamic allocation weight; the error compensation module optimizes a weight coefficient in combination with historical error data; the migration execution module executes migration according to the weight and limits the load of the resonance node; through cooperative regulation and control of topological entropy monitoring and hardware resonance analysis, local oscillation diffusion is inhibited, unnecessary migration operation is reduced, system stability is improved, and the service life of hardware is prolonged.

The invention relates to the technical field of digital marketing, and discloses an omni-channel marketing funnel intelligent attribution model and an automatic budget distribution system, and the model comprises a data collection module which is used for collecting data through a contact recording device and a user identification device which are disposed at a marketing terminal, and a behavior tracking device and a channel classification device which are disposed at a user side. Acquiring information such as multi-channel marketing contact interaction data, user behavior data and channel types; the path analysis module realizes data path analysis through time sequence synchronization of a time alignment unit, feature matching of a path association unit and dynamic adjustment of a computing power scheduling unit; the attribution calculation module generates the conversion attribution weight of each channel based on the matching data; and the budget mapping module establishes a dynamic mapping relationship between the weight and the budget and updates the dynamic mapping relationship. The system outputs the attribution result through the model application module, and the budget execution module distributes the budget according to the dynamic mapping, so that the channel contribution can be accurately evaluated, the scientific distribution of the marketing budget is realized, and the marketing efficiency and the rate of return on investment are improved.

The invention belongs to the field of eye movement data tracking, particularly relates to a pilot eye movement tracking method, system and equipment based on multi-camera fusion and a storage medium, and aims to solve the problems that in the prior art, the visual angle of a traditional eye tracker is limited, and sight estimation errors are caused by head movement. The method comprises the following steps of: constructing a multi-view visual perception network by deploying multiple cameras and eye trackers in a cockpit; multi-source data space-time alignment is achieved through space coordinate system mapping and time synchronization, and head motion errors are compensated by combining dynamic cutting of eye interested areas and three-dimensional head posture estimation. The geometric path generates a physical driving vector based on iris fitting and an eyeball model, and the data path regresses the vector through a deep learning model; and converting to a world coordinate system through a head posture after fusion. High-precision data of the eye tracker is preferentially adopted in the central area, and field-of-view data of the system is expanded in the edge area. According to the invention, the tracking precision under field angle coverage and motion interference is obviously improved.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

Disclosed herein are methods and systems to generate code for a workflow. A non-limiting example of a method comprises executing, by a processor, a large language model, which receives an input of an intent associated with a workflow and provides a machine-readable description by: identifying, by searching a hierarchical data structure using a vector embedding associated with the intent, an object corresponding to the intent; identifying a set of data paths within the hierarchical data structure to retrieve the identified object; and generating the machine-readable description, the machine-readable description describing the object and at least one data path within the set of data paths; and generating, by the processor, code for the workflow using the machine-readable description.

An example method for verifying data integrity in a storage system includes detecting a data access operation that processes data via a data path between a client and a storage device of the storage system, the data path including at least a first and a second processing stage; generating, based on the data access operation, a first instance of a first checksum at a first time based on a first intermediate representation of the data; generating, a second instance of the first checksum at a second time; modifying, based on the second checksum being different from the first checksum, the first intermediate representation to generate a corrected first intermediate representation; generating, based on the corrected first intermediate representation, a third checksum; and directing, based on verifying that the third checksum matches the first checksum, the second processing stage to generate the second intermediate representation.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

The invention discloses a body intelligent controller architecture based on an end side intelligent model and an operation method, and belongs to the technical field of industrial body intelligence. According to the architecture, a CPU, a GPU and an FPGA are integrated by adopting a heterogeneous multi-core processor, and high-speed interconnection is realized through a star-type + NoC hybrid topology; a multi-level task scheduling mechanism is constructed based on a real-time operating system, and it is ensured that control tasks are executed preferentially. End-side visual model lightweight (YOLOv5s model parameters are reduced to 3.5 M) and FPGA hardware acceleration (control instruction time delay is 10ns) are innovatively realized on an algorithm framework layer, and a transmission bottleneck is eliminated through a zero-copy data path. The system supports model hot switching less than or equal to 10ms and FPGA bit stream online updating less than or equal to 50ms, and has MD5 check and an automatic rollback mechanism. Compared with a traditional separation type scheme, the processing time delay is reduced by 25 times, the hardware cost is reduced, the size is reduced, and the real-time performance, reliability and deployment flexibility of the industrial robot and other intelligent agents with the body are remarkably improved.

An embodiment selects, using performance data of a plurality of paths, a first path, each path comprising a data communication path from a first network endpoint through a subset of a plurality of network elements in a data communication network to a second network endpoint. An embodiment adjusts a packet header of a data packet, wherein a parameter setting in the adjusted data packet header causes a first network element in the data communication network to forward the adjusted data packet to a next network element in the data communication network along the first path. An embodiment sends the adjusted data packet, wherein the adjusted data packet causes a first subset of the plurality of network elements in the data communication network to forward the adjusted data packet to the second network endpoint along the first path.

The invention relates to the field of multi-agent control, and provides an unmanned aerial vehicle patrol flight obstacle avoidance method based on deep reinforcement learning. Aiming at the problems of large work amount, incomplete coverage and poor dynamic obstacle response caused by manual route configuration due to dependence on point cloud data path planning in the prior art, the scheme fuses target detection and radar ranging to obtain obstacle types, positions and distance information; constructing a local obstacle avoidance potential field based on an artificial potential field method, calculating an obstacle avoidance direction through a gravitational repulsion gradient, and introducing a dynamic adjustment mechanism to avoid a local minimum value; designing a local dynamic reward function in combination with the target equipment position, and generating a path adjustment signal by integrating the target approaching progress of the unmanned aerial vehicle and the obstacle avoidance demand; a global reward function is constructed to evaluate the task completion degree, the path efficiency and the obstacle avoidance safety, and a macroscopic strategy optimization basis is formed; a deep neural network architecture is adopted to train an autonomous obstacle avoidance strategy, and an autonomous decision in a dynamic environment is realized through experience playback and an attention mechanism optimization model.

The subject application relates to separate command address (SCA) protocol-based memory controllers. For instance, a method may include receiving, by a separate command address (SCA)-based memory controller, a plurality of commands, scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues, converting the scheduled plurality of commands into SCA-based commands, selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution, and executing in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.

The embodiment of the invention provides a core grain verification method and related equipment. The core grain verification method comprises the following steps: acquiring data path modules of a plurality of core grains in a to-be-tested design and module verification environments corresponding to the data path modules; the data path modules of the plurality of core particles are in heterogeneous design; the module verification environment is used for indicating a verification environment corresponding to the data path module; compiling the obtained data path module of each core particle into different file libraries and connecting the file libraries to a top layer module of the to-be-tested design; combining the obtained module verification environments corresponding to the data path modules of the core particles into a top layer verification environment; and based on the top layer verification excitation of the top layer verification environment, executing verification of data path modules of a plurality of core particles in a to-be-tested design. According to the scheme, the test accuracy of the test scene of the cross-heterogeneous data path module can be ensured.

The embodiment of the invention provides a cross-clock domain data transmission method and device. The method comprises the following steps: sampling a first clock of a first clock domain by using a second clock of a second clock domain and outputting a sampling signal; moving a second clock edge of the second clock according to the sampling signal to enable the second clock edge to move from one side of a first clock edge of the first clock to the other side of the first clock edge of the first clock; repeatedly executing the step of sampling the first clock by the second clock and outputting the sampling signal and the step of moving the second clock edge of the second clock according to the sampling signal, so that the second clock edge reciprocates on the two sides of the first clock edge; judging whether a clock locking signal is generated or not; after the clock lock signal is generated, data transmission in a data path between the first clock domain and the second clock domain is enabled. The method and the device do not depend on a traditional asynchronous handshake mode or buffer mechanisms such as FIFO, delay needed by synchronous logic is avoided, and the method and the device are suitable for the requirement of high-speed communication.

The invention provides a self-adaptive PD charging control method and system based on a double Type-C circuit and a storage medium, and the method comprises the steps: monitoring an interface connection state in real time, collecting power-on current information when peripheral access is detected, and intelligently recognizing a device type in combination with a preset current threshold range and a PD protocol handshake process. The function change-over switch and the charging management module are dynamically configured; if the device is a data device, a data path is connected and power output is limited; if the device is a charging device, charging parameters are negotiated and high-power transmission is started; when the double charging devices are connected, intelligent power distribution and priority management are executed, electrical parameters such as voltage, current and temperature are continuously monitored, and self-adaptive adjustment is triggered when the voltage, the current, the temperature and the like exceed the limit. According to the invention, intelligent function switching and safe power management of double interfaces are realized, the risk of misplug damage is effectively avoided, and the equipment compatibility, the system energy efficiency and the user experience are improved.

The invention relates to the technical field of information retrieval, in particular to a digitized visitor recording system for a cultural relic museum, which comprises a visitor identity splitting module, a certificate field verification module, a path buffer continuing module, a time field splitting module and a passage information retrieval module. According to the method, a calling priority rule is established according to the difference between field sources and character formats, multi-source data are sequentially split and orderly called, certificate affiliation content is divided according to the corresponding relation between birth time and administrative setting time, so that the regional association relation has a distinguishable boundary, and by setting a field state monitoring and delayed write-in mode, the certificate affiliation content can be obtained. And keeping the continuity of a data path transmission process, matching exhibition hall numbers and corresponding open time periods in combination with a sequence of time fields, so that a visitor staying process has a continuous time positioning basis, matching identity numbers and passing records through an entrance and exit sequence, and communicating passing tracks of visitors in each node in an exhibition area.

The invention provides an optimized kernel network and an implementation method thereof, and relates to the technical field of kernel networks, the kernel network comprises a fast data channel component XDP arranged on a data link layer; when the network card equipment receives a message data packet, the XDP analyzes and filters the received data packet, or encapsulates or de-encapsulates the received data packet, and modifies a field to forward the data packet; and the XDP matches and filters the received data packet with the rules in the BPF Maps, and discards the data packet when the data packet is illegal. The method comprises the steps that hardware initialization comprises the step of adding a zero copy processing flow when an NAPI polling point processing function is added; the application program configures an XDP socket; the xsk unit executes a BPF instruction, calls a network card driving unit to configure an XSK cache pool, and establishes a DMA mapping relationship between the device and the UMEM shared cache; and the network card drives zero-copy receiving and receiving of the data packet. According to the invention, the kernel network communication efficiency is improved.

The invention relates to the technical field of data backup, and discloses an iOS device data backup and recovery method and system, and the method comprises the steps: carrying out the SSL certificate verification and EscrowBag key authentication of an iOS device, and obtaining a data path list; according to the data path list, parallel scanning of APFS file system B-Tree traversal, NAND flash memory page reading and SQLite WAL log analysis is carried out on the iOS device storage partition, and an original data set is obtained; performing integrity evaluation based on the original data set to obtain an effective data set and constructing a virtual file index; the data selection list of the user is confirmed based on the virtual file index, safety recovery is executed, and a data recovery result is returned. The SQLite page Cell reconstruction and fragment file signature matching technology is combined, intelligent repair and quality prediction can be conducted on damaged data, the user experience and operation efficiency are improved, and the user experience is improved. And the security and the reliability in the data recovery process are ensured.

The invention discloses a data path switching method of a Retimer controller and a Retimer chip, and belongs to the field of communication. In order to reduce the risk of timeout of RC and EP in a balance stage, the method for switching the data path of the Retimer controller comprises the following steps: when the Retimer controller simultaneously meets the condition that any channel of an uplink pseudo port and a downlink pseudo port respectively detects eight continuous TS2 sequences with speed fields of 1, the public maximum rate is PCIe Gen6 and is greater than the current rate, and the Retimer controller is in an FLIT mode and a stateful state, setting the start field to 1. And after the negotiation is completed, the RC controller, the EP controller and the Regimer controller enter a recovery. Speed state to switch the speed, and the switching from PCIe Gen5 to Gen6 is completed. And after switching, the Retimer and the EP are switched to a recovery. Phase0 state, the RC is switched to a recovery. Phase1 state, and when the Retimer controller is in the recovery. Phase0 state, a code stream generation module generates a TS0 sequence and sends the TS0 sequence to the RC and the EP. The method is applied to the PCIe field, and the robustness of RC and EP in the balancing process is improved.

The invention provides an on-chip network router, and a transmission method and device for routing data in an on-chip network, and the router comprises a row module and a column module which are mutually independent physically, so as to achieve the dimension decoupling of a data flow; wherein each of the row module and the column module comprises a crossbar switch and an arbitration unit coupled with the crossbar switch; the arbitration unit is configured to execute an arbitration decision on only one request in a conflict-free request pair when the two input ports of the crossbar switch request to be connected to the two different output ports respectively to form the conflict-free request pair, and to execute an arbitration decision on the conflict-free request pair based on the result of the arbitration decision. A data path is automatically established for another request in the conflict-free request pair to achieve mirroring effect arbitration. The router adopts the row and column decoupling type architecture and is matched with a mirror effect arbitration mechanism, so that resource competition is effectively reduced, arbitration logic is simplified, and the throughput and efficiency of the network-on-chip router are improved.

The invention discloses a memory performance detection method, device and equipment and a memory medium, and relates to the technical field of memory performance detection. Memory with the same capacity of a data path port of a memory box is mapped to an endpoint port, the mapped memory is converted into an extended memory which can be identified by a host node, and then the memory performance of the extended memory is subjected to a consistency test, so that a memory mapping relationship can be quickly and effectively established; according to the embodiment of the invention, the host nodes can schedule the memory capacity required by the host nodes in the memory box, and the inconsistency caused by different mapped memory spaces is eliminated by configuring extended memories with the same capacity for the host nodes, so that the memory performance of the plurality of host nodes tends to be consistent on the premise, and the effectiveness of the consistency test is improved.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

A method for managing data includes: receiving a file analysis request from a user, in which the request includes merging criteria, a first data path to access a first file, a second data path to access a second file, and a third data path to access a third file; obtaining the first file using the first data path, the second file using the second data path, and the third file using the third data path; analyzing the merging criteria; inferring, based on a determination, that the second file is suitable to be merged with the first file and the third file is not suitable to be merged with the first file; merging, based on the merging criteria, the first file and the second file to generate an output file; and initiating, via a graphical user interface (GUI), displaying of the output file to the user.

The invention provides a large model training system based on CPU-GPU double optimizers and SSD unloading, and belongs to the technical field of computers. The system comprises a parameter division manager, a CPU optimizer state exchanger, a CPU optimizer, a GPU optimizer state exchanger and a GPU optimizer, large model parameters are divided into a plurality of subgroups through the parameter division manager, and the subgroups are further divided into a CPU updating part and a GPU updating part; a CPU and GPU double optimizer structure is introduced, a double-SSD architecture is adopted to design an independent data path, GPU-CPU collaborative updating is achieved, optimizer state transition between a GPU or a CPU and an SSD is managed, I / O conflicts are eliminated, the GPU idle time is shortened, the influence of SSD read-write high delay is relieved, load balancing is guaranteed, and the training throughput is improved.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention discloses a hard disk backboard switching system and method, a hard disk backboard, electronic equipment and a medium, and relates to the technical field of servers. A detection circuit is arranged to automatically detect the level state of a protocol detection pin connected to a hard disk so as to determine the type of the hard disk and generate a corresponding control signal; the switching chipset responds to the signal and automatically switches the data path between the interface module and the mainboard bus, so that compatible management and control of a single backboard on hard disks of different protocol types are realized, two independent board cards are not needed, and therefore, the cost is reduced. The technical problems of high hardware cost, inconvenient operation and high system complexity when two independent board cards are adopted for management and control in the prior art can be solved, and the technical effects of reducing the hardware cost, improving the use convenience, reducing the system complexity and improving the system stability and the integration degree are achieved.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention discloses a PCIe interface chip layout and wiring method, and belongs to the field of chip design automation. In order to reduce adverse effects of Setup violation and Hold violation on chip performance, when physical layout arrangement of a PCIe interface chip is placed and a clock tree is synthesized, an IP core receiving side interface signal and register information associated with an IP core internal receiving side are captured, and a register associated with the IP core internal receiving side is placed according to the IP core direction, so that the chip performance is improved. And according to the delay length of the data path of the receiving side interface in the IP core, the delay length of the clock path of the receiving side interface in the IP core, and the delay length of the data path between the registers associated with the receiving side in the IP core, constraining the clock length of the registers associated with the receiving side. The method is applied to the field of chip design, and the chip has better performance and power consumption and smaller area.

The invention relates to a discrete distributed load driving system and method, computer equipment and a storage medium. The method comprises the steps that S1, a master control module generates an ordered 0th data packet according to a physical connection sequence of driving modules; s2, the main control module sends the 0th data packet to a first driving module of a one-way data path; s3, the mth driving module receives and analyzes the (m-1) th data packet sent by the upstream to obtain the mth control instruction; s4, the mth driving module drives a load connected with the mth driving module according to the mth control instruction; and S5, the mth driving module cuts off the first sub-data frame from the (m-1) th data packet and repacks the (m-1) th data packet to generate an mth data packet, and sends the mth data packet to a downstream (m + 1) th driving module. The method and the device have the effect of reducing deployment and maintenance cost during large-scale load control.