628 results about "High memory" patented technology

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

A new system architecture for servers used in supercomputers uses an on-chip switch fabric with backpressure to improve performance. A server-on-a-chip includes one or more of the on-chip switch fabrics coupling one or more processing cores enabled to respond to the backpressure. Optionally, one or more ports of the on-chip switch fabrics are used to provide (external) ports of the server-on-a-chip to enable seamless communication with other server-on-a-chip instances. Various instances of the server-on-a-chip use the seamless communication to communicate with each other over a single printed circuit board and / or with each other across a plurality of printed circuit boards. Optional smart memory and / or multi-homed memory techniques improve memory efficiency by posting all writes, hiding DRAM maintenance operations (e.g., refresh, scrubbing, error correction and / or error logging), and / or reducing attack vectors, such as via secure booting of encrypted boot images.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

The invention discloses a cache management method and device for memory access, equipment and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: obtaining a data read-write message of a central processing unit; detecting a data popularity type of an access address of the data read-write message; searching cache data corresponding to the access address from a target cache region; if the cache data is not found in the target cache region, sending a corresponding read-write request to a memory so as to find memory data corresponding to the access address from the memory; by setting the preset cache regions corresponding to the cold data and the hot data respectively, the cache can be partitioned according to the heat of the data, so that cache resources are reasonably allocated, the cost is reduced, the memory access efficiency and speed are improved, finer consistency control can be realized, and the cache hit rate and the system performance are improved; therefore, the required data is searched in the corresponding preset cache region according to the heat of the data, and the memory access speed is increased.

The invention discloses a memory allocation method and related equipment, which are applied to electronic equipment, and the method comprises the following steps: receiving a first memory request of an application program, the first memory request comprising a target memory space value; determining a virtual address matched with the target memory space value from a virtual memory space, and determining a target virtual address to be mapped from the virtual address; a to-be-mapped target physical address is determined from a physical memory space, whether the target virtual address and the size and byte boundary of the target physical address meet a first condition is judged, and the first condition comprises the alignment type of the byte boundary; if the first condition is met, determining an attribute parameter matched with the first condition; and creating a page table matched with the attribute parameter, and establishing a mapping relationship between the target virtual address and the target physical address. By adopting the embodiment of the invention, the memory access efficiency can be improved.

The embodiment of the invention provides a memory pool management method and device, a storage medium and an electronic device.The method comprises the steps that operation requirements of a distributed storage system are obtained, and large-page memory division is conducted on storage resources associated with the distributed storage system according to the operation requirements to obtain a plurality of target memory pools; wherein each target memory pool in the plurality of target memory pools corresponds to one type of memory object type, and the one type of memory object type at least comprises one memory object; recording historical data of using the plurality of target memory pools in a first preset period; constructing an intelligent prediction model through the historical data and a preset initial prediction model, and predicting an adjustment demand in a second preset period by using the intelligent prediction model and the current state data of the distributed storage system; and dynamically managing the plurality of target memory pools based on the adjustment demand. The problems that memory allocation is high in overhead and low in efficiency, and dynamic management and optimization of memory resources cannot be achieved are solved.

The invention discloses a server memory management system and a cluster system, and relates to the technical field of server memory management, the system identifies memory fault information of a server based on a fault reminding signal under the condition that a fault signal is received, and the current load state is determined based on operation data of the server. And matching the corresponding target repair strategy to perform fault repair on the server memory based on the target repair strategy. Therefore, the system can dynamically match different fault recovery strategies according to different fault scenes, so that the technical problem of poor flexibility of a memory fault recovery method in related technologies is solved, and the technical effects of improving the flexibility of memory fault recovery and the service operation stability of a server are achieved.

The invention relates to a remote memory read-write method and device based on an RDMA transmission protocol. The method comprises the following steps: creating a virtual character device based on memory information transmitted by a remote node, and mapping the memory information to a local virtual device; when missing page interruption is triggered, distributing a physical memory, initiating an RDMA read request, reading target memory data of a remote node to the physical memory, performing write protection on the target memory data, marking a dirty mark on the target memory data when a process of a user mode modifies the target memory data, and performing write protection on the target memory data; periodically detecting a local physical memory according to a preset time interval, when target memory data carrying a dirty mark is detected, initiating an RDMA write request, writing back the target memory data carrying the dirty mark to a far-end node, and when detecting that the physical memory is overtime, recovering the physical memory; by adopting the method, the data synchronization performance between the local node and the remote node can be accelerated, and the memory utilization efficiency can be improved.

The invention discloses a federal large language model fine tuning method and system based on zero-order optimization, and relates to the technical field of artificial intelligence. A large language model is deployed in a federal learning framework, and the usage amount of model parameters during training and the transmission amount in the communication process are reduced by using low-rank decomposition, so that the training efficiency is improved. And then performing zero-order fine tuning on the local model to complete updating of the model. The technical problem of high memory requirement in the prior art is solved.

The embodiment of the invention provides a memory management method and device, equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-applied first memory capacity, and determining a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence; starting from a first offset in the first offset sequence, according to the first offset, offsetting a bit of a preset register, and based on the register value before offset and the register value after offset, obtaining a register update value; each bit is used for representing that the corresponding memory area is in an idle state or an occupied state; on the basis of the register update value, continuing the next offset until the first offset sequence is traversed, and determining a final first register value; and encoding the first register value to obtain a first memory address corresponding to the first register value. The memory management efficiency can be improved.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention discloses a large language model reasoning acceleration method and system based on dynamic sparsity, and the method comprises the steps: adding a parallel bypass prediction path on an original main calculation path of a network module supporting dynamic simplification of a structure of an original target large language model for the original target large language model; embedding a predictor for selective activation in the bypass prediction path, the predictor being used for generating a network sub-module to be activated according to an input vector of the network module so as to obtain a target large language model supporting two working modes of a dense mode and a sparse mode; when the sparse mode needs to be executed, a predictor embedded in the bypass prediction path is activated to obtain a fast reasoning result; and when the dense mode needs to be executed, closing the predictor embedded in the bypass prediction path to obtain a comprehensive reasoning result. The method aims at solving the problems that in the large language model reasoning process, video memory occupation is too high, and time consumption is too large, and optimal balance of calculation efficiency and resource consumption is achieved.

The invention discloses a data verification method and device for a redundant disk array, equipment and a medium, and relates to the technical field of data verification, when a data verification value of target data is generated, the target data is firstly divided into a plurality of data blocks, and correspondingly reference data is also divided into one-to-one corresponding reference blocks; then, the unit verification value of each data block is determined by taking the data block as a unit, and the data verification value of the target data is obtained through block-by-block calculation, so that the data verification of the target data is realized according to the data verification value, the memory occupation in the data verification value generation process is reduced, the storage requirement of temporary data is reduced, and the data verification efficiency is improved. The high memory overhead of processing the whole target data at a time is avoided, and the calculation efficiency of the data verification value is improved. The size of the data block can be flexibly adjusted according to requirements, the application range is wide, the flexibility is high, the check and problem positioning of the stored data are facilitated, and the troubleshooting of abnormal conditions such as data damage of the stored data is facilitated.

The embodiment of the invention provides a memory recovery method and device, equipment and a medium, the method is executed by computer equipment deployed with a container, and the container comprises a quality service agent component and a memory recovery agent component. The method comprises the following steps: determining a to-be-recycled memory node in a memory control group managed by a container through a quality service agent component, and transmitting the to-be-recycled memory node to a memory recycling agent component; obtaining a memory usage amount and a memory recovery index corresponding to the to-be-recovered memory node through the memory recovery agent component, and determining a memory recovery amount corresponding to the to-be-recovered memory node according to the memory usage amount and the memory recovery index; and calling a memory recovery interface through the memory recovery agent component, and recovering the physical memory in the memory node to be recovered based on the memory recovery amount. By implementing the embodiment of the invention, the memory resource utilization rate can be improved.

The invention provides a memory allocation method and device.The method comprises the steps that the maximum lexical element handling capacity sent by a host end is received, the maximum lexical element handling capacity is determined based on the length of an input sequence and the number of allocated experts, and the number of the allocated experts is the number of expert models allocated to all lexical elements; applying for a memory matched with the maximum lexical element handling capacity at a device end; dividing a target memory corresponding to each expert model from a memory based on the lexical element quantity processed by each expert model; and allocating each target memory to the corresponding expert model, wherein each target memory is used for storing the lexical elements processed by the corresponding expert model. According to the method, the maximum lexical element processing amount does not need to be synchronized at the host end, so that delay introduced by synchronous operation from the equipment end to the host end can be avoided, communication overhead in the memory allocation process can be reduced, the memory allocation efficiency and the overall processing speed can be improved, and finally the model reasoning performance of the equipment end is improved.

The invention is suitable for the technical field of memory resource calling, and provides a memory resource calling optimization method and system. The method comprises the following steps: comprehensively monitoring memory resources to obtain memory monitoring data, scheduling and analyzing the memory monitoring data, and generating a distribution call notification or a recovery call notification; obtaining program request information and memory state information according to the allocation call notification, and allocating the target memory block to perform memory resource configuration; determining a plurality of adjacent idle memories according to the recovery calling notification, and compressing and recovering the plurality of adjacent idle memories; and when a preset fragment arrangement condition is met, identifying a plurality of dispersed memory fragments, and integrating the plurality of memory fragments into an available memory block. According to the method, the problems of more memory fragments, low utilization rate and poor flexibility in the prior art can be solved, more efficient memory allocation and recovery can be realized, the memory fragments are reduced, the utilization rate of the memory is improved, and meanwhile, the adaptability of a system to different memory requirements is enhanced.

The invention discloses a CXL-containing memory page placement system, and relates to the technical field of memories. Comprising a memory cold and hot page detection module and a memory migration module which are connected in sequence; the memory cold and hot page detection module is used for collecting memory access events, generating a page heat map based on the collected memory access events, and analyzing page types and page locality; the memory migration module is used for identifying and distributing cold and hot memory interfaces. According to the method, the use performance of the memory can be optimized and improved, and the method has good market prospects and application value.

The embodiment of the invention provides a memory semantic processing method and device, equipment, a medium and a product. According to the method, a large memory semantic task can be split into a plurality of small sub-memory semantic tasks according to the memory semantic task and the core resource of the processor, so that the scale of the memory semantic task can be within the processing capacity of the processor, and the semantic bit width limitation of the processor can be broken through. According to the method, the sub-memory semantic tasks are allocated to the cores of the processor for parallel execution, so that the processing efficiency of the memory semantic tasks can be improved, and the problem that part of the cores are idle and the part of the cores are overloaded is avoided. In addition, by aggregating the messages corresponding to the sub-memory semantic tasks, a plurality of transmission tasks of a plurality of sub-memory semantic tasks can be completed through one-time transmission, consumption of transmission resources is reduced, and the efficiency of data operation is improved.

The invention provides a game resource optimization method and device based on a predictive algorithm and a storage medium. The method comprises the following steps: compiling a source code of a game voice tool into a bytecode file and generating an executable game voice tool main body; dividing the loading process of the non-core resources into a plurality of stages, and pre-loading the non-core resources through at least one background thread; generating a target resource list for a subsequent game scene by using a predictive algorithm; executing a loading operation on the target resource which is not loaded by utilizing a background thread, and executing a releasing operation on the loaded resource which is judged to be lower than a preset threshold value in the subsequent game scene by the predictive algorithm, wherein the use probability of the loaded resource is lower than the preset threshold value; a high execution priority is set for a voice communication module, and the loading priority of non-core resources and the task allocation order of background threads are dynamically adjusted according to the real-time condition of voice communication. According to the method and the device, memory resource utilization can be improved, CPU (Central Processing Unit) occupation is reduced, and game jamming caused by resource competition is reduced.

The invention discloses a memory fault prediction method and device, a chip, equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps that error position distribution of an error correction unit associated with a memory is obtained, the memory comprises at least one memory particle, the error correction unit comprises a plurality of data bits obtained from a plurality of storage units of the memory through continuous multiple burst reading, and each data bit corresponds to one storage unit in the memory; the error position distribution is used for indicating the position of an error data bit in a plurality of data bits, and the error position distribution causes the occurrence of CE in the memory; a memory fault model is obtained, the memory fault model comprises at least one reference position distribution, and the reference position distribution is associated with the UCE of the memory; according to the similarity between the error position distribution and the at least one reference position distribution, a prediction result is output, and the prediction result is used for indicating the probability that the UCE occurs in the memory. The method is beneficial to improving the timeliness of memory fault prediction.

This application discloses a memory fault processing method and apparatus, and a storage medium, to improve memory fault repair efficiency. An out-of-band controller obtains fault information of a memory. The out-of-band controller determines a fault severity of a target cache block based on the fault information and a target replacement cache block based on the fault severity of the target cache block. The target replacement cache block is used to replace the target cache block, the target replacement cache block is a cache block currently used to replace a historically faulty cache block. The out-of-band controller sends a repair request to a central processing unit (CPU), where the repair request is used to request the CPU to perform fault repair on the target cache block.

The invention discloses a memory bank installation device, system and method which are applied to the field of memory installation, a press-fitting assembly comprises a pressing block and a power component, and the pressing block is installed on the power component; the pressure sensor is used for acquiring a first pressure value and a second pressure value of the pressing block on the memory bank; and the controller is used for controlling the power part to stop acting when the first pressure value is greater than the upper limit of the first threshold value, the first pressure value is smaller than or equal to the upper limit of the first threshold value, and the second pressure value is greater than a preset pressure value in the second threshold value. According to the memory bank installation device provided by the invention, the pressure values of the memory bank at the first preset position and the second preset position are respectively detected to serve as a judgment basis for judging whether the memory bank is inserted obliquely or not and whether the memory bank is installed in place or not, so that the probability of damage to the memory bank or a memory slot can be effectively reduced, and the memory bank installation device is convenient to operate and high in practicability. The cost is saved, and the installation efficiency and the automation degree of the memory bank can be effectively improved.

The invention relates to a memory allocation method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: receiving a memory allocation request of to-be-stored data to a memory database, wherein the memory allocation request comprises a data storage amount of the to-be-stored data; determining a target memory block from a virtual process space of the memory database according to the data storage amount; the virtual process space is a storage space mapped to a disk file based on a memory mapping mechanism, and data stored in the virtual process space is synchronously stored in the disk file; the size of the target memory block is greater than or equal to the data storage amount; and distributing the target memory block for the to-be-stored data, wherein the target memory block is used for storing the to-be-stored data. By adopting the method, the storage capacity and the storage efficiency of the memory database can be improved.

Described is a device having three-dimensional (3D) integration of a DRAM die and processor ASIC. Such an integrated device achieves much higher memory bandwidth and low memory access power consumption than prior art devices while still retaining the high capacity and low cost of DRAMs. The devices and techniques described herein can result in much higher computational throughput, higher power efficiency, and lower cost per throughput than conventional processors while still providing the high memory capacity necessary to be able to work on large problems.

The invention relates to a memory management method and device, equipment and a medium, and the method comprises the steps: obtaining a memory application request sent by memory requester equipment for a target resource; analyzing the memory application request to obtain a to-be-applied first memory size; a target memory box of which the size range comprises a first memory size is determined from a plurality of memory boxes of different size ranges, the memory boxes are obtained by clustering memory blocks of each memory size specification, and each memory box comprises a preset number of memory blocks of which the memory sizes are within the size range corresponding to the memory box; a target memory block matched with the first memory size is determined in all memory blocks of the target memory box, and the memory size of the target memory block is larger than or equal to the first memory size; and in response to the memory application request, allocating the target memory block to a target resource of the memory requester device. According to the technical scheme, the fragmentation problem can be reduced, and the memory processing efficiency is improved.

The invention discloses a memory detection method and electronic equipment. The method can comprise the steps that the electronic equipment detects a first memory occupied by a first process, wherein the first memory is an actually-used physical memory RSS; when the first memory is larger than the first threshold value, the electronic device detects a second memory occupied by the first process, and the second memory is a proportionally allocated actually used physical memory PSS. And when the second memory is greater than the first threshold value, the electronic equipment performs memory detection on the first process according to preset time. Thus, the electronic equipment detects the RSS occupied by the first process firstly, and if the RSS occupied by the first process exceeds the rated memory (namely the first threshold), the electronic equipment detects the PSS occupied by the first process. As the range of the RSS is larger than that of the PSS, the electronic equipment filters out most of the processes by detecting the RSS occupied by the first process, and then accurately locates the process with excessive memory by detecting the PSS occupied by the first process, so that the accuracy of memory detection is improved.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention provides a memory management method and device, a storage medium and an electronic device.The method comprises the steps that a heap memory of a process is applied from a system memory, and the process comprises a plurality of threads; aiming at a first thread of the process, the heap memory is adopted to construct a first local free table of the first thread, and the first local free table is used for locally storing an object pool of the first thread by adopting a thread local storage structure; and in response to a memory allocation request, allocating a first object for the first thread from the first local free table. Through the embodiment of the invention, the technical problem that memory fragments occur in dynamic memory allocation in related technologies is solved, and the memory management efficiency and performance are improved.

Embodiments of the present disclosure provide a memory management method, a device, a storage medium and a program product. The embodiments of the present disclosure provide a memory management mechanism relatively independent of an operating system, especially applicable to data scenarios where memory swapping is not desirable, or scenarios where independent memory isolation domains are required. Memory pages in a first memory pool are managed by means of a first memory pool management structure, and it is allowed to apply for a memory space from the memory pages in the first memory pool, the applied memory space is segmented into memory blocks of smaller granularity to create a second memory pool, and the memory blocks in the second memory pool are managed by means of a second memory pool management structure, so that the memory space can be allocated at the granularity of the memory blocks. Centralized memory management can be achieved, frequent swap-out of the memory pages in the first memory pool is avoided, system performance fluctuations are reduced, memory fragmentation can be reduced, the memory utilization rate is increased, and the system performance is improved.