486 results about "High memory" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention discloses a memory access method, a program product, equipment and a medium, and relates to the technical field of computers, firmware is utilized to determine to-be-reserved physical memory information, the to-be-reserved physical memory information is analyzed and continuously split to obtain physical memory segments, and the physical memory segments are divided and aligned; dividing the virtual address space, and performing alignment processing on the divided virtual address space; performing memory mapping on the processed physical memory segment and a physical address space corresponding to the processed virtual address space; generating a page table by utilizing a physical address space corresponding to the mapped and processed virtual address space; when an access instruction of a user is obtained, the corresponding target physical address space is screened from the page table to determine the mapped target physical memory segment, so that the user accesses the target physical memory segment based on the user mode process, the range and capacity of the memory segment are dynamically configured, the stability of the memory during key load operation is guaranteed, and the memory access performance is improved.

The invention discloses a cache management method and device for memory access, equipment and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: obtaining a data read-write message of a central processing unit; detecting a data popularity type of an access address of the data read-write message; searching cache data corresponding to the access address from a target cache region; if the cache data is not found in the target cache region, sending a corresponding read-write request to a memory so as to find memory data corresponding to the access address from the memory; by setting the preset cache regions corresponding to the cold data and the hot data respectively, the cache can be partitioned according to the heat of the data, so that cache resources are reasonably allocated, the cost is reduced, the memory access efficiency and speed are improved, finer consistency control can be realized, and the cache hit rate and the system performance are improved; therefore, the required data is searched in the corresponding preset cache region according to the heat of the data, and the memory access speed is increased.

The invention discloses a server memory management system and a cluster system, and relates to the technical field of server memory management, the system identifies memory fault information of a server based on a fault reminding signal under the condition that a fault signal is received, and the current load state is determined based on operation data of the server. And matching the corresponding target repair strategy to perform fault repair on the server memory based on the target repair strategy. Therefore, the system can dynamically match different fault recovery strategies according to different fault scenes, so that the technical problem of poor flexibility of a memory fault recovery method in related technologies is solved, and the technical effects of improving the flexibility of memory fault recovery and the service operation stability of a server are achieved.

The invention discloses a federal large language model fine tuning method and system based on zero-order optimization, and relates to the technical field of artificial intelligence. A large language model is deployed in a federal learning framework, and the usage amount of model parameters during training and the transmission amount in the communication process are reduced by using low-rank decomposition, so that the training efficiency is improved. And then performing zero-order fine tuning on the local model to complete updating of the model. The technical problem of high memory requirement in the prior art is solved.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention discloses a large language model reasoning acceleration method and system based on dynamic sparsity, and the method comprises the steps: adding a parallel bypass prediction path on an original main calculation path of a network module supporting dynamic simplification of a structure of an original target large language model for the original target large language model; embedding a predictor for selective activation in the bypass prediction path, the predictor being used for generating a network sub-module to be activated according to an input vector of the network module so as to obtain a target large language model supporting two working modes of a dense mode and a sparse mode; when the sparse mode needs to be executed, a predictor embedded in the bypass prediction path is activated to obtain a fast reasoning result; and when the dense mode needs to be executed, closing the predictor embedded in the bypass prediction path to obtain a comprehensive reasoning result. The method aims at solving the problems that in the large language model reasoning process, video memory occupation is too high, and time consumption is too large, and optimal balance of calculation efficiency and resource consumption is achieved.

The invention discloses a data verification method and device for a redundant disk array, equipment and a medium, and relates to the technical field of data verification, when a data verification value of target data is generated, the target data is firstly divided into a plurality of data blocks, and correspondingly reference data is also divided into one-to-one corresponding reference blocks; then, the unit verification value of each data block is determined by taking the data block as a unit, and the data verification value of the target data is obtained through block-by-block calculation, so that the data verification of the target data is realized according to the data verification value, the memory occupation in the data verification value generation process is reduced, the storage requirement of temporary data is reduced, and the data verification efficiency is improved. The high memory overhead of processing the whole target data at a time is avoided, and the calculation efficiency of the data verification value is improved. The size of the data block can be flexibly adjusted according to requirements, the application range is wide, the flexibility is high, the check and problem positioning of the stored data are facilitated, and the troubleshooting of abnormal conditions such as data damage of the stored data is facilitated.

The embodiment of the invention provides a memory recovery method and device, equipment and a medium, the method is executed by computer equipment deployed with a container, and the container comprises a quality service agent component and a memory recovery agent component. The method comprises the following steps: determining a to-be-recycled memory node in a memory control group managed by a container through a quality service agent component, and transmitting the to-be-recycled memory node to a memory recycling agent component; obtaining a memory usage amount and a memory recovery index corresponding to the to-be-recovered memory node through the memory recovery agent component, and determining a memory recovery amount corresponding to the to-be-recovered memory node according to the memory usage amount and the memory recovery index; and calling a memory recovery interface through the memory recovery agent component, and recovering the physical memory in the memory node to be recovered based on the memory recovery amount. By implementing the embodiment of the invention, the memory resource utilization rate can be improved.

The invention provides a memory allocation method and device.The method comprises the steps that the maximum lexical element handling capacity sent by a host end is received, the maximum lexical element handling capacity is determined based on the length of an input sequence and the number of allocated experts, and the number of the allocated experts is the number of expert models allocated to all lexical elements; applying for a memory matched with the maximum lexical element handling capacity at a device end; dividing a target memory corresponding to each expert model from a memory based on the lexical element quantity processed by each expert model; and allocating each target memory to the corresponding expert model, wherein each target memory is used for storing the lexical elements processed by the corresponding expert model. According to the method, the maximum lexical element processing amount does not need to be synchronized at the host end, so that delay introduced by synchronous operation from the equipment end to the host end can be avoided, communication overhead in the memory allocation process can be reduced, the memory allocation efficiency and the overall processing speed can be improved, and finally the model reasoning performance of the equipment end is improved.

The embodiment of the invention provides a memory semantic processing method and device, equipment, a medium and a product. According to the method, a large memory semantic task can be split into a plurality of small sub-memory semantic tasks according to the memory semantic task and the core resource of the processor, so that the scale of the memory semantic task can be within the processing capacity of the processor, and the semantic bit width limitation of the processor can be broken through. According to the method, the sub-memory semantic tasks are allocated to the cores of the processor for parallel execution, so that the processing efficiency of the memory semantic tasks can be improved, and the problem that part of the cores are idle and the part of the cores are overloaded is avoided. In addition, by aggregating the messages corresponding to the sub-memory semantic tasks, a plurality of transmission tasks of a plurality of sub-memory semantic tasks can be completed through one-time transmission, consumption of transmission resources is reduced, and the efficiency of data operation is improved.

The invention provides a game resource optimization method and device based on a predictive algorithm and a storage medium. The method comprises the following steps: compiling a source code of a game voice tool into a bytecode file and generating an executable game voice tool main body; dividing the loading process of the non-core resources into a plurality of stages, and pre-loading the non-core resources through at least one background thread; generating a target resource list for a subsequent game scene by using a predictive algorithm; executing a loading operation on the target resource which is not loaded by utilizing a background thread, and executing a releasing operation on the loaded resource which is judged to be lower than a preset threshold value in the subsequent game scene by the predictive algorithm, wherein the use probability of the loaded resource is lower than the preset threshold value; a high execution priority is set for a voice communication module, and the loading priority of non-core resources and the task allocation order of background threads are dynamically adjusted according to the real-time condition of voice communication. According to the method and the device, memory resource utilization can be improved, CPU (Central Processing Unit) occupation is reduced, and game jamming caused by resource competition is reduced.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention provides a memory management method and device, a storage medium and an electronic device.The method comprises the steps that a heap memory of a process is applied from a system memory, and the process comprises a plurality of threads; aiming at a first thread of the process, the heap memory is adopted to construct a first local free table of the first thread, and the first local free table is used for locally storing an object pool of the first thread by adopting a thread local storage structure; and in response to a memory allocation request, allocating a first object for the first thread from the first local free table. Through the embodiment of the invention, the technical problem that memory fragments occur in dynamic memory allocation in related technologies is solved, and the memory management efficiency and performance are improved.

Embodiments of the present disclosure provide a memory management method, a device, a storage medium and a program product. The embodiments of the present disclosure provide a memory management mechanism relatively independent of an operating system, especially applicable to data scenarios where memory swapping is not desirable, or scenarios where independent memory isolation domains are required. Memory pages in a first memory pool are managed by means of a first memory pool management structure, and it is allowed to apply for a memory space from the memory pages in the first memory pool, the applied memory space is segmented into memory blocks of smaller granularity to create a second memory pool, and the memory blocks in the second memory pool are managed by means of a second memory pool management structure, so that the memory space can be allocated at the granularity of the memory blocks. Centralized memory management can be achieved, frequent swap-out of the memory pages in the first memory pool is avoided, system performance fluctuations are reduced, memory fragmentation can be reduced, the memory utilization rate is increased, and the system performance is improved.

The invention discloses an audio test data processing method, system and device based on zero-copy NIO and a dynamic sliding window, and the method comprises the following steps: S1, building a memory mapping file channel, and directly mapping an audio file to a process address space; s2, constructing a double-buffer processing pipeline, and realizing asynchronous decoupling of a collection thread and a calculation thread by adopting a producer-consumer mode; and S3, a dynamic sliding window mechanism is adopted to maintain a real-time audio data interval, and the window size is dynamically adjusted according to a television CPU load. According to the technical scheme of the invention, the problems of high memory occupation, high detection delay and low cross-application data reading efficiency existing in audio testing of a television system in a multi-application concurrent scene are solved.

The invention belongs to the technical field of distributed storage, and particularly discloses a CXL shared memory pool page thermal management method, a CXL shared memory pool page thermal management system and a CXL shared memory pool page thermal management program product, the position of a memory block in a shared memory pool can be dynamically adjusted according to the heat value of the memory block through a corresponding hot page scheduling strategy, and the use of memory resources is optimized; through the designed CXL memory sharing pool system, memory resources can be managed more flexibly, the sharing performance and the utilization rate of the memory are improved, and the overhead of data communication and data copying in the distributed parallel computing system is effectively reduced; the redundancy of memory resources can be reduced through a corresponding resource sharing mode, the complexity of a software stack is reduced, and the overall system cost is reduced; and the security among the private memory data is ensured while the data object is ensured to realize zero-copy sharing among the nodes as much as possible, that is, the security and isolation of the data are ensured while the data sharing efficiency is improved.

A full-electronic DFPT simulation optimization acceleration method is used for a full-electronic DFPT simulation calculation task, the simulation calculation task is divided into multiple batches of subtasks, and the method comprises the steps that through a batch processing merging strategy, the multiple independent subtasks are merged into batch tasks enabling GPU thread blocks to be fully loaded, so that the GPU thread utilization rate is increased; for the merged batch tasks, atomic or grid point attributes are uniformly stored in a structured memory allocation mode, and a lock page memory pool is pre-allocated to multiplex a transmission buffer area, so that the memory access efficiency is improved, and memory fragmentization is reduced; and constructing a calculation-transmission assembly line based on a multi-stream assembly line mechanism, and performing overlapped execution of calculation of the merged batch tasks and data transmission of the next batch by using a lock page memory buffer area. According to the method, the thread-level parallel efficiency of the GPU can be improved, the memory layout and multiplexing are optimized, the data transmission waiting time is shortened, and the performance of DFPT simulation under the high-throughput condition is improved.

The invention provides a memory management method and related equipment, and relates to the technical field of cloud computers. The method is applied to an aggregation host, and the aggregation host comprises a plurality of computing nodes; the method comprises the following steps: in response to starting an aggregation host, reserving a local memory for each computing node; after the aggregation host is started, creating a kernel thread for each computing node; and in response to starting the load in the aggregation host, copying a memory page table corresponding to the load from a computing fast link (CXL) memory to a local memory reserved by each computing node through a kernel thread of each computing node. According to the method and the device, the local memory is reserved for the computing node, the memory page table is copied to the local, the dependence on a CXL memory is reduced, and the reserved local memory is closer to the computing node, so that the access speed is higher, the memory access speed and efficiency can be improved, and the problem that the performance is limited when a super aggregation host runs a service with a high requirement on the memory is solved.

The invention discloses a high-capacity file encryption method and system based on block processing. According to the method, a high-capacity file is read and encrypted in blocks according to the fixed size, the situation that the high-capacity file is wholly loaded to a memory is avoided, memory occupation is reduced, and efficient encryption is achieved; two symmetric encryption algorithms of SM4 and AES are supported, and the corresponding algorithm is automatically identified and called during decryption by embedding an algorithm identifier in an encrypted file; and generating a check code for the encrypted file by using SM3 for integrity check before decryption. A file path coding mode irrelevant to a platform is adopted, a Unicode path is supported, and mainstream operating systems such as Windows and Linux can be compatible; and meanwhile, a buffer area and a multi-thread mechanism are introduced, so that file I / O operation and encryption calculation are executed in parallel, and the encryption efficiency is improved by utilizing the advantages of a multi-core processor. According to the method, the problems of high memory occupation, inconvenience in algorithm switching, poor cross-platform compatibility and low encryption efficiency of high-capacity file encryption are solved, and the method has a wide application prospect.

The invention discloses a memory configuration method and a related device, relates to the technical field of communication, and can improve the utilization rate of VM memory resources while ensuring the service performance. In the method, an infrastructure manager acquires memory demand information of a virtual machine (VM); the VM memory demand information comprises a VM exclusive memory value and a VM shared memory value of the target VM. And the infrastructure manager determines a target computing node of the target VM to be deployed from the at least one computing node. The memory resource condition of the target computing node is matched with the VM memory demand information, and the target computing node comprises exclusive memory resources and shared memory resources. And the infrastructure manager configures a VM exclusive memory and a VM shared memory for the target VM based on the VM memory demand information. Wherein the VM exclusive memory is allocated from exclusive memory resources of the target computing node, the size of the VM shared memory is consistent with the VM shared memory value, and the shared memory resources in the target computing node are used for scheduling the shared memory for the target VM when the target VM runs.

The invention provides a bandwidth adjustment method and device, a storage medium and electronic equipment. The method comprises the following steps: identifying a user state scene; wherein the user state scene is associated with the current process number and the current process identifier; and sending a bandwidth adjustment instruction to a system on chip (SOC), so that the SOC adjusts the memory bandwidth to the target bandwidth after determining the target bandwidth matched with the user state scene. According to the method and the device, the rationality of memory bandwidth allocation can be improved, the performance and the cruising ability of the electronic equipment can be improved, and the availability is high.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

The invention discloses a model reasoning acceleration method and device, electronic equipment and a nonvolatile storage medium. The method comprises the steps that in the process that a natural language processing model carries out general matrix calculation, a first matrix and a second matrix are divided into a plurality of blocks respectively, general matrix calculation is executed through an image processing unit, and the first matrix and the second matrix are matrixes needing general matrix calculation; loading the blocks from a global memory of the image processing unit to a shared memory of the image processing unit, and performing matrix operation by adopting threads corresponding to the blocks in the shared memory; and writing a result obtained by calculation of each thread back to a corresponding position in the global memory to obtain a matrix calculation result corresponding to matrix calculation of the first matrix and the second matrix. The technical problem of low model reasoning calculation efficiency caused by high memory access delay and low data reuse rate of a global memory of an image processing unit during reasoning of a large model in related technologies is solved.

A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

The invention provides a memory management method and device based on dynamic mapping and a medium, and relates to the field of data processing. The method comprises the following steps: processing data in different data organization formats by adopting different memory management modes; storing the received data in a first format and then converting the received data into a second format for storage; defining a plurality of logic memory regions corresponding to different processing stages, and establishing a mapping relationship between the logic memory regions and the physical memory unit; and in response to the periodic trigger signal, updating the mapping relationship to circularly change the logic region corresponding to the physical memory unit. According to the method, the memory utilization rate is improved through dynamic loop mapping, read-write conflicts are solved through format conversion, and the system performance and flexibility are improved.

The invention provides a memory management method, a storage medium and electronic equipment. The memory management method comprises the following steps: according to an execution sequence of each operator in a network calculation graph, obtaining a data flow sequence corresponding to each operator during operation, and constructing a memory demand sequence corresponding to the data flow sequence; creating a target memory block in the available memory space of the memory; and allocating a memory space for each memory demand according to the size of the target memory block and the sequence and life cycle of each memory demand in the memory demand sequence. The memory management method is favorable for improving the memory utilization rate.

A three-dimensional (3D) stacked chip package is described. The 3D stacked chip package includes a die having a wide input / output (IO) logic die area and a system-on-chip (SoC) logic die area isolated from the wide IO logic die area. The 3D stacked chip package also includes a memory stack on the wide IO logic area of the die. The 3D stacked chip package further includes a package substrate supporting the die.

The invention discloses a memory sharing method, which is applied to realizing memory sharing among computing nodes. In the memory sharing method, the memory access control table is arranged on the communication hardware of the source end node, and the authority of the source end node for accessing the memory of the remote node is recorded in the memory access control table, so that the access of the memory of the remote node is not influenced when the source end node triggers to access the memory of the remote node. The communication hardware queries the memory access control table to determine whether access to the memory of the far-end node can be executed or not, so that the range of accessing the far-end memory by the source-end node is effectively limited, and the security of memory sharing is improved.