247 results about "High memory" patented technology

The invention discloses a large language model reasoning acceleration method and system based on dynamic sparsity, and the method comprises the steps: adding a parallel bypass prediction path on an original main calculation path of a network module supporting dynamic simplification of a structure of an original target large language model for the original target large language model; embedding a predictor for selective activation in the bypass prediction path, the predictor being used for generating a network sub-module to be activated according to an input vector of the network module so as to obtain a target large language model supporting two working modes of a dense mode and a sparse mode; when the sparse mode needs to be executed, a predictor embedded in the bypass prediction path is activated to obtain a fast reasoning result; and when the dense mode needs to be executed, closing the predictor embedded in the bypass prediction path to obtain a comprehensive reasoning result. The method aims at solving the problems that in the large language model reasoning process, video memory occupation is too high, and time consumption is too large, and optimal balance of calculation efficiency and resource consumption is achieved.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

The invention discloses a model reasoning acceleration method and device, electronic equipment and a nonvolatile storage medium. The method comprises the steps that in the process that a natural language processing model carries out general matrix calculation, a first matrix and a second matrix are divided into a plurality of blocks respectively, general matrix calculation is executed through an image processing unit, and the first matrix and the second matrix are matrixes needing general matrix calculation; loading the blocks from a global memory of the image processing unit to a shared memory of the image processing unit, and performing matrix operation by adopting threads corresponding to the blocks in the shared memory; and writing a result obtained by calculation of each thread back to a corresponding position in the global memory to obtain a matrix calculation result corresponding to matrix calculation of the first matrix and the second matrix. The technical problem of low model reasoning calculation efficiency caused by high memory access delay and low data reuse rate of a global memory of an image processing unit during reasoning of a large model in related technologies is solved.

The invention provides a memory management method and device based on dynamic mapping and a medium, and relates to the field of data processing. The method comprises the following steps: processing data in different data organization formats by adopting different memory management modes; storing the received data in a first format and then converting the received data into a second format for storage; defining a plurality of logic memory regions corresponding to different processing stages, and establishing a mapping relationship between the logic memory regions and the physical memory unit; and in response to the periodic trigger signal, updating the mapping relationship to circularly change the logic region corresponding to the physical memory unit. According to the method, the memory utilization rate is improved through dynamic loop mapping, read-write conflicts are solved through format conversion, and the system performance and flexibility are improved.

Embodiments of the present disclosure provide a data transmission method, a device, a storage medium, and a program product. The embodiments of the present disclosure provide a software-implemented RDMA memory page fault solution: when acquiring data from a remote memory, a remote end maps a page-faulted virtual memory into a specific physical memory region, allows for the occurrence of a memory page fault in an RDMA process, and adds a memory page fault processing flow between a local end and the remote end to implement memory page fault processing; and when writing data into the remote memory, the remote end provides a shared virtual memory and a private virtual memory and exposes the shared virtual memory to the local end, the local end writes data into the shared virtual memory, and then a remote control object migrates the data to the private virtual memory, wherein memory page faults are allowed to occur and be processed during the migration. Since memory page faults are allowed to occur and page fault processing is supported, dynamic allocation of physical memory resources is supported during the RDMA process, thereby improving the utilization of memory resources while leveraging the advantages of RDMA.

The invention discloses a hardware architecture of a multi-port memory, and belongs to the technical field of computer memory hardware circuit design. The core comprises a plurality of input ports, a plurality of output ports, a plurality of linked list FIFOs (First In First Out), an input switch internet, a plurality of block memory units, a plurality of reordering queues and an output switch internet, wherein the input port is connected with the block memory unit through the linked list FIFO and the input switch internet, and the block memory unit is connected with the output port through the output switch internet and the reordering queue. By introducing an innovative hardware architecture and a network interconnection architecture, resource consumption is effectively reduced while efficient and large-scale ports are realized, and memory access efficiency and parallel processing capability are improved; the method can be widely applied to high-performance computing, heterogeneous computing, data center acceleration and other application scenes needing high concurrent access and high throughput of a large number of ports, and stable operation of the system can be ensured under the condition of high load.

Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and / or applications based on a memory access rate of the VMs / applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs / applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

The application relates to a bidirectional message processing method based on a unified user state channel and belongs to the technical field of virtualized communication, which solves the problems of CPU idle rate, high memory occupation and aggravated message processing delay caused by large-scale virtual function representative port polling. The method comprises the following steps: creating a virtual interface and an association relationship between the virtual interface and a hardware virtual function instance identifier in a user state virtual switch; establishing a user state channel as a shared bidirectional message transmission path between a plurality of hardware virtual function instances and the user state virtual switch; constructing extended metadata containing the hardware virtual function instance identifier, obtaining transmission data according to the extended metadata and a to-be-processed message; receiving and analyzing the transmission data through the user state channel to obtain the to-be-processed message and the extended metadata, and then determining a forwarding rule of the to-be-processed message and executing the forwarding of the to-be-processed message. The method realizes accelerated processing of the bidirectional message without polling and significantly reduces the memory resource occupation.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

The invention discloses a real-time storage optimization method based on block data, which relates to the technical field of big data processing and distributed storage, introduces a block data concept, realizes block-by-block writing, in-block ordering, block-level ordering and an intelligent flush trigger mechanism, and realizes real-time writing with high throughput, low delay and low memory occupation. The method specifically comprises the steps that block data is introduced into a data memory model to serve as a basic processing unit, multiple rows of data are aggregated into a block according to an aggregation key CKValue, row data in the block are sequenced according to a primary key PK, and write-in, namely aggregation is achieved; writing data, aggregating according to blocks, and uniformly sorting in the blocks; one block, namely multiple rows of data, generates an FRC file, and small files are reduced; exception processing: supporting block-level recovery to skip a failed block; the core problems of too high memory occupation, large CPU consumption, high writing delay and the like in a high-concurrency and high-throughput real-time writing scene can be solved, and the method is widely applied to scenes with extremely high requirements on data real-time performance and system stability.

A graphics processor, an instruction scheduling method, a terminal device and a medium, the graphics processor comprising: a scheduling module, an instruction cache module, a memory access dynamic scheduling module, a unified description cache module, a read-write module and a texture module, wherein: the memory access dynamic scheduling module is adapted to receive a first instruction transmitted by the scheduling module, obtain corresponding first description register information based on the first instruction; after determining that the first instruction supports dynamic scheduling based on the first description register information, determine whether to schedule the first instruction to the read-write module or the texture module based on the load state of the read-write module and the load state of the texture module; and the unified description cache module is adapted to feed back the first description register information to the memory access dynamic scheduling module based on the type of the first instruction. The above scheme can balance the load of the texture module and the read-write module, and improve the execution efficiency of the memory access instruction.

The invention provides a memory management method, electronic equipment and a related device. Each file in the one or more files in the terminal equipment is divided according to the size of the memory page, and the hot page set is a part of pages in a plurality of pages of the one or more files. When the terminal equipment performs memory management according to the hot page set, in a plurality of pages of the same file, the swap-in priority of pages belonging to the hot page set is higher than that of pages not belonging to the hot page set, and / or the swap-in priority of the pages belonging to the hot page set is higher than that of the pages belonging to the hot page set. The swap-out priorities of the pages not belonging to the hot page set are higher than the swap-out priorities of the pages belonging to the hot page set. According to the method, the hot page and the non-hot page in the file are distinguished by taking the page managed by the memory as the granularity instead of taking the file as the granularity, the hot page in the file can be reserved in the memory for a long time, the hit rate is increased, the non-hot page in the file can be prevented from occupying the memory for a long time, and the memory management efficiency is improved.

The invention discloses a starting control method and device of a host, a computer program and a storage medium, and is applied to the technical field of computers, and the starting control method comprises the following steps: performing memory parameter training of the host in a memory initialization stage of host power-on starting; when the memory parameter training fails, reading record data of memory parameter training failure from a set first storage space; based on the recorded data, whether the cumulative number of times of failure of memory parameter training reaches a preset number of times threshold within the latest first duration is judged; if not, generating record data of failure of the current memory parameter training, and storing the record data into the first storage space; the host is restarted, and memory parameter training of the host is carried out again; and if yes, starting control of the host is carried out according to a preset processing strategy. By applying the scheme of the invention, the starting control of the host can be effectively realized, the success rate of memory parameter training is improved, and the cost of manual operation and maintenance management is reduced.

This application discloses a memory management method and electronic device, relating to the field of computer technology. The method includes configuring the memory of any controller in a target cluster based on its current memory management parameters, running preset test cases on the controller to obtain performance indicators under the current memory configuration, determining the fitness function value of the controller under the current memory configuration, and then determining the controller's historically optimal memory management parameters. If the current iteration count has not reached an iteration count threshold, the memory management parameters are updated based on the target update speed, and iteration continues based on the updated memory management parameters. If the current iteration count reaches the iteration count threshold, the controller is configured with appropriate memory based on its historically optimal memory management parameters. This achieves dynamic memory management of the controller, resulting in improved memory utilization.

The present application relates to the field of scientific computing and GPU technology, and particularly relates to a GPU scan path optimization method.The method comprises: constructing a three-dimensional Stencil calculation GPU framework based on an optimal scan traversal path; based on the three-dimensional Stencil calculation GPU framework, constructing a scan traversal path mathematical model, abstracting the scan traversal path into an integer programming problem, taking the total memory access amount as an optimization target, and optimizing to obtain an optimal two-dimensional window scan traversal path.Compared with the traditional direct calculation, the method of the present application can significantly reduce the data transfer in the global memory, improve the utilization rate of the accessed data, i.e., improve the data reuse rate, reduce the invalid waiting caused by the data blocking and high memory delay of the calculation unit, and thus improve the calculation efficiency.

Methods, systems, and devices for increased memory reliability via redundancy are described. The memory system may receive a write command associated with data to be written to the memory system and write the data to a first portion of the memory system and a copy of the data to a second portion of the memory system based on the write command. After writing the data and the copy of the data, the memory system may receive a read command for the data and read the data from the first portion and the copy of the data from the second portion based on the read command. After reading the data and the copy of the data, the memory system may perform an error control operation on the data and the copy of the data and transmit the data or the copy of the data based on performing the error control operation.

This invention provides a method, apparatus, electronic device, and storage medium for programming memory chips. The method includes: determining whether a first logical storage unit and a second logical storage unit receive a corresponding chip select signal; if neither the first nor the second logical storage unit receives the corresponding chip select signal, determining the physical bit width of the memory chip; if the physical bit width is a first preset bit width, simultaneously performing programming operations on the first and second channels corresponding to the memory chip; if the physical bit width is a second preset bit width, performing programming operations on the first and second channels corresponding to the memory chip respectively; if either the first or second logical storage unit receives the corresponding chip select signal, programming the memory chip according to the chip select signal. This method improves the flexibility and efficiency of memory chip programming and effectively ensures the signal integrity of each channel of the memory chip.

The present application relates to a kind of 3D medical image mask self-encoding methods based on Mamba, to optimize the self-encoding task of processing 3D medical image, especially solve the problem of high memory requirement and computing resource consumption encountered when processing long sequence data.The Mamba network architecture introduced in the present application is used as the backbone network of the self-encoding model, to optimize the ability of the model to process long sequence data.Mamba is an advanced architecture based on state space model, which combines linear dynamic system theory and neural network concepts, effectively capturing the timing information and dynamic characteristics in the data.The core advantages of the present application include selective scanning algorithm, hardware-aware algorithm, and efficient data processing capability, especially when processing long sequence data.The present application not only reduces the burden of computing and storage, but also maintains or improves the accuracy and efficiency of image processing, especially suitable for processing 3D medical image data that requires a large amount of computation and high memory bandwidth.

Automated memory overclocking, including: increasing a memory frequency setting of a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting that passes the memory stability test; and generating a configuration file including the overclocked memory frequency setting.

The invention relates to a high-precision terrain generation method, device and equipment based on dynamic paging. The method comprises the following steps: dividing global terrain data into multi-level tiles, generating multi-level LOD data, and constructing a quadtree-hash table two-level index structure; based on an index structure, dynamically calculating an LOD level according to a camera view cone and a predicted viewpoint position, and generating a paging scheduling queue according to a priority weight model; asynchronously loading high-priority paging data in an independent loading thread, and performing cache management by adopting an LRU strategy; and carrying out real-time three-dimensional rendering on the loaded pages, realizing smooth switching by adopting interpolation transition, carrying out vertex weighted average and texture mixing processing on adjacent page boundaries, and carrying out cyclic mapping on longitude boundaries. According to the scheme, the problems of high memory occupation, low rendering efficiency, loading delay and the like in large-range high-precision terrain real-time generation are effectively solved, and the system performance and the user experience are improved.

The invention discloses a generation method and an analysis method for a data file of a question bank system. The method comprises the steps of generating a file overall structure; determining the position of a file header structure based on the overall file structure, and generating the file header structure based on the position of the file header structure; determining the position of a table index area based on the file header structure, generating a table index area structure based on the position of the table index area, determining the position of each metadata table in the table data area based on the table index area structure, and generating the table data area based on the position of each metadata table; determining the position of a file index area based on the file header structure, generating a file index area structure based on the position of the file index area, determining the position of each file resource in the file data area based on the file index area structure, and generating the file data area based on the position of each file resource. The technical problems that in the prior art, when a large number of small files are frequently and randomly accessed, decompression efficiency is low, memory occupation is high, and access delay is large are solved.

The invention relates to the technical field of memory management, in particular to a memory management optimization method based on resource environment limitation and related equipment. The method comprises the following steps: acquiring high-precision metadata in a memory operation event by hijacking a memory allocator interface; performing statistical evaluation according to the historical event data in combination with the high-precision metadata to obtain a memory behavior pattern feature vector; predicting the memory behavior pattern feature vector through a lightweight prediction model to obtain prediction request data; comparing the predicted request data with the fluctuation amplitude of the historical request to obtain a memory management strategy; and the memory management operation is optimized by monitoring the delay improvement rate and the fragment rate. The memory demand can be dynamically predicted, the allocation strategy can be adaptively adjusted, fragment accumulation can be inhibited, and real-time performance, low fragment and high memory utilization rate can be realized.

The invention relates to the technical field of an edge AI computing system of a graph neural network, and discloses a behavior space-time prediction method and system of an edge AI chip. The method comprises the following steps: extracting customers and shelf entities in real time based on a video stream, and constructing a dynamic space-time node set; generating a sparse heterogeneous space-time high-order correlation structure based on the node set; on the basis of the structure, through a topological graph neural network subjected to knowledge distillation, behavior prediction and loss prevention response of topology perception are executed; in order to solve the problems that traditional unstructured data processing is high in memory occupation, a traditional graph structure is difficult to capture multi-body interaction, edge model behavior discrimination precision is low and loss prevention response lags, edge chip resource constraints are adapted through model quantitative pruning, dynamic sparse pruning and multi-dimensional loss prevention evidence fusion, and the edge chip behavior discrimination precision is improved. The subtle behavior distinguishing precision and the real-time response speed are improved, and precise loss prevention and shelf layout optimization of an unmanned sales scene are achieved.

The invention relates to a memory table storage method and system, electronic equipment and a storage medium, and the method comprises the steps: if the timestamp of to-be-written data is greater than or equal to the maximum timestamp of written data in an ordered list, writing the to-be-written data into the ordered list, and updating the maximum timestamp; if the timestamp of the to-be-written data is smaller than the maximum timestamp, the to-be-written data is determined to be out-of-order data, the out-of-order data is written into an increment list, index information corresponding to the out-of-order data is inserted into an increment index tree, a key in the index information is the timestamp of the out-of-order data, and the out-of-order data is written into the increment index tree; the value in the index information comprises a first position of the out-of-order data in the increment list and a second position needing to be accessed before the first position is accessed, and the second position is the position of the target data in the ordered list; according to the method, the write-in performance of the memory table can be ensured while the query performance of the memory table is improved.

The embodiment of the invention discloses a memory access optimization method and device, electronic equipment, a storage medium and a program.The method comprises the steps that memory access data of an application program are dynamically monitored in real time, and remote memory access data of the application program are determined according to the memory access data of the application program; under the condition of determining that the remote memory access data of the application program meets the memory exchange condition, determining a target exchange local memory from local memories; determining a target exchange remote memory according to the remote memory access data of the application program; and performing memory exchange processing on the target exchange local memory and the target exchange remote memory. According to the technical scheme provided by the embodiment of the invention, efficient management of the memory can be realized in a high-memory-demand use scene, and memory access delay is reduced, so that the memory access efficiency is improved, and the overall performance of the system is improved.

The application provides a high-efficiency memory repair system and method based on a pooling memory, which comprises a memory test module for detecting UCE error addresses of a memory bank with cacheline as a granularity; a management module for converting memory error addresses into memory page addresses, and issuing repair commands for the memory page addresses; an address routing module for replacing and adding the memory page addresses into a routing table by using a routing lookup table algorithm to complete address repair, and for performing corresponding address conversion and routing to a port where the memory bank or the out-of-band storage module is located according to a repair state of a host memory address accessed; and an out-of-band storage module for repairing damaged memory with memory page as a granularity. The application achieves the effects of improving memory utilization efficiency and compatibility, and enhancing a memory RAS system by using the out-of-band storage module and the high-efficiency memory repair system with dynamically configurable memory page as a granularity.

The application discloses a memory management method and electronic equipment, and relates to the technical field of computers, including any controller of a target cluster, based on the current memory management parameter of the controller, performing corresponding memory configuration on the controller, and running a preset test case on the controller to obtain the performance index of the controller under the current memory configuration, determining the fitness function value of the controller under the current memory configuration, and then determining the self historical optimal memory management parameter of the controller; if the current iteration number does not reach the iteration number threshold, updating the memory management parameter based on a target update speed, and continuing iteration based on the updated memory management parameter; if the current iteration number reaches the iteration number threshold, performing corresponding memory configuration on the controller based on the self historical optimal memory management parameter of the controller. The application realizes dynamic management of the memory of the controller, and achieves the technical effect of improving the memory utilization rate.

Provided is a memory system and a method for improving bandwidth utilization in the memory system that includes receiving, at a host processor, a first read request from an input buffer, determining a combinable address range associated with the first read request, identifying one or more additional read requests in the input buffer having access addresses within the combinable address range, when one or more additional read requests are identified, modifying the first read request to represent the one or more additional read requests using a bit vector indicating their presence within the combinable address range, packing the modified first read request into a single slot of an outgoing flit, and transmitting the flit over an outgoing communication link.

The invention relates to a memory processing method and device, a memory management system, electronic equipment and a chip, and belongs to the technical field of memory management. The method comprises the following steps: in response to a memory processing request, performing memory allocation and memory recovery processing corresponding to the memory processing request by adopting a target memory; wherein the target memory is a memory allocated to target hardware of the electronic equipment by a processor of the electronic equipment; in response to the fact that the first number of idle memories in the target memories is smaller than a first set threshold value, requesting the processor to distribute the idle memories to the target hardware to increase the first number; and in response to the first number being greater than a second set threshold, releasing the idle memory to the processor to reduce the first number. Therefore, the processor can distribute the target memory to the target hardware, the target hardware can respond to the memory processing request, the target memory is adopted for memory distribution and recovery processing, the load of the processor can be remarkably reduced, and the memory processing efficiency is remarkably improved.